A data storage method and system for power secondary equipment based on FPGA

Abstract

The application discloses a kind of electric power secondary equipment storage chip data storage reliability design method and system, including the CPU chip of electric power secondary equipment is expanded processing module FPGA through PCIE interface, and DDRRAM storage chip is externally connected, CPU chip is placed in the mapping space of PCIE, and is transferred to the storage space of BLOCK RAM, the check code of the data needing to be checked in BLOCKRAM is obtained by calculating FPGA, and is transferred to PCIE mapping space, and the data storage reliability is judged by the check code calculated.This application is to solve the problem of power grid accident caused by the data displacement of existing electric power secondary equipment storage chip, by FPGA real-time fast calculation check code, and by CPU according to the check result real-time judging whether the related key data such as protection control program and fixed value parameter stored in internal RAM storage and FLASH storage chip is abnormal, after checking abnormal, immediately real-time recovery processing of abnormal data is carried out, to ensure the stable and reliable operation of electric power secondary equipment.

Description

[0001] This invention relates to the field of power system automation technology, and in particular to a data storage method and system for power secondary equipment based on FPGA. Background Technology

[0002] Secondary power equipment, such as relay protection devices, uses two types of memory: non-volatile memory (FLASH) and random access memory (RAM). RAM is further divided into static RAM (SRAM) and dynamic RAM (DRAM). In secondary power equipment, non-volatile memory is mainly used to store critical data such as programs, configurations, settings, events, and waveform recordings. Random access memory is mainly used for real-time reading and writing of instructions and data during program execution. SRAM is faster than DRAM. DRAM is generally used as main memory, while SRAM is generally used as a secondary cache. Abnormal changes in memory can cause problems such as relay protection device program corruption, setting failure, and loss of event waveform recordings. In severe cases, it may lead to device function lockout, device failure to operate, or device malfunction, affecting the safety of primary power grid equipment and even the stable operation of the entire power system. Secondary power equipment is the first line of defense for the safe operation of the power grid, a key technical means to ensure grid stability and equipment safety, and a core component of power grid operation.

[0003] In 2018, the power grid experienced several instances of malfunctions in protection devices caused by abnormal memory displacement. Therefore, fault-tolerant design to prevent abnormal memory displacement is a crucial measure to ensure the normal functioning of secondary power equipment and protect the safe and stable operation of the power grid. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the above and / or existing problems, the present invention is proposed.

[0006] Therefore, the present invention provides a data storage method and system for FPGA-based power secondary equipment, which can solve the problems mentioned in the background art.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] In a first aspect, embodiments of the present invention provide a data storage method for FPGA-based power secondary equipment, comprising: connecting a CPU chip of the power secondary equipment to a processing module FPGA via a PCIe interface; the CPU chip including RAM memory and FLASH memory; the CPU chip placing important data from its managed RAM memory and FLASH memory into its PCIe mapping space and transmitting it to the BLOCK RAM storage space inside the FPGA via the PCIe interface; enabling the FPGA to continuously calculate the checksum of the important data in the BLOCK RAM that needs to be verified in real time, and transmitting the checksum back to the corresponding PCIe mapping space of the CPU chip; the CPU chip comparing the checksum calculated by the FPGA to determine the reliability of data storage in its managed RAM memory and FLASH memory, and performing recovery processing on abnormal data.

[0009] As described in the present invention, the data storage method for FPGA-based power secondary equipment includes data stored in RAM chips in RAM memory and data stored in FLASH chips in FLASH memory.

[0010] As described in the present invention, the data storage method for secondary power equipment based on FPGA includes: calculating the check codes of important data that need to be verified in the BLOCKRAM by the FPGA, including calculating the check codes of data stored in the RAM chip and data stored in the FLASH chip.

[0011] As described in the present invention, the data storage method for secondary power equipment based on FPGA includes: the FPGA transmitting the calculated check code to the PCIe mapping space of the CPU chip through the PCIe interface, which includes: the FPGA transmitting the check code to the PCIe mapping space defined by the CPU chip in its external DDR RAM storage chip through the PCIe interface.

[0012] As described in the present invention, the method for data storage of FPGA-based power secondary equipment includes: determining the reliability of data storage by calculating the check code; indicating that the data stored in the RAM chip has changed position when the check code of the data stored in the RAM chip is inconsistent with the first correct check code; and indicating that the data stored in the FLASH chip has changed position when the check code of the data stored in the FLASH chip is inconsistent with the second correct check code.

[0013] As described in the present invention, the data storage method for secondary power equipment based on FPGA further includes: the CPU chip determining the reliability of the RAM chip stored data and the FLASH chip stored data it manages by comparing the check code calculated by the FPGA; when the RAM chip stored data changes position, the RAM chip stored data that has not changed position is copied from the PCLE mapping space to the RAM memory for corresponding abnormal data recovery.

[0014] As described in the present invention, the data storage method for FPGA-based power secondary equipment includes: when the data stored in the FLASH chip changes position, the data stored in the FLASH chip that has not changed position is copied from the PCLE mapping space to the FLASH memory to perform corresponding abnormal data recovery.

[0015] A data storage system for secondary power equipment based on FPGA, characterized in that: it includes,

[0016] The expansion module, wherein the CPU chip of the secondary power equipment is extended to the FPGA processing module via a PCIE interface and externally connected to a DDR RAM storage chip;

[0017] The calculation module calculates the checksum of the data to be verified in the BLOCK RAM by calculating the FPGA and then transmits it to the PCIE mapping space.

[0018] The verification module uses the calculated checksum to determine the reliability of data storage.

[0019] Secondly, embodiments of the present invention provide a data storage system for secondary power equipment based on FPGA, comprising: an expansion module, which extends the CPU chip of the secondary power equipment to an FPGA processing module and connects an external DDRRAM storage chip via a PCIe interface; a calculation module, which calculates the checksum of the data to be verified in the BLOCK RAM by the FPGA and transmits it to the PCIe mapping space; and a verification module, which determines the reliability of data storage by the calculated checksum.

[0020] Thirdly, embodiments of the present invention provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the FPGA-based power secondary equipment data storage method as described above.

[0021] The beneficial effects of this invention are as follows: This invention discloses a data storage reliability design method and system for FPGA-based power secondary equipment. The CPU chip of the power secondary equipment expands the processing module FPGA through a PCIe interface, and simultaneously connects to an external DDR RAM storage chip. The CPU chip maps the relevant data that needs to be verified in real time stored in the on-chip RAM storage chip and FLASH storage chip to the PCIe mapping space in the external DDR RAM of the CPU, and transmits the relevant data that needs to be verified in real time to the Block RAM storage space of the FPGA through the PCIe interface. The FPGA calculates the check code in real time and sends the calculation result back to the CPU in real time through the PCIe interface. The CPU judges whether the relevant data stored in the on-chip RAM storage and FLASH storage is abnormal based on the verification result and takes corresponding measures to avoid the impact of abnormal displacement of RAM and FLASH storage data on the functional failure of the power secondary equipment. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0023] Figure 1 The following is a detailed flowchart of a data storage reliability design method and system for FPGA-based power secondary equipment, provided as an embodiment of the present invention.

[0024] Figure 2 This invention provides a flowchart of a data storage reliability design method and system for FPGA-based power secondary equipment, including a RAM storage reliability design flowchart.

[0025] Figure 3 This invention provides a flowchart of a reliability design method and system for data storage of FPGA-based power secondary equipment, specifically for FLASH storage.

[0026] Figure 4 This is an internal structure diagram of a computer device for a data storage reliability design method and system based on FPGA for secondary power equipment, provided as an embodiment of the present invention. Detailed Implementation

[0027] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0028] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0029] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0030] This invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of this invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0031] Furthermore, in the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] Example 1

[0034] Reference Figure 1 and Figure 2This is the first embodiment of the present invention, which provides a method and system for designing data storage reliability of a power secondary equipment storage chip, including:

[0035] S1: The CPU chip of the secondary power equipment is connected to the FPGA processing module through the PCIe interface. The CPU chip includes RAM memory and FLASH memory.

[0036] The CPU chip of the secondary power equipment is extended to the FPGA processing module via a PCIe interface and connected to an external DDR RAM storage chip. The FPGA processing module includes BLOCK RAM storage space, and the DDR RAM storage chip includes PCIe mapping space.

[0037] Furthermore, in the system hardware design, the CPU processor is connected to an external FPGA chip via a PCIe communication interface, and an external DDR RAM chip is connected via a DDR interface. Redundancy processing is performed on the program data that needs to be verified in the CPU's on-chip RAM. The redundant program data are defined as Program A and Program B respectively. The external interface is implemented through hardware design principles.

[0038] S2: The CPU chip places important data from the RAM and FLASH memory it manages into its PCIe mapping space and then transmits it to the BLOCK RAM storage space inside the FPGA through the PCIe interface.

[0039] Specifically, the process involves placing the stored data into the PCIe mapping space of the CPU chip and transferring it to the storage space of the BLOCK RAM. The CPU chip stores data including data stored in the RAM chip and data stored in the FLASH chip. The CPU chip solves the problem of abnormal displacement of on-chip RAM storage and external FLASH storage chips through the redundant design of internal RAM program and FLASH storage data.

[0040] Furthermore, a space is allocated in the CPU's external DDR RAM as a PCIe mapping space for PCIe communication with the FPGA chip. The CPU chip puts the data stored in RAM and FLASH into the processing module FPGA, then calculates the verification code on the processing module FPGA, and stores the verification code in the Block RAM storage chip. It is important to note that the CPU defines the storage space for redundant data A and data B in DDR RAM as the PCIe mapping space, and periodically transfers the stored data A and data B to the Block RAM storage space inside the FPGA via the PCIe interface according to the interrupt execution cycle of the protection control calculation.

[0041] S3: Enables the FPGA to continuously calculate the checksum of the important data in the BLOCK RAM that needs to be verified in real time, and transmits the checksum back to the corresponding PCIe mapping space of the CPU chip.

[0042] The step of calculating the checksum of the data to be verified in the BLOCK RAM by calculating the FPGA includes calculating the redundant data in the BLOCK RAM storage space in real time according to the interrupt execution cycle of the protection control calculation.

[0043] The process of transmitting the checksum of the data to the PCIe mapping space includes transmitting the checksum calculation result to the PCIe mapping space defined by the CPU chip in DDR RAM via the PCIe bus.

[0044] Furthermore, the relevant verification data includes binary computer data such as program code data and configuration parameter data. The FPGA calculates the check code of the data to be verified in its Block RAM storage space in real time according to the interrupt execution cycle of the protection control calculation. The FPGA calculates the CRC23 check code in real time in a parallel manner and transmits the CRC23 check code calculation result to the PCIe mapping space in the external DDR RAM of the CPU chip through the PCIe bus.

[0045] S4: The CPU chip compares the checksum calculated by the FPGA to determine the reliability of data storage in the RAM and FLASH memory it manages, and performs recovery processing on abnormal data.

[0046] The reliability of data storage is determined by calculating checksums. This involves comparing the checksums of redundant data calculated in real-time by the CPU chip and the FPGA. If they don't match, it indicates that the redundant data has been displaced. Determining data storage reliability also includes copying the displaced data from the DDR space corresponding to the previously undisplaced data to the displaced storage area. When data stored in RAM or FLASH chips shifts at a certain location due to strong external disturbances, the checksums of the corresponding storage space calculated by the FPGA will inevitably change. The FPGA calculates the checksums for all storage spaces and transmits them to the CPU chip. The CPU chip then uses the checksums of the RAM and FLASH chips to determine whether the data stored in the RAM and FLASH chips it manages has shifted, thus determining the data's reliability.

[0047] Furthermore, abnormal memory displacement is mainly caused by manufacturing processes, scale and performance, as well as cosmic radiation. Manufacturing processes refer to the discovery that some memory failures are caused by alpha particle radiation, with the primary sources of alpha particles being the casing and solder. Scale and performance refer to the increasing size of integrated circuits, the decreasing size of transistors, and the increasing frequency, but also the decreasing voltage limits and narrowing noise tolerance of transistors, making processors more sensitive to crosstalk, voltage disturbances, and electromagnetic radiation. This leads to reduced reliability.

[0048] Furthermore, the CPU compares the current verification result with the previous verification result to determine in real time whether the relevant data in the on-chip RAM and FLASH storage has been abnormally shifted. It then takes countermeasures to recover the abnormal data using redundant storage data, thus avoiding the impact of abnormal shifts in RAM and FLASH storage data on the functional failure of secondary power equipment.

[0049] Specifically, the CPU chip periodically checks the checksum calculation results. Based on the checksum calculated in real time by the FPGA, the CPU chip determines whether redundant data A and data B have been shifted. If an abnormal shift is found, the data is copied from the RAM or FLASH storage area that has never been shifted to the RAM or FLASH storage area that has been shifted.

[0050] In one embodiment, a data storage method and system for FPGA-based power secondary equipment is characterized by comprising:

[0051] The expansion module extends the CPU chip of the secondary power equipment to an FPGA processing module via a PCIE interface and connects to an external DDR RAM storage chip.

[0052] The calculation module calculates the checksum of the data to be verified in the BLOCK RAM by calculating the FPGA and then transmits it to the PCIe mapping space.

[0053] The verification module determines the reliability of data storage by calculating a checksum. These modules can be embedded in hardware within the processor of a computer device or stored in software within the computer device's memory, allowing the processor to call and execute the corresponding operations.

[0054] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals. Wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0055] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: The CPU chip of the secondary power equipment is connected to the processing module FPGA via a PCIe interface. The CPU chip includes RAM and FLASH memory. The CPU chip places important data from its managed RAM and FLASH memory into its PCIe mapping space and transmits it to the BLOCKRAM storage space inside the FPGA via the PCIe interface. The FPGA then performs real-time cyclic calculation of the checksums of the important data in the BLOCKRAM that requires verification and transmits the checksums back to the corresponding PCIe mapping space of the CPU chip. The CPU chip compares the checksums calculated by the FPGA to determine the reliability of data storage in its managed RAM and FLASH memory and performs recovery processing on abnormal data.

[0056] In summary, this invention utilizes the CPU chip of a secondary power equipment to expand the processing module FPGA via a PCIe interface, while simultaneously connecting an external DDR RAM storage chip. The CPU chip maps the relevant data requiring real-time verification stored in the on-chip RAM and FLASH storage chips to the PCIe mapping space in the external DDR RAM of the CPU. This data is then transmitted to the Block RAM storage space of the FPGA via the PCIe interface. The FPGA rapidly calculates the checksum in real time and sends the calculation result back to the CPU via the PCIe interface. Based on the verification result, the CPU determines in real time whether the relevant data stored in the on-chip RAM and FLASH is abnormal and takes appropriate measures to prevent the secondary power equipment from malfunctioning due to abnormal data shifts in RAM and FLASH storage. Upon detecting an anomaly, the CPU immediately performs real-time recovery processing of the abnormal data, ensuring the stable and reliable operation of the secondary power equipment.

[0057] Example 2

[0058] Reference Figure 3 This is the second embodiment of the present invention, which provides a data storage method and system for FPGA-based power secondary equipment. In order to verify the beneficial effects of the present invention, specific experiments are conducted for scientific demonstration.

[0059] In secondary power equipment, non-volatile memory is mainly used to store critical data such as programs, configurations, settings, events, and waveform recordings; random access memory is mainly used for real-time reading and writing of instructions and data during program execution. SRAM is faster than DRAM. DRAM is generally used as main memory, while SRAM is generally used as a secondary cache. Once the memory experiences abnormal changes, it will cause problems such as damage to the relay protection device program, failure of settings, and loss of event waveform recordings. In severe cases, it may lead to accidents that affect the safety of primary power grid equipment and even the stable operation of the entire power system, such as device function lockout, device failure to operate, and device malfunction. Table 1 below shows the storage capacity and speed in detail:

[0060] Table 1. Storage Capacity and Speed ​​Details

[0061]

[0062] There are three main types of abnormal memory shifts: First, single-event upsets (SEE), where a single data bit in memory flips, causing data anomalies. This type of error is common in static random access memory (SRAM), dynamic random access memory (DRAM), and non-volatile memory (NRAM). Second, single-event transients (SETs), where a single data bit in memory experiences voltage or current fluctuations that are sampled and recorded by the circuit before being recovered. This type of abnormal shift mainly occurs in DRAM. Third, multi-bit flips, where multiple data bits in memory change simultaneously. SEE and SETs can generally be detected and corrected using hardware ECC (Error Checking and Correction). However, since most controllers do not have hardware ECC, and even if they do, it can only correct one-bit flip errors, redundant correction schemes must be designed for abnormal shifts in the storage medium to achieve system-level error detection and correction.

[0063] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A data storage method for secondary power equipment based on FPGA, characterized in that: include, The CPU chip of the secondary power equipment is connected to the FPGA processing module via a PCIe interface. The CPU chip includes RAM memory and FLASH memory. The CPU chip places important data from the RAM and FLASH memory it manages into its PCIe mapping space and then transmits it to the BLOCKRAM storage space inside the FPGA through the PCIe interface. This enables the FPGA to continuously calculate the checksum of the important data in the BLOCKRAM that needs to be verified in real time, and transmit the checksum back to the corresponding PCIe mapping space of the CPU chip; The CPU chip compares the checksum calculated by the FPGA to determine the reliability of data storage in the RAM and FLASH memory it manages, and then performs recovery processing on abnormal data.

2. The FPGA-based power secondary equipment data storage method as described in claim 1, characterized in that: The important data includes data stored in RAM chips in RAM memory and data stored in FLASH chips in FLASH memory.

3. The FPGA-based power secondary equipment data storage method as described in claim 2, characterized in that: FPGA calculates the checksums of important data in BLOCKRAM that need to be verified, including: calculating the checksums of data stored in RAM chips and data stored in FLASH chips.

4. The FPGA-based power secondary equipment data storage method as described in claim 1, characterized in that: The FPGA transmits the calculated checksum to the CPU chip's PCIe mapping space via the PCIe interface, including: the FPGA transmitting the checksum to the CPU chip's PCIe mapping space defined by its external DDRRAM memory chip via the PCIe interface.

5. The FPGA-based power secondary equipment data storage method as described in claim 3, characterized in that: The method of determining the reliability of data storage by calculating the check code includes: when the check code of the data stored in the RAM chip is inconsistent with the first correct check code, it indicates that the data stored in the RAM chip has been displaced; when the check code of the data stored in the FLASH chip is inconsistent with the second correct check code, it indicates that the data stored in the FLASH chip has been displaced.

6. The FPGA-based power secondary equipment data storage method as described in claim 5, characterized in that: The CPU chip determines the reliability of the RAM chip stored data and FLASH chip stored data by comparing the check code calculated by the FPGA. In addition, when the RAM chip stored data changes position, the CPU chip copies the RAM chip stored data that has not changed position from the PCLE mapping space to the RAM memory to perform the corresponding abnormal data recovery.

7. The FPGA-based power secondary equipment data storage method as described in claim 6, characterized in that: When the data stored in the FLASH chip changes position, the data stored in the FLASH chip that has not changed position is copied from the PCLE mapping space to the FLASH memory to perform the corresponding abnormal data recovery.

8. A data storage system for secondary power equipment based on FPGA, based on the data storage method for secondary power equipment based on FPGA as described in any one of claims 1 to 7, characterized in that: include, The expansion module extends the CPU chip of the secondary power equipment to an FPGA processing module via a PCIE interface and connects to an external DDRRAM storage chip. The calculation module calculates the checksum of the data to be verified in the BLOCKRAM by calculating the FPGA and then transmits it to the PCIe mapping space. The verification module determines the reliability of data storage by calculating the checksum.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the FPGA-based power secondary equipment data storage method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the FPGA-based power secondary equipment data storage method according to any one of claims 1 to 7.

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