A method for adaptive flash timing adjustment and a storage device thereof

Abstract

The application discloses a self-adaptive flash memory timing adjustment method and a storage device thereof, and relates to the technical field of storage. The method comprises the following steps: creating a statistical array composed of state acquisition times for different page types of flash memory, wherein the state acquisition times represent the execution times of reading states when the flash memory reaches a ready state; setting corresponding weights for different reading state times according to different page types; and adaptively and dynamically adjusting operation time according to the state acquisition times and the weights during actual operation instructions. The application counts the times of reading states in actual reading operation execution, sets corresponding weights for different reading state times, adaptively and dynamically adjusts the timing parameters of flash memory reading time, programming time and erasing time, realizes automatic optimal adaptation of different page types of different dies (LUN), considers the consumption of NAND life PEC, automatically adapts and adjusts at a certain PEC threshold, and thus the purpose of improving performance is achieved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a method for adaptive flash memory timing adjustment and a storage device thereof. Background Technology

[0002] Solid-state drives (SSDs) consist of NAND flash memory chips comprising several dies (or logic units, LUNs). Each die contains several planes, each plane contains several blocks, and each block contains several pages. The SSD controller sends read, write, and erase operation commands to the flash memory chips via a bus. To identify whether an operation command has been completed, a read status command is sent to the flash memory chip via the bus. The flash memory chip responds to the read status command by returning to either a ready or busy state.

[0003] Due to the physical characteristics of NAND itself, on the one hand, the read time tR of different types of flash memory media such as SLC, MLC, TLC, and QLC varies. Even within the same flash memory medium, the read time tR between different die dies (or LUNs) will also vary. On the other hand, for the same type of flash memory medium, the read time tR between different batches of die dies (or LUNs) will also vary. All of the above will cause the read time tR to vary in different scenarios.

[0004] The usual practice is to set the delay based on the typical read time (tR) of the NAND chip. However, this ignores the differences between different die (LUN) chips, and the tR setting needs to be readjusted when using different batches and different NAND chips. This makes it impossible to accurately set the tR to meet different needs and affects read performance. Summary of the Invention

[0005] Based on the above-mentioned technical problems, the present invention provides a method for adaptive flash memory timing adjustment, comprising:

[0006] A statistical array consisting of the number of times the flash memory acquires the status is created for different page types, where the number of times the read status is executed represents the number of times the flash memory is acquired to reach the ready state.

[0007] By assigning corresponding weights to the number of read states based on different page types;

[0008] The operation time is adaptively and dynamically adjusted based on the number of times and weights of status acquisition during actual operation instructions.

[0009] As described above, in an adaptive flash memory timing adjustment method, the statistical array consisting of the number of state acquisitions is created for flash memory of different page types, including:

[0010] Identify the storage media type, which includes at least one of MLC, TLC and QLC. MLC includes low pages and high pages, TLC includes low pages, middle pages and high pages, and QLC includes low pages, middle pages, high pages and super pages.

[0011] Based on the storage medium type and the corresponding page types, count the maximum number of times each page type performs a read operation;

[0012] Construct a statistics array that includes page type and number of read states;

[0013] The number of read states can be flexibly configured according to the scenario and media type. The number of read states can be equal to, greater than, or less than the maximum number of read states.

[0014] The adaptive flash timing adjustment method described above includes, in which, according to different page types, corresponding weights are assigned to different read states and their corresponding number of reads, including:

[0015] When the number of status reads is greater than or equal to 2, weighted arrays are set respectively;

[0016] Different weights are assigned to the number of read operations performed for different states.

[0017] In the adaptive flash timing adjustment method described above, the weight is set to increase as the number of read states increases.

[0018] The adaptive flash timing adjustment method described above further includes:

[0019] The reading state is weighted and calculated based on the number of read states and their weights, and a reading state tolerance threshold TH is set.

[0020] The operation time is dynamically adjusted based on whether the weighted calculation result exceeds the threshold.

[0021] The adaptive flash timing adjustment method described above includes, in which the weighted calculation based on the number of read states and their weights, the following steps are taken:

[0022] S1. Obtain the weighted array [a,b,c] consisting of the number of operation commands for reading the status and the corresponding weight array [w1,w2,w3], where a, b, and c are positive integers greater than or equal to 2;

[0023] S2. Calculate the average value of the final weighted array V = (a*w1 + b*w2 + c*w3) / (w1 + w2 + w3).

[0024] The adaptive flash memory timing adjustment method described above includes the following sub-steps for dynamically adjusting the operation time:

[0025] S3. Determine whether the average value V of the final weighted array is greater than or equal to the tolerance threshold TH. If the average value V of the final weighted array is greater than or equal to the tolerance threshold TH, then execute step S4. Otherwise, decrement the operation time by 1, record the direction as negative, and return to continue executing step S1.

[0026] S4. Determine if the direction of the previous record is positive. If it is, increment the operation time by 1, the recording direction is positive, and return to continue executing step S1. Otherwise, end. The initial previous direction is set to positive, and the unit of operation time is μs.

[0027] In the adaptive flash timing adjustment method described above, the adaptive adjustment is initiated once when the storage device is powered on for the first time.

[0028] The adaptive flash timing adjustment method described above further includes:

[0029] The system counts the number of erase / write operation cycles. If the count exceeds the cycle threshold, the system automatically adjusts the operation time accordingly.

[0030] The present invention also provides a storage device, comprising: a control unit and an NVM chip, wherein the control unit performs any of the methods described above.

[0031] The beneficial effects achieved by this invention are as follows: This invention counts the number of read statuses during actual read operations, and by setting corresponding weights for different read status counts, it adaptively and dynamically adjusts the timing parameters of flash memory operation time (e.g., read time, program time, erase time), automatically and optimally adapts to different page types of different die dies (LUNs), and takes into account the consumption of NAND lifetime PEC, automatically adapting and adjusting at certain PEC threshold intervals, thereby achieving the goal of improving performance. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0033] Figure 1 This document illustrates a functional block diagram of a NAND flash memory die (LUN) in a relevant embodiment of this application.

[0034] Figure 2This diagram illustrates a specific example of the page read command.

[0035] Figure 3 This diagram shows a NAND flash memory package containing four dies (LUNs).

[0036] Figure 4 This is a flowchart of an adaptive flash memory timing adjustment method provided in an embodiment of this application;

[0037] Figure 5 This is a histogram to count the number of times the ReadStatus state is executed for different page types in TLC (low page LP, middle page MP, high page UP).

[0038] Figure 6 The flowchart shows the specific operation steps for adjusting the read time tR.

[0039] Figure 7 A schematic diagram illustrating the positive and negative adaptive adjustment of the read time tR.

[0040] Figure 8 A histogram showing the number of read states executed after adjusting for read time tR. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but may be changed as will become clear upon understanding this disclosure, except for operations that must occur in a specific order. Furthermore, for the sake of clarity and conciseness, descriptions of features known upon understanding this disclosure may be omitted.

[0043] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many feasible ways of implementing the methods, apparatus, and / or systems described herein that will be clear upon understanding the disclosure of this application.

[0044] Throughout this specification, when a component is described as "connected to" or "attached to" another component, the component may be directly "connected to" or "attached to" the other component, or there may be one or more other components in between. Conversely, when an element is described as "directly connected to" or "directly attached to" another element, there may be no other elements in between. Similarly, similar expressions (e.g., "between" and "immediately between," and "adjacent to" and "closely adjacent to") should be interpreted in the same manner. As used herein, the term "and / or" includes any one of the relevant listed items or any combination of any two or more of the relevant listed items.

[0045] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0046] The terminology used herein is for the purpose of describing various examples only and is not intended to limit disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising,” “including,” and “having” indicate the presence of the features, quantities, operations, components, elements, and / or combinations thereof stated therein, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0047] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as understood based on the disclosure of this application and as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and in the disclosure of this application, and shall not be interpreted ideally or overly formally. The use of the term “may” herein with respect to examples or embodiments (e.g., regarding what an example or embodiment may include or implement) indicates the existence of at least one example or embodiment that includes or implements such a feature, while not all examples are limited thereto.

[0049] In a related embodiment of this application, Figure 1 This diagram illustrates a functional block diagram of a NAND flash memory die (LUN) in a relevant embodiment of this application. Figure 1 As shown, the storage device includes not only the memory composed of a NAND array, but also control components such as an I / O control module and a control logic module, as well as registers such as address registers, status registers, and command registers. When external devices communicate with the NAND flash memory, they use electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by the I / O control module. Commands received by the I / O control module are latched into a command register and transmitted to the control logic module to generate internal signals to control flash memory operations. Addresses are latched into an address register and then sent to the row decoder to select the row address, or to the column decoder to select the column address. Data is transferred byte-by-byte from the NAND array to the external device, or vice versa, through data registers and cache registers. The NAND array uses page-based operations for programming and reading, and block-based operations for erasing. In normal page operations, the data register and cache register operate as a single register. In cache operations, the data register and cache register operate independently to increase data throughput. The status register reports the status of the die (i.e., logic unit, LUN) operation.

[0050] In NAND operation, all commands and data must be communicated through DQ[7:0]. After executing a read command, the status of the read command needs to be confirmed. After the status register returns the NAND status as Ready, it indicates that the data has been read from the NAND array into the NAND cache register, and the data can be read from the NAND cache register for data transfer.

[0051] Figure 1 In the middle, the key signal functions are as follows:

[0052] DQ[7:0]: Data bus. There are two types of flash memory interfaces: Toggle and ONFI. ONFI 2.0 renames ToggleI / O[7:0] to DQ[7:0], with the same function.

[0053] ZQ: Reference pin for ZQ calibration;

[0054] DQS: Data strobe signal, used to indicate the latch position of data. DQS is a bidirectional bus with the same frequency as the clock signal;

[0055] CE# (ChipEnable): Chip enable signal, which enables a specific CE model and selects the target corresponding to that CE;

[0056] CLE (CommandLatchEnable): Command latch enable signal. When CLE is enabled, it means that command data will be read and transmitted to the NAND chip to perform corresponding operations, such as read, erase, or program.

[0057] ALE (AddressLatchEnable): Address latch signal, indicating the start of input address information;

[0058] W / R# (Write / Read): Write / read direction;

[0059] WE# (WriteEnable): Write enable signal: Enable indicates that data can be written;

[0060] RE# (ReadEnable): Read enable signal, enabling indicates that data can be written;

[0061] WP# (WriteProtection): Enables or disables programming and erasing operations for the NAND array;

[0062] R / B (Ready / Busy): This signal indicates the status of the target chip. When the chip is ready to receive or send data, the R / B signal will be in the "Ready" state, indicating that the device can transmit data. Conversely, when the chip is busy processing other tasks or cannot receive or send data, the R / B signal will be in the "Busy" state, indicating that the chip is temporarily unavailable.

[0063] Specifically, taking the page read command 00h-30h as an example, its function is to read data from a page in the NAND array into the corresponding cache register and then output the data. When the page read command is executed, 00h is first sent to the command register, followed by the required address cycle to the address register, and finally the 30h command is sent. The selected die (LUN) will enter a "Busy" state (RDY=0, ARDY=0) during data transmission for a duration of tR (ReadyTime, e.g., 100 milliseconds). To determine the progress of data transmission, the host can monitor the target's R / B signal or perform a read status operation (e.g., 70h).

[0064] Figure 2 A schematic diagram showing a specific example of the page read command is provided. Figure 2 As shown, after sending the page read command 00h-30h, the R / B signal line is pulled low and enters the Busy state. After a certain period of time, the command sequence 70h is sent to execute the ReadStatus. During the first status read, because the R / B signal line is still pulled low, the status register returns to 80h, and the die (LUN) is still in the Busy state (80h in binary is 10000000, that is, bits 6 and 5 of the status register RDY=0, ARDY=0, RDY is an abbreviation for Ready / Busy I / O; ARDY is an abbreviation for Ready / Busy Array). Therefore, it is necessary to wait for a period of time before executing the ReadStatus for the second time. At this time, the R / B signal line is pulled high, the status register returns to E0h, and the die (LUN) is in the Ready state (E0h in binary is 11100000, that is, bits 6 and 5 of the status register RDY=1, ARDY=1). At this time, data can be read from the buffer register for transmission.

[0065] A memory target is one or more logic units within a NAND flash memory package that share a chip enable (CE) signal. Each logic unit has a logic unit number (LUN). A NAND flash memory package may include one or more dies (LUNs), and multiple logic units within a NAND flash memory chip can independently execute commands and report status.

[0066] Figure 3 This diagram illustrates a single NAND flash memory package containing four dies (LUNs). Figure 3As shown, not every die (LUN) has its own set of DQ[7:0], but the die 0 (LUN0) in Target0 and Target2 share a set of DQ[7:0]_0, while the die 0 (LUN0) in Target1 and Target3 share another set of DQ[7:0]_1. Therefore, when multiple die dies (LUNs) share DQ[7:0], if multiple read status commands are required, and because read status commands have high priority, they may be frequently inserted into the gaps between valid read commands and data transmission execution, resulting in a waste of the DQ[7:0] data bus. The effective utilization rate of the DQ[7:0] data bus directly affects the read performance. Therefore, minimizing unnecessary command and data overhead on the DQ[7:0] data bus can improve performance.

[0067] For read operations, setting an appropriate delay for the first read status (ReadStatus) is crucial. If the delay is too short, multiple read status executions will be required; conversely, if the delay is too long, the read status of the memory chip cannot be detected in time for data output. Therefore, both excessively long and short delays negatively impact read performance. The processing time for a read operation mainly consists of two parts: data reading time and data transmission time. Read time refers to the delay mentioned earlier, which is the time tR it takes for the die (LUN) to go from a busy state to a ready state after sending the read command. From an operational perspective, it represents the time tR it takes to read data from the NAND memory cell to the cache register. Both dimensions ultimately represent the read time tR (or simply tR time), and its values ​​typically include typical and maximum values.

[0068] NAND non-volatile memory is distinguished by different media types based on the number of bits of data it can store, including SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell). With the development of technology, TLC and QLC media are currently the most common.

[0069] SLC: Each SLC cell stores only 1 bit of data (0 or 1). Due to the simplicity of the storage cell, SLC has the shortest time-to-read (tR) and the fastest read speed. The main advantages of SLC are high reliability and long lifespan, but its storage density is relatively low.

[0070] MLC: Each MLC storage cell stores 2 bits of data. Compared to SLC, MLC has a higher storage density. MLC makes a trade-off between read speed and lifespan, and its read / write time is relatively longer than that of SLC.

[0071] TLC: Each TLC cell stores 3 bits of data. Compared to MLC, TLC has a higher storage density. However, TLC has lower endurance than SLC and MLC, a relatively slower read speed, and a longer time-to-return (tR) time compared to SLC / MLC.

[0072] QLC: Each QLC cell stores 4 bits of data. QLC has higher storage density, but its read speed is slower and its lifespan is shorter compared to other media types, with a longer read / write time.

[0073] MLC, TLC, and QLC memory cells can store more than two bits of data, so they are further distinguished by different page types. The naming conventions for different NAND flash memory types differ. For example, using MLC, TLC, and QLC media:

[0074] MLC has two page types, typically divided into LowerPage (LP) and UpperPage (UP).

[0075] TCL typically uses three page types: Low Page (LP), Middle Page (MP), and Upper Page (UP).

[0076] QLC page types are typically divided into four types: LowPage (LP), MiddlePage (MP), UpperPage (UP), and ExtraPage (XP).

[0077] The read time (tR) varies slightly between different page types on the same medium. The read time (tR) may also differ between different die dies (LUNs). The read time (tR) may also differ between different batches of NAND die dies (LUNs). Similarly, the programming time (tPROG) and erase time (tBER) also exhibit similar issues between different batches of die dies (LUNs).

[0078] Therefore, for the different scenarios of read time tR mentioned above, the traditional approach is to set the delay based on the typical value of NAND chip read time tR to meet most tR conditions. However, in this case, the differences between different die (LUN) are ignored, and when using different batches of different NAND, the tR setting needs to be adjusted again, making it impossible to achieve precise setting of read time tR and adaptive operation.

[0079] Example 1

[0080] like Figure 4 As shown, Embodiment 1 of the present invention provides a method for adaptive flash memory timing adjustment, comprising:

[0081] Step 410: Create a statistical array consisting of the number of times the flash memory acquires the status for different page types, where the number of times the read status is acquired represents the number of times the read status is executed when the flash memory reaches the ready state.

[0082] Statistical arrays can be used to count the number of state acquisitions using various statistical methods, such as histograms, which can visually display the statistical results. Creating a statistical array for the number of state acquisitions for different page types of flash memory includes: identifying the storage medium type, which must include at least one of MLC, TLC, and QLC; MLC includes low and high pages; TLC includes low, middle, and high pages; and QLC includes low, middle, high pages, and superpages; calculating the maximum number of read state executions for each page type corresponding to the storage medium type; and constructing a statistical array that includes the page type and the number of read state executions. This array can be flexibly configured according to the scenario and media type, where the number of read state executions is equal to, greater than, or less than the maximum number of read state executions.

[0083] Taking TCL media with LowPage (LP), MiddlePage (MP), and UpperPage (UP) as an example, the initial read time tR of LowPage LP / MiddlePage MP / UpperPage UP is set to a typical value, assuming it is [tR_LP, tR_MP, tR_UP].

[0084] Taking read operations as an example, a histogram array of read status counts is created. This array contains two elements: the page type (PAGE_TYPE_CNT) and the maximum number of read statuses (RETRY_CNT_MAX). For example, the array can be represented as rsRetry[PAGE_TYPE_CNT][RETRY_CNT_MAX]. For each die die (LUN)'s LP / MP / UP operations, a certain number (e.g., 5000 times, balancing statistical accuracy and sampling time) of read status counts are recorded, forming a histogram.

[0085] Taking TLC media as an example, the page type PAGE_TYPE_CNT = 3, corresponding to the three types of TLC media: low page (LP), middle page (MP), and high page (UP). Table 1 lists the different interpretations of the number of times the ReadStatus command is executed to obtain the Ready status. The maximum number of times the ReadStatus command is executed, RETRY_CNT_MAX = 4, which represents the tolerance level for the number of times the ReadStatus command is executed. Commands exceeding 4 times are given the same weight in the calculation, indicating that read latency exceeds the expected threshold. The maximum number of times the ReadStatus command is executed, RETRY_CNT_MAX, can be flexibly adjusted according to different media types and business needs, such as decreasing or increasing. The maximum number of times, RETRY_CNT_MAX, is N-1.

[0086] Table 1

[0087]

[0088] Figure 5 To statistically analyze the number of ReadStatus executions for different page types in TLC (low page LP, middle page MP, high page UP), a histogram was created, with a maximum of 4 ReadStatus executions. The histogram shows that most read operations reach the Ready state with only one ReadStatus execution, while a small number of read operations require 2 to 4 ReadStatus executions.

[0089] Step 420: According to different page types, set corresponding weights for the number of read statuses (ReadStatus).

[0090] When the number of read statuses is greater than or equal to 2, that is, the number of read commands executed in the read status (ReadStatus) more than 2 times is defined as a weighted array [a, b, c]. Different weights are assigned to different numbers of read statuses, that is, the weights corresponding to the weighted array [a, b, c] are [w1, w2, w3]. The weights can be configured in ascending order as the number of read statuses increases, meaning that the more times the read status is executed, the less acceptable it is, and the larger the weight is. So:

[0091] The weighted average of the number of commands in two ReadStatus reads is a*w1;

[0092] The weighted average of the number of commands in the three ReadStatus reads is b*w2;

[0093] The weighted average of the number of commands with 4 or more read statuses (ReadStatus) is c*w3.

[0094] Calculate the average value V of the final weighted array [a,b,c] as V = (a*w1+b*w2+c*w3) / (w1+w2+w3), multiplying each element by its weight and then dividing by the sum of all weights.

[0095] It should be noted that the "corresponding weights" can be the same or different as needed. Taking the above example, the three weights corresponding to the 2nd to 4th read states should ideally increase in order, meaning that the more retries a state has, the less acceptable it is, and the higher its weight. The number of array partitions should be determined based on the actual RS statistics. The example counts 1, 2, 3, and 4 cases, but more or fewer cases can also be counted.

[0096] Taking the read operation as an example, the number of read commands that execute the read status (ReadStatus) more than twice can be defined as fewer, such as 2, or more, such as 5, such as weighted arrays [a,b] and [a,b,c,d,e]. Different weights are assigned to different read statuses, that is, the weights corresponding to the weighted array [a,b] are [w1,w2], while the weights corresponding to the weighted array [a,b,c,d,e] are [w1,w2,w3,w4,w5].

[0097] Step 430: Based on the number of times the status is acquired and the weight of the actual operation command, the operation time is adaptively and dynamically adjusted.

[0098] The actual operation instructions include one of the following: read operation, program operation, or erase operation; the corresponding adjustment of the operation time is the read time, program time, and erase time.

[0099] For example, for actual read operations, the read time tR is dynamically adjusted based on the number of times the actual read operation read status (ReadStatus) is executed, so as to automatically and optimally adapt to different page types of different die dies (LUNs).

[0100] The reading status is weighted and calculated based on the number of reads and their weights. A reading status tolerance threshold TH is set, and the operation time (such as the reading time tR) is dynamically adjusted based on whether the weighted calculation result exceeds the threshold.

[0101] like Figure 6 As shown, the weighted calculation based on the number of read states and their weights includes the following sub-steps:

[0102] Step 610: Obtain the weighted array [a,b,c] consisting of the number of operation commands for reading the status and the corresponding weight array [w1,w2,w3], where a, b, and c are positive integers greater than or equal to 2;

[0103] Step 620: Calculate the average value of the final weighted array V = (a*w1 + b*w2 + c*w3) / (w1 + w2 + w3).

[0104] Dynamically adjusting the operation time includes the following sub-steps:

[0105] Step 630: Determine whether the average value V of the final weighted array is greater than or equal to the tolerance threshold TH. If the average value V of the final weighted array is greater than or equal to the tolerance threshold TH, then proceed to step 640. Otherwise, tR-- (i.e., operation time minus 1) is recorded as negative, and the process returns to continue executing step 610.

[0106] Step 640: Determine if the direction of the previous record was positive (set the initial previous direction to positive). If yes, increment tR (i.e., increment the operation time by 1), indicating the recording direction is positive, and return to continue executing step 610; otherwise, end. The initial previous direction is set to positive, and the unit of operation time is μs.

[0107] Specifically, taking the read operation as an example, if the average value V of the weighted array [a,b,c] is greater than or equal to the tolerance threshold TH, it means that the read time tR is too short, resulting in too many read status operations occupying the command overhead of the DQ[7:0] line, affecting read performance. It is necessary to adjust tR in the positive direction, adding 1 to the read time tR, that is, waiting 1μs longer before executing the read status.

[0108] If the previous direction was positive, the read time tR is set to tR(pagetype) + 1, where tR(pagetype) is the read time tR corresponding to different page types: low page LP / middle page MP / high page UP. The initial value is the typical value of tR [tR_LP, tR_MP, tR_UP].

[0109] If the previous direction was positive, the read time tR is set to tR_xP+1, where tR_xP depends on LP / MP / UP.

[0110] If the previous direction was negative, it means that the read time tR oscillated here and has reached the optimal value. Set tR to tR(page type) + 1, where tR(page type) is determined according to different page types: low page LP / middle page MP / high page UP. Since tR has reached the optimal value, pause the statistical adjustment.

[0111] If the average value V of the weighted array [a,b,c] is less than the tolerance threshold TH, it means that the read time tR is too long and needs to be adjusted to reduce tR. The direction is negative, so the read time tR is decremented by 1, that is, tR is set to tR(pagetype)-1. Here, tR(pagetype) is determined according to different page types: low page LP / middle page MP / high page UP. The initial value is the typical value of tR [tR_LP,tR_MP,tR_UP].

[0112] Based on the adaptive adjustment method for reading time described above, the reading time tR can be cyclically adjusted in both positive and negative directions according to whether the average value V of the weighted array [a,b,c] exceeds the tolerance threshold TH. Figure 7 As shown, Figure 7 A schematic diagram illustrating the positive and negative adaptive adjustment of the read time tR.

[0113] It should also be noted that this adaptive flash timing adjustment method, for the start conditions of adaptive adjustment operation time, takes into account the consumption of NAND lifetime PEC, and can automatically adapt and adjust at certain PEC threshold intervals, thereby achieving the purpose of improving read performance.

[0114] The lifespan of NAND flash memory is typically expressed in program / erase cycles (PEC). Each erase / write operation causes some wear and tear on the NAND storage cells. Therefore, to avoid inaccuracies in single adjustments and the impact of NAND lifespan depletion, a PEC threshold can be set. Once a certain threshold is exceeded, histogram statistics are enabled to re-adjust the ideal read time tR.

[0115] Taking read operations as an example, histogram statistics can be adaptively adjusted once when the SSD storage system is powered on for the first time because of the overhead of some command return processing. The statistics end after the read time tR is adjusted to the ideal value. The adjusted tR does not need to be recorded and written to the NAND metadata area. Histogram statistics and read time tR adjustment are restarted after the system is powered off and powered on for the second time.

[0116] Considering the balance between system overhead and read time accuracy, it is optional to start statistics when the SSD storage system is powered on for the first time, and stop statistics after the read time tR is adjusted to the ideal value. The adjusted read time tR can be recorded and written to the NAND metadata area. After the system is powered off and powered on for the second time, it is not necessary to start histogram statistics and read time tR adjustment again, reducing the command overhead of power-on restart.

[0117] After power-on, the system begins to collect statistics on the information returned by read commands. After adjustment, to avoid wasting time (processing the rs information returned by each cmd's complete function), statistics are no longer collected. Adjustments are only made again at certain PEC stages. This is related to the code implementation. The read time tR is set to default tR during code initialization. After adjustment, the adjusted read time tR is not recorded, so it is lost upon power failure and needs to be re-enacted upon power-on. Alternatively, the adjusted read time tR can be recorded. However, in the code, this part is only for debugging and is not uploaded to the library, so it is unnecessary to add power failure recording.

[0118] Figure 8 A histogram of the number of read states executed after adjusting for read time tR, as shown below. Figure 8 As shown in the histogram, the number of read status operations is calculated after adjusting the read time tR. By adaptively adjusting the read time tR, most reads can reach the Ready state with only one read status operation (ReadStatus), while only a very small number of reads require more than two read status operations (Read Status). This reduces the possibility of read status commands frequently being inserted into valid read command and data transmission gaps, reduces waste of DQ lines, improves the effective utilization of DQ lines, and further enhances system read performance.

[0119] The adaptive read time adjustment tR provided by this invention can better adapt to differences between die (LUN) layers, such as the difference in read time tR between different die (LUN) layers of the same medium, and the difference in read time tR between different batches of die (LUN). As can be seen from the histogram of RS counts after tR adjustment, by adaptively adjusting the read time for different page types, over 98% of reads can achieve Ready status with a single RS count after optimization, improving the effective utilization of the DQ line and further enhancing system read performance.

[0120] In addition to adaptive adjustment of read time, this invention is also applicable to adaptive dynamic adjustment of flash memory programming time and erase time timing parameters, so as to automatically and optimally adapt to different page types of different die dies (LUNs), thereby improving SSD performance.

[0121] In a specific embodiment of the present invention, the adaptive positive and negative adjustment strategy of the read time tR is introduced using the page read command (00h-30h) as an example. Similarly, the programming time tPROG corresponding to the write page command (80h-10h) and the erase time tBER corresponding to the erase command (60h-D0h) can also adopt the adaptive positive and negative adjustment strategy of the present invention to improve performance.

[0122] In this embodiment of the application, a storage device (or solid-state storage device, etc.) is provided, comprising: a memory and a controller, wherein the controller executes an adaptive flash timing adjustment method according to any of the above method embodiments. The memory may be an NVM chip.

[0123] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute an adaptive flash timing adjustment method in any of the above method embodiments, performing the steps described above.

[0124] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for adaptive flash memory timing adjustment, characterized in that, include: A statistical array consisting of the number of times the flash memory acquires the status is created for different page types, where the number of times the read status is executed represents the number of times the flash memory is acquired to reach the ready state; Assign corresponding weights to the number of reads in different read states based on different page types; The operation time is adaptively and dynamically adjusted based on the number of times and weights of the status acquired during the actual operation command. Among them, assigning corresponding weights to the number of read states according to different page types includes: When the number of status reads is greater than or equal to 2, weighted arrays are set respectively; Different weights are assigned to perform different read operations. The adaptive and dynamic adjustment of the operation time based on the number and weight of the state acquisition during the actual operation instruction also includes: The reading state is weighted and calculated based on the number of read states and their weights, and a reading state tolerance threshold TH is set. The operation time is dynamically adjusted based on whether the weighted calculation result exceeds the tolerance threshold; The dynamic adjustment of the operation time based on whether the weighted calculation result exceeds the tolerance threshold includes: If the average value obtained from the weighted calculation is greater than or equal to the tolerance threshold, it is determined whether the previous recorded direction was positive. If it was positive, the operation time is incremented by 1. If the average value obtained from the weighted calculation is less than the tolerance threshold, the operation time is reduced by 1, and the unit of operation time is μs.

2. The adaptive flash memory timing adjustment method as described in claim 1, characterized in that, The statistical arrays consisting of the number of status acquisitions for flash memory of different page types include: Identify the storage media type, which includes at least one of MLC, TLC and QLC. MLC includes low pages and high pages, TLC includes low pages, middle pages and high pages, and QLC includes low pages, middle pages, high pages and super pages. Based on the storage medium type and the corresponding page types, count the maximum number of times each page type performs a read operation; Construct a statistics array that includes page type and number of read states; The number of read states can be flexibly configured according to the scenario and media type. The number of read states can be equal to, greater than, or less than the maximum number of read states.

3. The adaptive flash memory timing adjustment method as described in claim 1, characterized in that, The weight is set to increase as the number of read states increases.

4. The adaptive flash memory timing adjustment method as described in claim 1, characterized in that, The weighted calculation based on the number of read states and their respective weights includes: S1. Obtain the weighted array [a, b, c] consisting of the number of operation commands for reading the status and the corresponding weight array [w1, w2, w3], where a, b, and c are positive integers greater than or equal to 2; S2. Calculate the average value of the final weighted array V = (a w1 + b w2 + c w3) / (w1+w2+w3).

5. The adaptive flash memory timing adjustment method as described in claim 4, characterized in that, Dynamically adjusting the operation time includes the following sub-steps: S3. Determine whether the average value V of the final weighted array is greater than or equal to the tolerance threshold TH. If the average value V of the final weighted array is greater than or equal to the tolerance threshold TH, then execute step S4. Otherwise, decrement the operation time by 1, record the direction as negative, and return to continue executing step S1. S4. Determine if the direction of the previous record is positive. If it is, increment the operation time by 1, the record direction is positive, and return to continue executing step S1. Otherwise, end the process. The initial previous direction is set to positive.

6. The adaptive flash memory timing adjustment method as described in claim 1, characterized in that, When the storage device is powered on for the first time, it initiates an adaptive adjustment.

7. The adaptive flash memory timing adjustment method as described in claim 1, characterized in that, Also includes: The system counts the number of erase / write operation cycles. If the count exceeds the cycle threshold, the system automatically adjusts the operation time accordingly.

8. A storage device, characterized in that, include: A control unit and an NVM chip, wherein the control unit performs the method according to any one of claims 1-7.

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