A design method of charge pump phase-locked loop system

Abstract

A design method of charge pump phase-locked loop system, comprising the following steps: step 1, converting user requirements into CPPLL system indicators; step 2, determining the best CPPLL sub-module indicators by using MATLAB and Simulink; step 3, completing the CPPLL sub-module circuit design; step 4, completing the CPPLL system circuit design; step 5, extracting the pre-simulation noise source data of the CPPLL sub-module circuit by using Cadence, judging whether the pre-simulation indicators of the CPPLL system circuit meet the CPPLL system indicators, if yes, ending the front-end design of the CPPLL system; step 6, starting the back-end design of the CPPLL system, extracting the parasitic parameters of the CPPLL system; step 7, performing post-simulation on the CPPLL system circuit with the parasitic parameters by using the Cadence Spectre platform, judging whether all the post-simulation indicators of the CPPLL system meet the CPPLL system indicators, if yes, outputting the GDS file for tape-out. The method saves the design period of the charge pump phase-locked loop system and reduces the cost.

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