Sensitive amplifier circuit

Abstract

The application discloses a kind of sensitive amplifier circuits, bit line adjusting unit includes first NMOS tube;First NMOS tube is connected between data line node and bit line node, and there is feedback circuit between gate and source, comprising: first inverter, input and output are respectively connected bit line node and feedback node, the gate of first NMOS tube is feedback node.There is first switch between the power supply end of first inverter and power supply voltage.In addition, first current source and second switch are also connected between power supply voltage and feedback node.The reading process includes first stage and second stage connected in front and back.In first stage, first switch is turned on and second switch is turned off, and first inverter is used to realize strong feedback between bit line node and the feedback node, to ensure speed.In second stage, first switch is turned off and second switch is turned on, and first current source realizes fixed current feedback between bit line node and feedback node, to eliminate the influence of power supply voltage fluctuation on reading result.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a sense amplifier (SA) circuit. Background Technology

[0002] like Figure 1 The diagram shown is a circuit diagram of an existing sensitive amplifier circuit. The existing sensitive amplifier circuit includes a bit line adjustment unit 101 connected between bit line node A and data line node C.

[0003] The bit line adjustment unit 101 includes a first NMOS transistor MN101.

[0004] The drain of the first NMOS transistor MN101 is connected to the data line node C, and the source of the first NMOS transistor MN101 is connected to the bit line node A.

[0005] A feedback circuit is provided between the gate of the first NMOS transistor MN101 and the bit line node A. The feedback circuit is composed of an inverter 103. The inverter 103 is a CMOS inverter, including an NMOS transistor MN102 and a PMOS transistor MP101. The NMOS transistor MN102 acts as a pull-down transistor, and the PMOS transistor MP101 acts as a pull-up transistor.

[0006] The input terminal of inverter 103 is connected to the bit line node A, and the output terminal of inverter 103 is connected to the gate of the first NMOS transistor MN101 as a feedback node B.

[0007] The voltage of feedback node B is the inverted signal of bit line node A. When the voltage of node A is lower, the voltage of node B is higher; conversely, when the voltage of node A is higher, the voltage of node B is lower. However, the high-low level transition of node B is not abrupt, but rather involves a flipping region located near the clamping voltage Vclamp. When the voltage of node A is greater than Vclamp, the voltage of node B flips to a low level; conversely, when the voltage of node A is less than Vclamp, the voltage of node B flips to a high level. Figure 1 In this process, after pre-charging, the voltage at node A is clamped at the clamping voltage Vclamp. The first NMOS transistor MN101 is also called a clamp transistor.

[0008] During reading, bit line node A is connected to the selected memory cell 104, and the voltage of bit line node A is determined by the storage state of the memory cell 104.

[0009] A current source Iref is connected between the data line node C and the power supply voltage Vdd. The current of the current source Iref is used as a reference current for comparison with the cell current of the storage cell 104. During reading, a first output voltage is formed at the data line node C by comparing the current of the current source Iref with the cell current.

[0010] The sensitive amplifier circuit also includes an output unit 102; the first output voltage is input to the input terminal of the output unit 102 and outputs a second output voltage Soutb at the output terminal of the output unit 102. Figure 1 In this context, the output unit 102 includes a comparator.

[0011] The first output voltage is connected to the first input terminal, i.e., the + terminal, of the comparator.

[0012] The second input terminal of the comparator, i.e., the - terminal, is connected to the reference voltage Vref.

[0013] The comparator outputs the second output voltage Soutb.

[0014] Multiple memory cells 104 form a memory array. A decoding circuit 105 is also connected between the source of the first NMOS transistor MN101 and the bit line node A; during reading, the corresponding memory cell 104 is selected through the decoding circuit 105. The decoding circuit 105 consists of multiple switches plus decoding signals. Figure 1 The image only shows one NMOS transistor MN103 and two decoding signals YA and YB.

[0015] The storage cell 104 is a non-volatile storage cell, and the gate structure of the non-volatile storage cell includes a floating gate; the storage state of the non-volatile storage cell includes an erase state and a programming state.

[0016] When the non-volatile memory cell is an N-type device, it includes an N+ doped source region and a drain region. In the programming state, electrons are stored in the floating gate; in the erasure state, the electrons stored in the floating gate are removed.

[0017] In the programmed state, the non-volatile memory cell has a first threshold voltage, and the cell current is a first cell current.

[0018] In the erase state, the non-volatile memory cell has a second threshold voltage, and the cell current is a second cell current.

[0019] The first threshold voltage is greater than the second threshold voltage, and the first cell current is less than the second cell current. The larger the cell current, the lower the voltage of the bit line node A.

[0020] The information stored in the memory cell 104 in the programmed state is '0'. When reading '0', the cell current is the first cell current, and the voltage of bit line node A is relatively high. After being inverted by the inverter 103, the voltage of bit line node B will be relatively low. However, since bit line node B is directly connected to the power supply voltage Vdd through the pull-up transistor of the inverter 103, i.e., the PMOS transistor MP101, when the power supply voltage Vdd fluctuates, such as when a large overshoot occurs, the PMOS transistor MP101 will conduct, causing the voltage of bit line node B to also overshoot with the power supply voltage Vdd. This can easily cause the level of node B to flip, increasing the current of the first NMOS transistor MN101, and finally causing the output voltage Soutb to flip, resulting in a failure to read '0'. Summary of the Invention

[0021] This invention provides a sensitive amplifier circuit that can reduce the impact of power supply voltage fluctuations during the reading process while ensuring reading speed.

[0022] The sensitive amplifier circuit provided by the present invention includes a bit line adjustment unit connected between the bit line node and the data line node.

[0023] The bit line adjustment unit includes a first NMOS transistor.

[0024] The drain of the first NMOS transistor is connected to the data line node, and the source of the first NMOS transistor is connected to the bit line node.

[0025] A feedback circuit is provided between the gate of the first NMOS transistor and the bit line node, the feedback circuit comprising:

[0026] A first inverter, the input of which is connected to the bit line node, and the output of which is connected to the gate of the first NMOS transistor, the gate of which is the feedback node.

[0027] A first switch is connected between the power supply terminal of the first inverter and the power supply voltage, and the control terminal of the first switch is connected to a first control signal.

[0028] A first current source and a second switch are connected in series between the power supply voltage and the feedback node, and the control terminal of the second switch is connected to a second control signal.

[0029] The reading process includes a first stage and a second stage that are connected one after the other.

[0030] In the first stage, the first control signal turns on the first switch and the second control signal turns off the second switch. The first inverter is used to achieve strong feedback between the bit line node and the feedback node, ensuring that the bit line node reaches the bit line clamping voltage at a certain speed.

[0031] In the second stage, the first control signal disconnects the first switch and the second control signal turns the second switch on. The first current source provides fixed current feedback between the bit line node and the feedback node to eliminate the influence of power supply voltage fluctuations on the reading results.

[0032] A further improvement is that, during reading, the bit line node is connected to the selected memory cell.

[0033] A further improvement is that the first inverter is a CMOS inverter, comprising a second NMOS transistor and a first PMOS transistor.

[0034] The gate of the second NMOS transistor and the gate of the first PMOS transistor are both connected to the bit line node.

[0035] The source of the second NMOS transistor is grounded.

[0036] The drain of the second NMOS transistor and the drain of the first PMOS transistor are both connected to the feedback node.

[0037] The source of the first PMOS transistor serves as the power supply terminal of the first inverter.

[0038] A further improvement is that the first switch is composed of a second PMOS transistor, the drain of the second PMOS transistor is connected to the source of the first PMOS transistor, the source of the second PMOS transistor is connected to the power supply voltage, and the gate of the second PMOS transistor is the control terminal and connected to the first control signal.

[0039] A further improvement is that the second switch is composed of a third PMOS transistor, the gate of which is the control terminal and connected to the second control signal.

[0040] A further improvement is that the source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the first terminal of the first current source, and the second terminal of the first current source is connected to the feedback node.

[0041] A further improvement is that a second current source is connected between the data line node and the power supply voltage, and the current of the second current source is used as a reference current for comparison with the cell current of the memory cell; during reading, a first output voltage is formed at the data line node by comparing the current of the second current source and the cell current.

[0042] A further improvement is that the sensitive amplifier circuit also includes an output unit; the first output voltage is input to the input terminal of the output unit and outputs a second output voltage at the output terminal of the output unit.

[0043] A further improvement is that the output unit includes a comparator.

[0044] The first output voltage is connected to the first input terminal of the comparator.

[0045] The second input terminal of the comparator is connected to a reference voltage.

[0046] The comparator outputs the second output voltage.

[0047] A further improvement is that the storage unit is a non-volatile storage unit.

[0048] A further improvement is that multiple of the aforementioned storage units form a storage array.

[0049] A decoding circuit is also connected between the source of the first NMOS transistor and the bit line node; during reading, the corresponding memory cell is selected through the decoding circuit.

[0050] A further improvement is that the gate structure of the non-volatile memory cell includes a floating gate; the storage states of the non-volatile memory cell include an erase state and a programming state.

[0051] In the programmed state, the non-volatile memory cell has a first threshold voltage, and the cell current is a first cell current.

[0052] In the erase state, the non-volatile memory cell has a second threshold voltage, and the cell current is a second cell current.

[0053] The first threshold voltage is greater than the second threshold voltage, and the first unit current is less than the second unit current.

[0054] The larger the unit current, the lower the voltage of the bit line node.

[0055] A further improvement is that, in the second stage of the read operation, the voltage of the bit line node in the programming state is higher than the bit line clamping voltage, and the fixed current feedback stabilizes the voltage of the feedback node and keeps the first NMOS transistor off.

[0056] A further improvement is that the non-volatile memory cell is an N-type device, including an N+ doped source region and a drain region. In the programming state, electrons are stored in the floating gate; in the erasure state, the electrons stored in the floating gate are removed.

[0057] A further improvement is that the fluctuations in the power supply voltage include fluctuations caused by noise.

[0058] Unlike existing technologies where the feedback circuit of the bit line adjustment unit is composed of inverters, this invention improves upon existing feedback circuits by adding a first switch between the power supply terminal of the inverter and the power supply voltage, and controlling the first switch with a first control signal. A first current source controlled by a second switch is added between the feedback node and the power supply voltage, and the second switch is controlled by a second control signal. In the first stage of reading, the first switch is turned on and the second switch is turned off, allowing the feedback circuit to be implemented using an inverter. Because the inverter can achieve strong feedback, the reading speed is guaranteed. In the second stage of reading... With the first switch disconnected and the second switch turned on, the inverter is no longer connected to the power supply voltage, so the inverter cannot achieve pull-up. At this time, the feedback circuit achieves pull-up through the first current source. Since the current of the first current source is constant and unaffected by fluctuations in the power supply voltage, it can prevent the voltage of the feedback node from suddenly rising with the rise in the power supply voltage, and thus prevent the failure to read '0' when the voltage of the feedback node surges. Therefore, this invention can reduce the impact of power supply voltage fluctuations, such as noise, on the feedback circuit, and prevent read flipping caused by power supply voltage fluctuations. Thus, it can prevent noise and ensure the reading speed at the same time. Attached Figure Description

[0059] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0060] Figure 1 This is a circuit diagram of an existing sensitive amplifier circuit;

[0061] Figure 2 This is a circuit diagram of the sensitive amplifier circuit according to an embodiment of the present invention;

[0062] Figure 3 yes Figure 2 The waveform curve of the voltage at point B. Detailed Implementation

[0063] like Figure 2 The diagram shown is a circuit diagram of a sensitive amplifier circuit according to an embodiment of the present invention. The sensitive amplifier circuit according to an embodiment of the present invention includes a bit line adjustment unit 201 connected between bit line node A and data line node C.

[0064] The bit line adjustment unit 201 includes a first NMOS transistor MN201.

[0065] The drain of the first NMOS transistor MN201 is connected to the data line node C, and the source of the first NMOS transistor MN201 is connected to the bit line node A.

[0066] A feedback circuit is provided between the gate of the first NMOS transistor MN201 and the bit line node A, the feedback circuit including:

[0067] The first inverter 203 has its input terminal connected to the bit line node A and its output terminal connected to the gate of the first NMOS transistor MN201, which is the feedback node B.

[0068] In this embodiment of the invention, the first inverter 203 is a CMOS inverter, including a second NMOS transistor MN202 and a first PMOS transistor MP201.

[0069] The gate of the second NMOS transistor MN202 and the gate of the first PMOS transistor MP201 are both connected to the bit line node A.

[0070] The source of the second NMOS transistor MN202 is grounded.

[0071] The drain of the second NMOS transistor MN202 and the drain of the first PMOS transistor MP201 are both connected to the feedback node B.

[0072] The source of the first PMOS transistor MP201 serves as the power supply terminal of the first inverter 203.

[0073] A first switch is connected between the power supply terminal of the first inverter 203 and the power supply voltage Vdd, and the control terminal of the first switch is connected to the first control signal S1.

[0074] A first current source Iref1 and a second switch are connected in series between the power supply voltage Vdd and the feedback node B. The control terminal of the second switch is connected to the second control signal S2.

[0075] In this embodiment of the invention, the first switch is composed of a second PMOS transistor MP202. The drain of the second PMOS transistor MP202 is connected to the source of the first PMOS transistor MP201. The source of the second PMOS transistor MP202 is connected to the power supply voltage Vdd. The gate of the second PMOS transistor MP202 is a control terminal and is connected to the first control signal S1.

[0076] The second switch is composed of a third PMOS transistor MP203, and the gate of the third PMOS transistor MP203 is the control terminal and connected to the second control signal S2.

[0077] In this embodiment of the invention, the source of the third PMOS transistor MP203 is connected to the power supply voltage Vdd, the drain of the third PMOS transistor MP203 is connected to the first terminal of the first current source Iref1, and the second terminal of the first current source Iref1 is connected to the feedback node B.

[0078] The reading process includes a first stage and a second stage that are connected one after the other.

[0079] In the first stage, the first control signal S1 turns on the first switch and the second control signal S2 turns off the second switch. The first inverter 203 is used to achieve strong feedback between the bit line node A and the feedback node B, ensuring that the bit line node A reaches the bit line clamping voltage at a certain speed.

[0080] In the second stage, the first control signal S1 disconnects the first switch and the second control signal S2 turns the second switch on. The first current source Iref1 provides fixed current feedback between the bit line node A and the feedback node B to eliminate the influence of power supply voltage Vdd fluctuations on the reading results.

[0081] The fluctuations in the power supply voltage Vdd include fluctuations caused by noise.

[0082] In the second stage of the read, the voltage of the bit line node A in the programming state is higher than the bit line clamping voltage, and the fixed current feedback stabilizes the voltage of the feedback node B and keeps the first NMOS transistor MN201 off.

[0083] like Figure 3 As shown, is Figure 2 The waveform curve of the voltage at point B shows that during the first stage controlled by the first control signal S1, the voltage of the feedback node B rises rapidly, but there is an overshoot. This overshoot is caused by the overshoot of the power supply voltage Vdd.

[0084] Figure 3 In the second stage, following the first stage, the voltage of the feedback node B is stable, as it is controlled by the second control signal S2. This is because the fixed current feedback is used in the second stage.

[0085] In this embodiment of the invention, during reading, the bit line node A is connected to the selected storage unit 204.

[0086] A second current source Iref2 is connected between the data line node C and the power supply voltage Vdd. The current of the second current source Iref2 is used as a reference current for comparison with the cell current of the storage cell 204. During reading, a first output voltage is formed at the data line node C by comparing the current of the second current source Iref2 with the cell current.

[0087] The sensitive amplifier circuit further includes an output unit; the first output voltage is input to the input terminal of the output unit and outputs a second output voltage Soutb at the output terminal of the output unit.

[0088] The output unit includes a comparator 202.

[0089] The first output voltage is connected to the first input terminal of the comparator 202.

[0090] The second input terminal of the comparator 202 is connected to the reference voltage Vref.

[0091] The output terminal of the comparator 202 outputs the second output voltage Soutb.

[0092] The memory cell 204 is a non-volatile memory cell. Multiple memory cells 204 form a memory array. The non-volatile memory cell is an N-type device, including an N+ doped source region and a drain region. In the programming state, electrons are stored in the floating gate; in the erasure state, the electrons stored in the floating gate are removed. In other embodiments, the non-volatile memory cell can also be a P-type device, in which case both the source and drain regions are P+ doped.

[0093] A decoding circuit 205 is also connected between the source of the first NMOS transistor MN201 and the bit line node A; during reading, the corresponding memory cell 204 is selected through the decoding circuit 205. Figure 2 In the diagram, only one NMOS transistor MN203 is used to represent the decoding circuit. The decoding circuit 205 selects the memory cell to be read through the decoding signal. Figure 2 In this context, the decoded signal is represented by YB / YA, which means that the signal includes both YB and YA.

[0094] The gate structure of the non-volatile memory cell includes a floating gate; the storage states of the non-volatile memory cell include an erase state and a programmable state.

[0095] In the programmed state, the non-volatile memory cell has a first threshold voltage, and the cell current is a first cell current.

[0096] In the erase state, the non-volatile memory cell has a second threshold voltage, and the cell current is a second cell current.

[0097] The first threshold voltage is greater than the second threshold voltage, and the first unit current is less than the second unit current.

[0098] The larger the unit current, the lower the voltage of the bit line node A.

[0099] Unlike the feedback circuit of the existing bit line adjustment unit 201, which is composed of an inverter, this embodiment of the invention improves upon the existing feedback circuit by adding a first switch between the power supply terminal of the inverter and the power supply voltage Vdd, and controlling the first switch with a first control signal S1. A first current source Iref1, controlled by a second switch, is added between the feedback node B and the power supply voltage Vdd, and the second switch is controlled by a second control signal S2. In the first stage of reading, the first switch is turned on and the second switch is turned off, allowing the feedback circuit to be implemented using an inverter. Since the inverter can achieve strong feedback, the reading speed is guaranteed. In the second stage of reading, the first switch is turned off... With the switch on and the second switch turned on, the inverter is no longer connected to the power supply voltage Vdd, so the inverter cannot achieve pull-up. At this time, the feedback circuit achieves pull-up through the first current source Iref1. Since the current of the first current source Iref1 is constant and is not affected by the fluctuation of the power supply voltage Vdd, it can prevent the voltage of feedback node B from suddenly rising with the rise of the power supply voltage Vdd, and thus prevent the failure to read '0' when the voltage of feedback node B rises. Therefore, the embodiment of the present invention can reduce the influence of power supply voltage Vdd fluctuations, such as noise, on the feedback circuit, and prevent read flipping caused by the fluctuation of power supply voltage Vdd. Thus, it can prevent noise and ensure the reading speed at the same time.

[0100] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A sensitive amplifier circuit, characterized in that, include: Bit line adjustment unit connected between bit line nodes and data line nodes; The bit line adjustment unit includes a first NMOS transistor; The drain of the first NMOS transistor is connected to the data line node, and the source of the first NMOS transistor is connected to the bit line node; A feedback circuit is provided between the gate of the first NMOS transistor and the bit line node, the feedback circuit comprising: The first inverter has its input terminal connected to the bit line node and its output terminal connected to the gate of the first NMOS transistor, with the gate of the first NMOS transistor serving as the feedback node. A first switch is connected between the power supply terminal of the first inverter and the power supply voltage, and the control terminal of the first switch is connected to a first control signal. A first current source and a second switch are connected in series between the power supply voltage and the feedback node, and the control terminal of the second switch is connected to a second control signal. The reading process includes a first stage and a second stage that are connected consecutively; In the first stage, the first control signal turns on the first switch and the second control signal turns off the second switch. The first inverter is used to achieve strong feedback between the bit line node and the feedback node, ensuring that the bit line node reaches the bit line clamping voltage at a certain speed. In the second stage, the first control signal disconnects the first switch and the second control signal turns the second switch on. The first current source provides fixed current feedback between the bit line node and the feedback node to eliminate the influence of power supply voltage fluctuations on the reading results.

2. The sensitive amplifier circuit as described in claim 1, characterized in that: During reading, the bit line node is connected to the selected memory cell.

3. The sensitive amplifier circuit as described in claim 2, characterized in that: The first inverter is a CMOS inverter, comprising a second NMOS transistor and a first PMOS transistor; The gate of the second NMOS transistor and the gate of the first PMOS transistor are both connected to the bit line node; The source of the second NMOS transistor is grounded; The drain of the second NMOS transistor and the drain of the first PMOS transistor are both connected to the feedback node; The source of the first PMOS transistor serves as the power supply terminal of the first inverter.

4. The sensitive amplifier circuit as described in claim 3, characterized in that: The first switch is composed of a second PMOS transistor. The drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage. The gate of the second PMOS transistor is the control terminal and is connected to the first control signal.

5. The sensitive amplifier circuit as described in claim 1, characterized in that: The second switch is composed of a third PMOS transistor, the gate of which is the control terminal and connected to the second control signal.

6. The sensitive amplifier circuit as described in claim 5, characterized in that: The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the first terminal of the first current source, and the second terminal of the first current source is connected to the feedback node.

7. The sensitive amplifier circuit as described in claim 2, characterized in that: A second current source is connected between the data line node and the power supply voltage. The current of the second current source is used as a reference current for comparison with the cell current of the storage cell. During reading, a first output voltage is formed at the data line node by comparing the current of the second current source with the cell current.

8. The sensitive amplifier circuit as described in claim 7, characterized in that: The sensitive amplifier circuit also includes an output unit; the first output voltage is input to the input terminal of the output unit and outputs a second output voltage at the output terminal of the output unit.

9. The sensitive amplifier circuit as described in claim 8, characterized in that: The output unit includes a comparator; The first output voltage is connected to the first input terminal of the comparator; The second input terminal of the comparator is connected to a reference voltage; The comparator outputs the second output voltage.

10. The sensitive amplifier circuit as described in claim 7, characterized in that: The storage unit is a non-volatile storage unit.

11. The sensitive amplifier circuit as described in claim 10, characterized in that: The multiple storage units constitute a storage array; A decoding circuit is also connected between the source of the first NMOS transistor and the bit line node; during reading, the corresponding memory cell is selected through the decoding circuit.

12. The sensitive amplifier circuit as described in claim 10, characterized in that: The gate structure of the non-volatile memory cell includes a floating gate; the storage states of the non-volatile memory cell include an erase state and a programming state. In the programmed state, the non-volatile memory cell has a first threshold voltage, and the cell current is a first cell current; In the erased state, the non-volatile memory cell has a second threshold voltage, and the cell current is the second cell current; The first threshold voltage is greater than the second threshold voltage, and the first unit current is less than the second unit current; The larger the unit current, the lower the voltage of the bit line node.

13. The sensitive amplifier circuit as described in claim 12, characterized in that: In the second stage of the read, the voltage of the bit line node in the programming state is higher than the bit line clamping voltage, and the fixed current feedback stabilizes the voltage of the feedback node and keeps the first NMOS transistor off.

14. The sensitive amplifier circuit as described in claim 12, characterized in that: The non-volatile memory cell is an N-type device, including an N+ doped source region and a drain region. In the programming state, electrons are stored in the floating gate; in the erasure state, the electrons stored in the floating gate are removed.

15. The sensitive amplifier circuit as described in claim 1, characterized in that: The fluctuations in the power supply voltage include fluctuations caused by noise.

Images