A packaging mold, a packaging method, and a chip structure

Abstract

The application provides a packaging mold, a packaging method and a chip structure. The packaging mold comprises a first mold, the first mold comprises at least one first component part, a first side of the first component part has at least one first accommodating space and at least one second accommodating space, when the first mold is placed on the upper surface of the chip, the first accommodating space is isolated from the external environment, and the second accommodating space is communicated with the external environment. One first component part corresponds to one chip, the first accommodating space is used for accommodating a first semiconductor device of the chip, the second accommodating space is used for accommodating a second semiconductor device of the chip, and the types of the first semiconductor device and the second semiconductor device are different. The packaging mold provided in the application has a high yield when applied to the packaging of a radio frequency module.

Description

Technical Field

[0001] This application relates to the field of radio frequency module packaging, specifically to a packaging mold for improving yield, a packaging method for chip packaging using the packaging mold, and a chip structure packaged using the packaging method. Background Technology

[0002] An integrated solution, as opposed to a discrete solution, refers to a solution that integrates two or more discrete components, such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers, into a single module. This improves integration and performance while miniaturizing the components. Specifically, in integrated circuits, the RF front end refers to the RF device section located after the antenna and before the transceiver.

[0003] Currently, depending on the integration method, RF front-ends can be divided into FEMiD (integrated RF switch, filter and duplexer), PAMiD (integrated multi-mode multi-band power amplifier and FEMiD), LPAMiD (low noise amplifier, integrated multi-mode multi-band power amplifier and FEMiD), DiFEM (integrated RF switch and filter) and LFEM (integrated RF switch, low noise amplifier and filter), etc.

[0004] It should be noted that during the packaging process of RF modules, some components cannot be underfilled, such as SAW (Surface Acoustic Wave) filters, which need to be placed in a cavity to achieve resonant performance. Other components require underfilling, such as PA (Power Amplifier), LNA (Low Noise Amplifier), or SW (Radio Switch), to improve operational stability. Currently, the yield rate of RF module packaging methods that allow some components to be underfilled while others do not is still underdeveloped. Summary of the Invention

[0005] In view of this, this application provides a packaging mold, a packaging method for chip packaging using the packaging mold, and a chip structure packaged using the packaging method, as follows:

[0006] A packaging mold, used for chip packaging, comprising:

[0007] A first mold, comprising at least one first component, wherein a first side of the first component has at least one first receiving space and at least one second receiving space, wherein when the first mold is placed on the upper surface of the chip, the first receiving space is isolated from the external environment, and the second receiving space is connected to the external environment;

[0008] In this embodiment, one of the first components corresponds to one chip, the first accommodating space is used to accommodate a first semiconductor device of the chip, the second accommodating space is used to accommodate a second semiconductor device of the chip, and the first semiconductor device and the second semiconductor device are of different types.

[0009] Optionally, the second side of the first mold has a protrusion, and the second side of the first mold is opposite to the first side of the first mold;

[0010] Also includes:

[0011] The second mold has a groove on its first side, and when the second mold is placed on the second side of the first mold, the protrusion is located in the groove.

[0012] A third mold is located on the side of the first mold away from the second mold. When the packaging mold is applied to the packaging of a chip, the side surface of the third mold facing the first mold is used to place the chip.

[0013] Optionally, when the first mold includes at least two first components, the third mold includes at least two second components, one second component corresponds to at least one first component, and there is a gap between the at least two second components;

[0014] The packaging mold further includes at least one injection head located in the gap between two adjacent second components for injecting packaging material into the second receiving space.

[0015] Optionally, the chip includes at least one first semiconductor device and at least one second semiconductor device, with one first accommodating space accommodating one first semiconductor device and one second accommodating space accommodating one second semiconductor device.

[0016] Optionally, the chip includes at least one first semiconductor device and at least one second semiconductor device, with a first accommodating space accommodating the at least one first semiconductor device and a second accommodating space accommodating the at least one second semiconductor device.

[0017] An encapsulation method, the method comprising:

[0018] The chip to be packaged is assembled with any of the above-mentioned packaging molds. The chip to be packaged includes a substrate and a first semiconductor device and a second semiconductor device located on the substrate. The first semiconductor device is located in a first receiving space of the first mold, and the second semiconductor device is located in a second receiving space of the first mold.

[0019] Inject encapsulation material around the first mold until the encapsulation material fills the second receiving space;

[0020] The encapsulation material is cured to form a first encapsulation layer, and the encapsulation mold is removed.

[0021] A sealing film is formed on the side of the first encapsulation layer away from the substrate of the chip to be encapsulated. The sealing film at least covers the area where the first semiconductor device is located, forming a sealed cavity with the first encapsulation layer and the substrate. The first semiconductor device is located in the sealed cavity.

[0022] Optionally, when the packaging mold further includes a second mold and a third mold, assembling the chip to be packaged with the packaging mold of claim 1 includes:

[0023] The chip to be packaged is placed on the third mold, and the first mold is placed on the chip to be packaged. The second mold is located on the side of the first mold away from the chip to be packaged. The first semiconductor device on the chip to be packaged is located in the first receiving space of the first mold, and the second semiconductor device on the chip to be packaged is located in the second receiving space of the first mold. The protrusion on the first mold is located in the groove on the second mold.

[0024] Optionally, injecting encapsulation material around the perimeter of the first mold includes:

[0025] Encapsulation material is injected between the first mold and the third mold using an injection head.

[0026] Optionally, the method further includes:

[0027] A second encapsulation layer is formed on the side of the sealing film away from the substrate, and the second encapsulation layer covers the sealing film and the first encapsulation layer.

[0028] A chip structure, comprising:

[0029] A chip, the chip comprising a substrate and a first semiconductor device and a second semiconductor device located on the substrate;

[0030] A first packaging layer located in the region where the second semiconductor device is located on the chip, the first packaging layer covering the second semiconductor device;

[0031] A sealing film is located at least in the region where the first semiconductor device is located on the chip, the sealing film, the first encapsulation layer, and the substrate form a sealed cavity, and the first semiconductor device is located in the sealed cavity;

[0032] A second encapsulation layer is located on the side of the sealing film away from the substrate, and the second encapsulation layer covers the sealing film and the first encapsulation layer.

[0033] Optionally, the first semiconductor device includes an acoustic filter. When the packaging mold provided in this application is applied to chip packaging, the packaging mold is assembled with the chip and then directly filled, without the need for a pre-coating before filling with packaging material. This avoids the risk of failure due to pre-coating and subsequent film breaking, resulting in unfilled bottoms or damaged devices, leading to a higher yield.

[0034] In addition, when the packaging mold provided in this application is applied to the packaging of radio frequency modules, the packaging mold and the chip are assembled and then directly filled. The process is simple and avoids the complex film breaking process and the need for other tools introduced by first coating and then breaking the film before filling the packaging material. This simplifies the process, reduces the process complexity, and reduces the packaging cost.

[0035] Furthermore, when the packaging mold provided in this application is applied to chip packaging, the packaging mold is simple and readily available, can be reused, and has high packaging efficiency, further reducing packaging costs. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0038] Figure 1 This is a schematic diagram of the structure of an RF module after it has been coated with a film, before the underfilling of components that require underfilling.

[0039] Figure 2 This is a schematic diagram of the structure of a packaging mold provided in one embodiment of this application;

[0040] Figure 3This is a schematic diagram of the structure of a packaging mold provided in another embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of the second mold in the packaging mold provided in another embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the structure of the packaging mold provided in another embodiment of this application;

[0043] Figure 6 This is a layout diagram of a chip for a packaging mold application provided in one embodiment of this application;

[0044] Figure 7 A flowchart illustrating an embodiment of the encapsulation method provided in this application;

[0045] Figures 8-15 This is a schematic diagram of the various structures involved in the packaging method provided in one embodiment of this application. Detailed Implementation

[0046] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0047] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0048] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] As described in the background section, current RF module packaging methods have yields that need improvement when some components are not underfilled and others are underfilled.

[0050] Currently, the packaging method for RF modules involves coating the components with a film before underfilling them. After coating, the film is broken at the locations of the components requiring underfill, and then underfilling is performed. For example... Figure 1 As shown, Figure 1This is a schematic diagram of the structure of the RF module 01 after it has been coated with film 02, before the bottom filling of the components that need to be bottom-filled.

[0051] The above-mentioned packaging method has the risk of failure during the film breaking process, resulting in the bottom of the device that needs to be filled not being filled or the radio frequency device being damaged. In addition, the above-mentioned packaging method is relatively complex to perform, and requires other tools to assist in the film breaking process.

[0052] In view of this, embodiments of this application provide a packaging mold applied to chip packaging, such as... Figure 2 As shown, it includes:

[0053] The first mold 10 includes at least one first component 11. The first component 11 has at least one first receiving space 111 and at least one second receiving space 112 on its first side. When the first mold 10 is placed on the upper surface of the chip 20, the first receiving space 111 is isolated from the external environment, and the second receiving space 112 is connected to the external environment.

[0054] In this embodiment, one of the first components 11 corresponds to one chip 20. The first accommodating space 111 is used to accommodate the first semiconductor device 21 of the chip 20, and the second accommodating space 112 is used to accommodate the second semiconductor device 22 of the chip 20. The first semiconductor device 21 and the second semiconductor device 22 are of different types. Optionally, in one embodiment of this application, the first semiconductor device 21 is a semiconductor device that cannot be underfilled, and the second semiconductor device 22 is a semiconductor device that requires underfilling. Specifically, the first semiconductor device 21 can be a SAW (Surface Acoustic Wave) filter, and the second semiconductor device 22 can be a PA (Power Amplifier), LNA (Low Noise Amplifier), or SW (Radio Frequency Switch), etc. This application does not limit this and the specific choice depends on the circumstances.

[0055] Specifically, in one embodiment of this application, the following continues... Figure 2 As shown, the chip also includes a substrate 23, on which the first semiconductor device 21 and the second semiconductor device 22 are located.

[0056] The packaging mold provided in this application embodiment, when applied to chip packaging, has the first mold placed on the upper surface of the chip, the first semiconductor device on the chip located in the first accommodating space of the first mold, and the second semiconductor device on the chip located in the second accommodating space of the first mold. When filling the area where the second semiconductor device is located with packaging material, since the first mold is placed on the upper surface of the chip, the first accommodating space is isolated from the external environment, while the second accommodating space is connected to the outside, so that the packaging material can only fill the second accommodating space and will not enter the first accommodating space, thereby achieving bottom filling of the second semiconductor device and no bottom filling of the first semiconductor device.

[0057] Therefore, when the packaging mold provided in this application is applied to the packaging of radio frequency modules, the packaging mold is assembled with the radio frequency module and then directly filled, without the need to cover the film before filling the packaging material. This avoids the risk of failure to break the film due to the film breaking before filling the packaging material, resulting in the bottom of the device that needs to be filled not being filled or the radio frequency device being damaged. The yield is high.

[0058] In addition, when the packaging mold provided in this application is applied to the packaging of radio frequency modules, the packaging mold is assembled with the radio frequency module and then directly filled. The process is simple and avoids the complex film breaking process and the need for other tools introduced by first coating and then breaking the film before filling the packaging material. This simplifies the process, reduces the process complexity, and reduces the packaging cost.

[0059] Furthermore, when the packaging mold provided in this application embodiment is applied to the packaging of radio frequency modules, the packaging mold is simple and readily available, can be reused, and has high packaging efficiency, further reducing packaging costs.

[0060] Optionally, based on the above embodiments, in one embodiment of this application, the second accommodating space is connected to the external environment through the side wall of the first mold. Specifically, in this embodiment, a first opening may be provided on the side wall of the first mold corresponding to the position of the second accommodating space, so that the second accommodating space communicates with the external environment through the first opening on the side wall of the first mold. In another embodiment of this application, the second accommodating space is connected to the external environment through the second side surface of the first mold. Specifically, in this embodiment, a second opening may be provided on the second side surface of the first mold, so that the second accommodating space communicates with the external environment through the second opening. However, this application is not limited to this, and it depends on the specific situation. The second side of the first mold is opposite to the first side of the first mold.

[0061] Based on any of the above embodiments, in one embodiment of this application, such as Figure 2 and Figure 3 As shown, the second side of the first mold 10 has a protrusion 12, and the second side of the first mold is opposite to the first side of the first mold; optionally, in this embodiment, as... Figure 3 and Figure 4 As shown, the packaging mold further includes a second mold 30. The first side of the second mold 30 has a groove 31. When the second mold is placed on the second side of the first mold, the protrusion 12 is located in the groove 31. Through the cooperation of the protrusion and the groove, the second mold can fix the first mold in the plane where the chip is located, thus preventing the first mold from moving in the plane where the chip is located. This would prevent the packaging material from extending into the area where the first receiving space is located when the packaging mold is used to fill the second receiving space, thereby affecting the performance of the first semiconductor device.

[0062] Optionally, based on the above embodiments, in one embodiment of this application, such as Figure 5 As shown, the packaging mold also includes a third mold 40, which is located on the side of the first mold 10 away from the second mold 20. When the packaging mold is used for packaging the chip 20, the side surface of the third mold 40 facing the first mold 10 is used to place the chip 20.

[0063] It should be noted that, in this embodiment, the packaging mold can be used for packaging a single chip or for packaging multiple chips simultaneously. This application does not limit this, and it depends on the specific circumstances.

[0064] Optionally, in one embodiment of this application, the following continues... Figure 5 As shown, the first mold 10 includes at least two first components 11. In this embodiment, one first mold 10 is used for packaging at least two chips 20.

[0065] Based on the above embodiments, in one embodiment of this application, the third mold 40 includes at least two second components 41, each second component 41 corresponding to at least one first component 11, and there is a gap between the at least two second components 41; in this embodiment, the encapsulation mold further includes at least an injection head 50, the injection head 50 being located within the gap between two adjacent second components 41, for injecting encapsulation material into the second accommodating space. Specifically, in this embodiment, the injection head 50 injects encapsulation material into the second accommodating space by injecting encapsulation material into the gap between the first mold 10 and the third mold 40.

[0066] It should be noted that in the above embodiments, the first mold may further include at least three first components. In this embodiment, when the first mold includes at least three first components, the third mold may include two second components or at least three second components. That is, in this embodiment, the number of second components included in the third mold may be less than the number of first components included in the first mold or equal to the number of first components. This application does not limit this, as long as the number of second components included in the third mold is less than the number of first components included in the first mold.

[0067] Based on any of the above embodiments, in one embodiment of this application, the chip includes at least one first semiconductor device and at least one second semiconductor device, with at least one first semiconductor device accommodated in a first accommodating space and at least one second semiconductor device accommodated in a second accommodating space.

[0068] Specifically, in one embodiment of this application, the chip includes a first semiconductor device, and the first mold includes a first accommodating space for accommodating the first semiconductor device; in another embodiment of this application, the chip includes at least two first semiconductor devices, and the first mold includes a first accommodating space for simultaneously accommodating the at least two first semiconductor devices, i.e., in this embodiment, all the first semiconductor devices are located in the same first accommodating space; in yet another embodiment of this application, the chip includes at least three first semiconductor devices, and the first mold includes at least two first accommodating spaces. In this embodiment, one first accommodating space can accommodate one first semiconductor device, or at least two first semiconductor devices, or a partial first accommodating space can accommodate one semiconductor device and a partial first accommodating space can accommodate at least two first semiconductor devices. The number of first semiconductor devices accommodated in different first accommodating spaces can be the same or different, and this application does not limit this, but depends on the specific circumstances.

[0069] Similarly, the chip includes a second semiconductor device, and the first mold includes a second accommodating space for accommodating the second semiconductor device; in another embodiment of this application, the chip includes at least two second semiconductor devices, and the first mold includes a second accommodating space for simultaneously accommodating the at least two second semiconductor devices, that is, in this embodiment, all the second semiconductor devices are located in the same second accommodating space; in yet another embodiment of this application, the chip includes at least three second semiconductor devices, and the first mold includes at least two second accommodating spaces. In this embodiment, one second accommodating space can accommodate one second semiconductor device, or at least two second semiconductor devices, or a partial second accommodating space can accommodate one semiconductor device and a partial second accommodating space can accommodate at least two second semiconductor devices, that is, one second accommodating space can accommodate one second semiconductor device or at least two second semiconductor devices. The number of second semiconductor devices accommodated in different second accommodating spaces can be the same or different, and this application does not limit this, depending on the specific circumstances.

[0070] Specifically, in one embodiment of this application, such as Figure 6 As shown, the chip includes three SAW (Surface Acoustic Wave) filters, one PA (Power Amplifier), one LNA (Low Noise Amplifier), and one SW (Radio Switch). The three SAW filters are integrated in region A, and the PA, LNA, and SW are located in region B. In one implementation of this embodiment, the first mold includes a first accommodating space and a second accommodating space. The three SAW filters are all located in the same first accommodating space, and the PA, LNA, and SW are located in the same second accommodating space. In another implementation of this embodiment, the first mold includes three first accommodating spaces and three second accommodating spaces. The three SAW filters are each located in a separate first accommodating space, and the PA, LNA, and SW are each located in a separate second accommodating space. This application does not limit the implementation of these features; the specific implementation depends on the circumstances.

[0071] Furthermore, this application also provides a packaging method for packaging a chip using the packaging mold provided in any of the above embodiments. Specifically, as shown... Figure 7 As shown, the packaging method provided in this application embodiment includes:

[0072] S1: Assemble the chip to be packaged with the packaging mold described in claim 1, such as... Figure 8 As shown, the chip to be packaged includes a substrate 23 and a first semiconductor device 21 and a second semiconductor device 22 located on the substrate 23, as follows: Figure 9As shown, the first semiconductor device 21 is located in the first accommodating space of the first mold, and the second semiconductor device 22 is located in the second accommodating space of the first mold.

[0073] In one embodiment of this application, when the packaging mold further includes a second mold and a third mold, assembling the chip to be packaged 20 with the packaging mold 80 in this embodiment includes: placing the chip to be packaged 20 on the third mold 40 and placing the first mold 10 on the chip to be packaged 20, wherein the second mold 30 is located on the side of the first mold 10 away from the chip to be packaged 20, wherein the first semiconductor device on the chip to be packaged 20 is located in the first receiving space of the first mold 10, and the second semiconductor device of the chip to be packaged is located in the second receiving space of the first mold 10; the protrusion on the first mold 10 is located in the groove on the second mold 30.

[0074] It should also be noted that when the packaging mold does not include the third mold, the chip to be packaged can be placed on the support plate first, and then the packaging mold and the chip to be packaged can be assembled together. This application does not limit this, as long as the first mold and the chip to be packaged are assembled together, such that the first mold is located on the surface of the chip to be packaged, the first semiconductor device is located in the first accommodating space of the first mold, and the second semiconductor device of the chip to be packaged is located in the second accommodating space of the first mold.

[0075] The encapsulation method provided in the embodiments of this application is described below using the third mold as a support plate.

[0076] Continue as Figure 8 As shown, in one embodiment of this application, the first semiconductor device 21 located on the substrate 23 includes two SAWs, and the second semiconductor device 22 located on the substrate 23 includes a PA and an LNA. However, this application does not limit this and it depends on the specific circumstances.

[0077] S2; Inject encapsulation material around the first mold until the encapsulation material fills the second receiving space, such as... Figure 10 As shown, when the packaging mold includes a third mold, injecting packaging material around the first mold includes: injecting packaging material between the first mold 10 and the third mold 10 using the injection head of the packaging mold 80 until the packaging material fills the second receiving space. Optionally, the packaging material is an injection molding material, but this application does not limit it and it depends on the specific circumstances.

[0078] S3: As Figure 11As shown, the encapsulation material is cured to form a first encapsulation layer 100, and the encapsulation mold is removed.

[0079] S4: As Figure 12 and Figure 13 As shown, a sealing film 200 is formed on the side of the first encapsulation layer 100 away from the substrate 23 of the chip to be encapsulated. The sealing film 200 at least covers the area where the first semiconductor device 21 is located, and forms a sealed cavity 300 with the first encapsulation layer 100 and the substrate 23. The first semiconductor device 21 is located in the sealed cavity 300.

[0080] Optionally, in one embodiment of this application, such as Figure 12 As shown, the sealing film 200 covers the area where the first semiconductor device 21 is located, exposing the area where the second semiconductor device 22 is located; in another embodiment of this application, as Figure 13 As shown, the sealing film 200 not only covers the area where the first semiconductor device 21 is located, but also exposes the area where the second semiconductor device 22 is located. This application does not limit this, and it depends on the specific situation.

[0081] It should be noted that the sealing film is made of a different material than the first encapsulation layer. Optionally, the first sealing film may be a polymer film, such as a dry film, but this application does not limit this and it depends on the specific circumstances.

[0082] Based on any of the above embodiments, in one embodiment of this application, such as Figure 14 and Figure 15 As shown, the method also includes:

[0083] A second encapsulation layer 400 is formed on the side of the sealing film 200 away from the substrate 23, and the second encapsulation layer 400 covers the sealing film 200 and the first encapsulation layer 100.

[0084] Optionally, the second encapsulation layer may be made of the same material as the first encapsulation layer, such as injection molding material, but this application does not limit this and it depends on the specific circumstances.

[0085] Accordingly, embodiments of this application also provide a chip structure, such as... Figure 14 and Figure 15 As shown, it includes:

[0086] Chip 20, the chip 20 includes a substrate 23 and a first semiconductor device 21 and a second semiconductor device 22 located on the substrate 23;

[0087] A first encapsulation layer 100 is located on the chip 20 in the region where the second semiconductor device 22 is located, and the first encapsulation layer 100 covers the second semiconductor device 22;

[0088] A sealing film 200 is located at least in the area where the first semiconductor device 21 is located on the chip 20. The sealing film 200, together with the first encapsulation layer 100 and the substrate 23, forms a sealed cavity, and the first semiconductor device 21 is located in the sealed cavity 300.

[0089] A second encapsulation layer 400 is located on the side of the sealing film 200 away from the substrate 23, and the second encapsulation layer 400 covers the sealing film 200 and the first encapsulation layer 100.

[0090] Optionally, in one embodiment of this application, the first semiconductor device includes an acoustic filter, such as a SAW, but this application does not limit this and it depends on the specific circumstances.

[0091] When using the packaging method provided in this application embodiment to package a chip, the packaging mold is assembled with the chip to be packaged and then directly filled, without the need to apply a film before filling the packaging material. This avoids the risk of failure due to film breaking caused by applying a film before filling the packaging material, resulting in the bottom of the device not being filled or the device being damaged. The yield is high.

[0092] In addition, when using the packaging method provided in this application embodiment to package a chip, the packaging mold is assembled with the chip to be packaged and then directly filled. The process is simple and avoids the complex film breaking process and the need for other tools introduced by first coating and then breaking the film before filling the packaging material. This simplifies the process, reduces the complexity of the process, and reduces the packaging cost.

[0093] Furthermore, when using the packaging method provided in the embodiments of this application for chip packaging, the packaging mold is simple and readily available, can be reused, and has high packaging efficiency, further reducing packaging costs.

[0094] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0095] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0096] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0097] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0098] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging mold, used for chip packaging, characterized in that, include: A first mold, comprising at least one first component, wherein a first side of the first component has at least one first receiving space and at least one second receiving space, wherein when the first mold is placed on the upper surface of the chip, the first receiving space is isolated from the external environment, and the second receiving space is connected to the external environment; Wherein, one of the first components corresponds to one chip, the first accommodating space is used to accommodate a first semiconductor device of the chip, the second accommodating space is used to accommodate a second semiconductor device of the chip, and the first semiconductor device and the second semiconductor device are of different types; The method of using the packaging mold includes: The chip to be packaged is assembled with the packaging mold. The chip to be packaged includes a substrate and a first semiconductor device and a second semiconductor device located on the substrate. The first semiconductor device is located in a first receiving space of the first mold, and the second semiconductor device is located in a second receiving space of the first mold. Inject encapsulation material around the first mold until the encapsulation material fills the second receiving space; The encapsulation material is cured to form a first encapsulation layer, and the encapsulation mold is removed. A sealing film is formed on the side of the first encapsulation layer away from the substrate of the chip to be encapsulated. The sealing film at least covers the area where the first semiconductor device is located, forming a sealed cavity with the first encapsulation layer and the substrate. The first semiconductor device is located in the sealed cavity.

2. The packaging mold according to claim 1, characterized in that, The second side of the first mold has a protrusion, and the second side of the first mold is opposite to the first side of the first mold; Also includes: The second mold has a groove on its first side, and when the second mold is placed on the second side of the first mold, the protrusion is located in the groove. A third mold is located on the side of the first mold away from the second mold. When the packaging mold is applied to the packaging of a chip, the side surface of the third mold facing the first mold is used to place the chip.

3. The packaging mold according to claim 2, characterized in that, When the first mold includes at least two first components, the third mold includes at least two second components, one second component corresponds to at least one first component, and there is a gap between the at least two second components; The packaging mold further includes at least one injection head located in the gap between two adjacent second components for injecting packaging material into the second receiving space.

4. The packaging mold according to claim 1, characterized in that, The chip includes at least one first semiconductor device and at least one second semiconductor device, with one first accommodating space accommodating one first semiconductor device and one second accommodating space accommodating one second semiconductor device.

5. The packaging mold according to claim 1, characterized in that, The chip includes at least one first semiconductor device and at least one second semiconductor device, with a first accommodating space accommodating the at least one first semiconductor device and a second accommodating space accommodating the at least one second semiconductor device.

6. A packaging method, characterized in that, The method includes: The chip to be packaged is assembled with the packaging mold according to claim 1. The chip to be packaged includes a substrate and a first semiconductor device and a second semiconductor device located on the substrate. The first semiconductor device is located in a first receiving space of the first mold, and the second semiconductor device is located in a second receiving space of the first mold. Inject encapsulation material around the first mold until the encapsulation material fills the second receiving space; The encapsulation material is cured to form a first encapsulation layer, and the encapsulation mold is removed. A sealing film is formed on the side of the first encapsulation layer away from the substrate of the chip to be encapsulated. The sealing film at least covers the area where the first semiconductor device is located, forming a sealed cavity with the first encapsulation layer and the substrate. The first semiconductor device is located in the sealed cavity.

7. The packaging method according to claim 6, characterized in that, When the packaging mold further includes a second mold and a third mold, assembling the chip to be packaged with the packaging mold of claim 1 includes: The chip to be packaged is placed on the third mold, and the first mold is placed on the chip to be packaged. The second mold is located on the side of the first mold away from the chip to be packaged. The first semiconductor device on the chip to be packaged is located in the first receiving space of the first mold, and the second semiconductor device on the chip to be packaged is located in the second receiving space of the first mold. The protrusion on the first mold is located in the groove on the second mold.

8. The packaging method according to claim 7, characterized in that, Injecting encapsulation material around the perimeter of the first mold includes: Encapsulation material is injected between the first mold and the third mold using an injection head.

9. The packaging method according to claim 6, characterized in that, The method also includes: A second encapsulation layer is formed on the side of the sealing film away from the substrate, and the second encapsulation layer covers the sealing film and the first encapsulation layer.

10. A chip structure, characterized in that, include: A chip, the chip comprising a substrate and a first semiconductor device and a second semiconductor device located on the substrate; A first packaging layer located in the region where the second semiconductor device is located on the chip, the first packaging layer covering the second semiconductor device; A sealing film is located at least in the region where the first semiconductor device is located on the chip, the sealing film, the first encapsulation layer, and the substrate form a sealed cavity, and the first semiconductor device is located in the sealed cavity; A second encapsulation layer is located on the side of the sealing film away from the substrate, and the second encapsulation layer covers the sealing film and the first encapsulation layer; The packaging method for the chip structure includes: The chip to be packaged is assembled with the packaging mold according to claim 1. The chip to be packaged includes a substrate and a first semiconductor device and a second semiconductor device located on the substrate. The first semiconductor device is located in a first receiving space of the first mold, and the second semiconductor device is located in a second receiving space of the first mold. Inject encapsulation material around the first mold until the encapsulation material fills the second receiving space; The encapsulation material is cured to form a first encapsulation layer, and the encapsulation mold is removed. A sealing film is formed on the side of the first encapsulation layer away from the substrate of the chip to be encapsulated. The sealing film at least covers the area where the first semiconductor device is located, forming a sealed cavity with the first encapsulation layer and the substrate. The first semiconductor device is located in the sealed cavity.

11. The chip structure according to claim 10, characterized in that, The first semiconductor device includes an acoustic filter.

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