A high electron mobility transistor and its fabrication method

Abstract

This invention discloses a high electron mobility transistor and its fabrication method, relating to the field of semiconductor process technology. The high electron mobility transistor includes a silicon substrate and further comprises, sequentially stacked on the silicon substrate, a composite buffer layer, an AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer. The composite buffer layer includes an AlScN layer stacked on the silicon substrate and an AlSiN layer stacked on the AlScN layer. The Si doping concentration in the AlSiN layer gradually decreases from the side closest to the AlScN layer to the side furthest from the AlScN layer. This invention solves the technical problem in the prior art where growing a thick buffer layer on a silicon substrate to filter dislocations increases warpage and leads to crack formation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor process technology, and specifically to a high electron mobility transistor and its fabrication method. Background Technology

[0002] With the development of semiconductor processes and technologies, high electron mobility transistors (HEMTs) have become increasingly popular and are widely used in mobile phones, satellite television, and radar. HEMTs consist of a heterojunction formed by two materials with different band gaps, providing a channel for charge carriers. Gallium nitride (GaN)-based materials possess advantages such as a large band gap, high electron saturation drift velocity, good chemical stability, radiation resistance, high temperature resistance, and ease of heterojunction formation, making them the preferred material for manufacturing HEMT structures. GaN-based heterostructures exhibit high carrier concentration and electron mobility, low on-resistance, and the advantage of a wide band gap allows them to withstand very high operating voltages. Therefore, GaN-based HEMTs are suitable for applications such as high-temperature, high-frequency, high-power devices and low-loss switching devices.

[0003] GaN-based high electron mobility transistors typically use silicon (Si) as the substrate material for GaN growth. Due to the good thermal conductivity of Si substrates, large-size epitaxy can be achieved, especially 6-inch, 8-inch, and 12-inch epitaxial wafers, reducing production costs and giving them a significant market competitiveness. However, there is a large lattice mismatch and thermal mismatch between the Si substrate and the GaN epitaxial film. The large lattice mismatch generates film stress during epitaxial growth, leading to a decrease in the crystal quality of the epitaxial film. Furthermore, the large thermal mismatch generates thermal stress during cooling, causing cracks on the epitaxial film surface, which also degrades the crystal quality of the epitaxial layer. Therefore, extensive and in-depth research is still needed to fabricate high electron mobility transistors with even superior performance.

[0004] To reduce cracks, improve epitaxial layer quality, and lower defect density, it is first necessary to reduce impurity diffusion in the Si substrate, and secondly, to reduce the extension of dislocation density in the epitaxial layer. Common methods for reducing impurity diffusion in the Si substrate include pre-laying Al and AlN buffer layers, or pre-laying NH3 or SiN insertion layers. Common methods for reducing dislocation density in the epitaxial layer include gradually releasing the stress caused by lattice mismatch using graded AlGaN layers, AlN / AlGaN, and AlN / GaN superlattices. However, these methods generally filter dislocations by growing relatively thick epitaxial layers, which can improve the crystal quality of the epitaxial film. But as the epitaxial layer thickness increases, the warpage of the epitaxial wafer also increases. Excessive warpage can lead to surface cracks or even wafer splitting. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a high electron mobility transistor and a spin coating method, which aims to solve the technical problem that in the prior art, growing a thick buffer layer on a silicon substrate to filter dislocations will increase the warpage and lead to cracks.

[0006] One aspect of the present invention is to provide a high electron mobility transistor, comprising a silicon substrate, the high electron mobility transistor further comprising:

[0007] A composite buffer layer, an AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially stacked on the silicon substrate.

[0008] The composite buffer layer includes an AlScN layer stacked on the silicon substrate and an AlSiN layer stacked on the AlScN layer. The Si doping concentration in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows: The high electron mobility transistor provided by the present invention can effectively reduce warpage and improve crystal quality. Specifically, a composite buffer layer is stacked on a silicon substrate. The composite buffer layer includes an AlScN layer stacked on the silicon substrate and an AlSiN layer stacked on the AlScN layer. Sc doping can provide sufficient compressive stress to the AlScN layer, alleviating warpage. At the same time, Sc doping can effectively alleviate lattice mismatch between the substrate and the AlScN layer, reducing defect density and thus improving the crystal quality of the subsequently grown epitaxial layers. Since Sc doping will lead to a decrease in the roughness of the composite buffer layer, in the AlScN layer... An AlSiN layer is stacked on top of the N-layer. Due to the small atomic radius of Si, it can fill the dislocation defects generated by the AlScN layer, further improving the crystal quality of the composite buffer layer. In order to balance the roughness and the tensile stress brought by the AlSiN layer, the Si doping concentration in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer, so as to minimize the tensile stress brought by the AlSiN layer, alleviate the warpage of the composite buffer layer, reduce the roughness of the composite buffer layer, and improve the crystal quality of the subsequently grown epitaxial layer. This solves the technical problem that the growth of a thicker buffer layer on a silicon substrate to filter dislocations will increase the warpage and lead to cracks.

[0010] According to one aspect of the above technical solution, the thickness of the AlScN layer is 20nm-100nm.

[0011] According to one aspect of the above technical solution, the Sc component ratio of the AlScN layer is 0.1-0.4.

[0012] According to one aspect of the above technical solution, the thickness of the AlSiN layer is 50nm-150nm.

[0013] According to one aspect of the above technical solution, the Si doping concentration in the AlSiN layer is 1×10⁻⁶. 17 cm -3 -2×10 18 cm -3 .

[0014] According to one aspect of the above technical solution, the Si doping concentration in the AlSiN layer is from 1×10⁻⁶. 18 cm -3 Gradually decrease to 1×10 17 cm -3 .

[0015] According to one aspect of the above technical solution, the thickness of the AlGaN buffer layer is 1μm-3μm.

[0016] According to one aspect of the above technical solution, the doping element of the GaN high-resistivity buffer layer is carbon, and the carbon doping concentration is 1×10⁻⁶. 19 cm -3 -1×10 20 cm -3 .

[0017] Another aspect of the present invention is to provide a method for fabricating a high electron mobility transistor, characterized in that the fabrication method includes:

[0018] Provide a silicon substrate;

[0019] A composite buffer layer is grown on the silicon substrate. The composite buffer layer includes an AlScN layer grown on the silicon substrate and an AlSiN layer grown on the AlScN layer. The doping concentration of Si in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer.

[0020] An AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the composite buffer layer.

[0021] To further explain, the growth steps of the composite buffer layer include:

[0022] The temperature was adjusted to 1000℃-1200℃, the pressure was set to 30mbar-70mbar, and TMAl, Cp3Sc and NH3 and H2 were introduced at the same time as carrier gas to grow an AlScN layer with a thickness of 20nm-100nm on a silicon substrate.

[0023] The temperature is adjusted to 1000℃-1200℃, the pressure is set to 30mbar-70mbar, and TMAl, SiH4 and NH3 are introduced simultaneously. H2 is used as the carrier gas to grow an AlSiN layer with a thickness of 50nm-150nm on the AlScN layer. Attached Figure Description

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1 This is a schematic diagram of the high electron mobility transistor in the first embodiment of the present invention;

[0026] Figure 2 This is a flowchart of the method for fabricating a high electron mobility transistor according to the second embodiment of the present invention;

[0027] Component symbol explanation in the attached diagram:

[0028] Silicon substrate 100, composite buffer layer 200, AlScN layer 210, AlSiN layer 220, AlGaN buffer layer 300, GaN high-resistivity buffer layer 400, GaN channel layer 500, AlN insertion layer 600, AlGaN barrier layer 700, GaN capping layer 800. Detailed Implementation

[0029] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be more thorough and complete.

[0030] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," "upper," "lower," and similar expressions used herein are for illustrative purposes only and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0031] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0032] Please see Figure 1 The figure shows a high electron mobility transistor provided by the present invention. The high electron mobility transistor includes a silicon substrate 100, wherein the silicon substrate 100 has good thermal conductivity, enabling large-size epitaxy, particularly 6-inch, 8-inch, and 12-inch epitaxial wafers, which can reduce production costs and has significant market competitiveness. In this embodiment, the silicon substrate 100 is a P-type doped silicon substrate 100, wherein the silicon substrate 100 is a (111) crystal orientation silicon substrate 100, and its doping element is boron (B) with a doping concentration of 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 .

[0033] Furthermore, the high electron mobility transistor also includes: a composite buffer layer 200, an AlGaN buffer layer 300, a GaN high-resistivity buffer layer 400, a GaN channel layer 500, an AlN insertion layer 600, an AlGaN barrier layer 700 and a GaN capping layer 800 sequentially stacked on the silicon substrate 100.

[0034] The composite buffer layer 200 can reduce the carrier concentration of the substrate, decrease the lattice mismatch between the silicon substrate 100 and the subsequently grown epitaxial layer, improve the crystal quality of the subsequently grown epitaxial layer, reduce the defect density, and adjust the warpage, which is beneficial to improving the electrical performance of the device. The composite buffer layer 200 includes an AlScN layer 210 stacked on the silicon substrate 100 and an AlSiN layer 220 stacked on the AlScN layer 210.

[0035] Furthermore, since the AlScN layer 210 is directly stacked on the silicon substrate 100, it will be subjected to a large tensile stress. The doping of Sc can provide sufficient compressive stress for the AlScN layer 210 to alleviate the warpage. At the same time, the doping of Sc can effectively alleviate the lattice mismatch between the substrate and the AlScN layer 210, reduce the defect density, and thus improve the crystal quality of the subsequent epitaxial layer growth.

[0036] Preferably, the Sc component of the AlScN layer 210 has a composition ratio of 0.1-0.4. Since the higher the Sc component ratio, the more compressive stress is provided to the AlScN layer 210, the better the performance of alleviating the warpage of the epitaxial layer. However, the growth conditions of the AlScN layer 210 are relatively strict, and the growth pressure is relatively low. As the Sc component increases, the growth pressure decreases, the surface roughness of the AlScN layer 210 increases, and the defect density in the AlScN layer 210 increases.

[0037] Preferably, the thickness of the AlScN layer 210 is 20nm-100nm. The thickness of the AlScN layer 210 will affect the warpage, and the imbalance between tensile stress and compressive stress will lead to warpage, an increase in dislocation defects, and affect the growth of subsequent epitaxial layers.

[0038] In addition, an AlSiN layer 220 is stacked on top of the AlScN layer 210, and the Si doping concentration in the AlSiN layer 220 is 1×10⁻⁶. 17 cm -3 -2×10 18 cm -3 The doping of Si in AlSiN layer 220 can reduce the roughness of the interface of AlScN layer 210. Since Si has a small atomic radius, it can fill the dislocation defects generated in AlScN layer 210, thereby improving the crystal quality of composite buffer layer 200.

[0039] Furthermore, the higher the Si doping concentration in the AlSiN layer 220, the better the crystal quality. However, as the Si composition increases, the impact on warpage becomes greater, which will provide tensile stress. Therefore, in order to balance roughness and warpage, the Si doping concentration in the AlSiN layer 220 gradually decreases from the side closer to the AlScN layer 210 to the side farther away from the AlScN layer 210, so as to minimize the tensile stress brought by the AlSiN layer 220.

[0040] Preferably, the doping concentration is from 1×10 18 cm -3 Gradually decrease to 1×10 17 cm -3 The higher the Sc composition of AlScN layer 210, the more convex the warpage; the higher the Si doping concentration in Si-doped AlSiN layer 220, the more concave the warpage. By adjusting the Sc composition of AlScN layer 210 and the Si doping concentration in AlSiN layer 220, the warpage of the epitaxial layer can be alleviated, and the roughness of the composite buffer layer 200 can be reduced, thereby improving the crystal quality of the subsequently grown epitaxial layer.

[0041] Preferably, the thickness of the AlSiN layer 220 is 50nm-150nm; similarly, the thickness of the AlSiN layer 220 will affect the warpage, and the imbalance between tensile stress and compressive stress will lead to warpage, an increase in dislocation defects, and affect the growth of subsequent epitaxial layers.

[0042] An AlGaN buffer layer 300 is provided on the composite buffer layer 200. The thickness of the AlGaN buffer layer 300 is 1μm-3μm, and the Al component accounts for 0.1-0.8%.

[0043] Furthermore, a GaN high-resistivity buffer layer 400 is stacked on the AlGaN buffer layer 300 to block the diffusion of two-dimensional electron gas toward the silicon substrate 100. The GaN high-resistivity buffer layer 400 is doped with carbon, and the carbon doping concentration is 1×10⁻⁶. 19 cm -3 -1×10 20 cm -3 The thickness of the GaN high-resistivity buffer layer 400 is 1μm-2μm.

[0044] Furthermore, a GaN channel layer 500 is stacked on the GaN high-resistivity buffer layer 400 to form a polarization effect with the AlGaN barrier layer 700 to generate a two-dimensional electron gas. The thickness of the GaN channel layer 500 is 300nm-600nm.

[0045] Furthermore, an AlN insertion layer 600 is stacked on the GaN channel layer 500 to reduce interface scattering between the GaN channel layer 500 and the AlGaN barrier layer 700, thereby improving electron mobility. The thickness of the AlN insertion layer 600 is 0.5 nm to 2 nm.

[0046] Furthermore, an AlGaN barrier layer 700 is stacked on the AlN insertion layer 600 to form a polarization effect with the GaN channel layer 500 to generate a two-dimensional electron gas. The thickness of the AlGaN barrier layer 700 is 20nm-25nm.

[0047] Furthermore, a GaN capping layer 800 is stacked on the AlGaN barrier layer 700 to cover the AlGaN barrier layer 700 and prevent the AlGaN barrier layer 700 from being oxidized. The thickness of the GaN capping layer 800 is 3nm-5nm.

[0048] Additionally, please see Figure 2 The figure shows a method for fabricating a high electron mobility transistor provided by the present invention, the method comprising steps S10-S12:

[0049] Step S10: Provide a silicon substrate;

[0050] Before the epitaxial layer grows, the silicon substrate needs to be pretreated to remove impurities adsorbed on the surface of the silicon substrate.

[0051] Specifically, the silicon substrate is placed in the reaction chamber, the temperature is heated to 1000℃-1200℃, the pressure is set to 50mbar-100mbar, and H2 is introduced for pretreatment for 5min-10min.

[0052] Step S11: A composite buffer layer is grown on the silicon substrate. The composite buffer layer includes an AlScN layer grown on the silicon substrate and an AlSiN layer grown on the AlScN layer. The doping concentration of Si in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer.

[0053] Specifically, the temperature is adjusted to 1000℃-1200℃, the pressure is set to 30mbar-70mbar, and TMAl, Cp3Sc and NH3 and H2 are introduced at the same time as carrier gas to grow an AlScN layer with a thickness of 20nm-100nm on a silicon substrate.

[0054] The temperature is adjusted to 1000℃-1200℃, the pressure is set to 30mbar-70mbar, and TMAl, SiH4 and NH3 are introduced simultaneously. H2 is used as the carrier gas to grow an AlSiN layer with a thickness of 50nm-150nm on the AlScN layer.

[0055] Step S12: An AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the composite buffer layer.

[0056] Among them, an AlGaN buffer layer is grown on the composite buffer layer to alleviate lattice mismatch.

[0057] Specifically, the temperature is adjusted to 1000℃-1200℃ and the pressure is set to 30mbar-100mbar to epitaxially grow an AlGaN buffer layer with a thickness of 1μm-3μm on the composite buffer layer, wherein the Al composition of the AlGaN buffer layer accounts for 0.1-0.8%.

[0058] Furthermore, a GaN high-resistivity buffer layer is epitaxially grown on the AlGaN buffer layer to block the diffusion of two-dimensional electron gas toward the substrate.

[0059] Specifically, the temperature is adjusted to 950℃-1050℃, and the pressure is set to 50mbar-100mbar to epitaxially grow a GaN high-resistivity buffer layer with a thickness of 1μm-2μm on the AlGaN buffer layer. The GaN high-resistivity buffer layer is doped with carbon at a concentration of 10⁻⁶. 19 cm -3 -10 20 cm -3 .

[0060] Furthermore, a GaN channel layer is epitaxially grown on the GaN high-resistivity buffer layer to form a polarization effect with the AlGaN barrier layer to generate a two-dimensional electron gas.

[0061] Specifically, the temperature is set to 1050℃-1150℃ and the pressure is adjusted to 100mbar-300mbar to grow a GaN channel layer with a thickness of 300nm-600nm on the GaN high-resistivity buffer layer.

[0062] Furthermore, an AlN insertion layer is epitaxially grown on the GaN channel layer to reduce interface scattering between the GaN channel layer and the AlGaN barrier layer, thereby improving electron mobility.

[0063] Specifically, the temperature is adjusted to 1050℃-1150℃ and the pressure is set to 30mbar-100mbar to grow an AlN insertion layer with a thickness of 0.5nm-2nm on the GaN channel layer.

[0064] Furthermore, an AlGaN barrier layer is grown on the AlN insertion layer to form a polarization effect with the channel layer to generate a two-dimensional electron gas.

[0065] Specifically, the temperature is adjusted to 1050℃-1150℃ and the pressure is set to 30mbar-100mbar to epitaxially grow an AlGaN barrier layer with a thickness of 20nm-25nm on the AlN insertion layer, wherein the Al composition accounts for 0.2-0.25%.

[0066] In addition, a GaN capping layer is epitaxially grown on the AlGaN barrier layer to cover the AlGaN barrier layer and prevent the AlGaN barrier layer from being oxidized.

[0067] Specifically, the temperature is adjusted to 1050℃-1150℃ and the pressure is set to 30mbar-100mbar to epitaxially grow a GaN capping layer with a thickness of 3nm-5nm on the AlGaN barrier layer.

[0068] At this point, the epitaxial structure growth is complete, and the temperature of the reaction chamber is reduced to room temperature in a nitrogen atmosphere.

[0069] The present invention is further illustrated below with specific embodiments:

[0070] Example 1

[0071] Please see Figure 1 The image shows a high electron mobility transistor provided in the first embodiment of the present invention. The high electron mobility transistor includes a silicon substrate, wherein the silicon substrate is a (111) crystal orientation silicon substrate, and the doping element is boron (B) with a doping concentration of 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 .

[0072] Furthermore, the high electron mobility transistor also includes: a composite buffer layer, an AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer, which are sequentially stacked on a silicon substrate.

[0073] The composite buffer layer includes an AlScN layer stacked on a silicon substrate and an AlSiN layer stacked on top of the AlScN layer.

[0074] Preferably, the Sc component of the AlScN layer accounts for 0.3%, and the thickness of the AlScN layer is 40 nm.

[0075] In addition, an AlSiN layer is stacked on top of the AlScN layer, and the thickness of the AlSiN layer is 100 nm.

[0076] Furthermore, the Si doping concentration in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer, with the doping concentration starting from 1×10⁻⁶. 18 cm -3 Gradually decrease to 1×10 17 cm -3 That is, the initial doping concentration of Si in the AlSiN layer is 1×10⁻⁶. 18 cm -3 The termination doping concentration of Si in the AlSiN layer is 1×10⁻⁶. 17 cm -3 .

[0077] An AlGaN buffer layer is provided on the composite buffer layer. The thickness of the AlGaN buffer layer is 1μm-3μm, and the Al component accounts for 0.1-0.8%.

[0078] Furthermore, a GaN high-resistivity buffer layer is stacked on the AlGaN buffer layer. The doping element of the GaN high-resistivity buffer layer is carbon, and the carbon doping concentration is 1×10⁻⁶. 19 cm -3 -1×10 20 cm-3 The thickness of the GaN high-resistivity buffer layer is 1μm-2μm.

[0079] Furthermore, a GaN channel layer is stacked on the GaN high-resistivity buffer layer, and the thickness of the GaN channel layer is 300nm-600nm.

[0080] Furthermore, an AlN insertion layer is stacked on the GaN channel layer, with the thickness of the AlN insertion layer being 0.5nm-2nm.

[0081] Furthermore, an AlGaN barrier layer is stacked on the AlN insertion layer, and the thickness of the AlGaN barrier layer is 20nm-25nm.

[0082] Furthermore, a GaN capping layer is stacked on the AlGaN barrier layer, with a thickness of 3nm-5nm.

[0083] Accordingly, the fabrication method of the high electron mobility transistor in this embodiment includes steps S10-S12:

[0084] Step S10: Provide a silicon substrate;

[0085] Specifically, the silicon substrate is placed in the reaction chamber, the temperature is heated to 1000℃-1200℃, the pressure is set to 50mbar-100mbar, and H2 is introduced for pretreatment for 5min-10min.

[0086] Step S11: A composite buffer layer is grown on the silicon substrate. The composite buffer layer includes an AlScN layer grown on the silicon substrate and an AlSiN layer grown on the AlScN layer. The doping concentration of Si in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer.

[0087] Specifically, the temperature is adjusted to 1100℃, the pressure is set to 30mbar, and TMAl, Cp3Sc and NH3 and H2 are introduced at the same time as carrier gas to grow an AlScN layer with a thickness of 20nm-100nm on a silicon substrate.

[0088] The temperature was adjusted to 1100℃, the pressure was set to 30mbar-70mbar, and TMAl, SiH4 and NH3 were introduced simultaneously. H2 was used as the carrier gas to grow an AlSiN layer with a thickness of 50nm-150nm on the AlScN layer.

[0089] Step S12: An AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the composite buffer layer.

[0090] Specifically, the temperature is adjusted to 1000℃-1200℃ and the pressure is set to 30mbar-100mbar to epitaxially grow an AlGaN buffer layer with a thickness of 1μm-3μm on the composite buffer layer, wherein the Al composition of the AlGaN buffer layer accounts for 0.1-0.8%.

[0091] Furthermore, the temperature is adjusted to 950℃-1050℃ and the pressure is set to 50mbar-100mbar to epitaxially grow a GaN high-resistivity buffer layer with a thickness of 1μm-2μm on the AlGaN buffer layer. The GaN high-resistivity buffer layer is doped with carbon at a concentration of 10%. 19 cm -3 -10 20 cm -3 .

[0092] Furthermore, the temperature was set to 1050℃-1150℃ and the pressure was adjusted to 100mbar-300mbar to grow a GaN channel layer with a thickness of 300nm-600nm on the GaN high-resistivity buffer layer.

[0093] Furthermore, the temperature was adjusted to 1050℃-1150℃ and the pressure was set to 30mbar-100mbar to grow an AlN insertion layer with a thickness of 0.5nm-2nm on the GaN channel layer.

[0094] Furthermore, the temperature was adjusted to 1050℃-1150℃ and the pressure was set to 30mbar-100mbar to epitaxially grow an AlGaN barrier layer with a thickness of 20nm-25nm on the AlN insertion layer, wherein the Al composition accounted for 0.2-0.25%.

[0095] Furthermore, the temperature was adjusted to 1050℃-1150℃ and the pressure was set to 30mbar-100mbar to epitaxially grow a GaN capping layer with a thickness of 3nm-5nm on the AlGaN barrier layer.

[0096] At this point, the epitaxial structure growth is complete, and the temperature of the reaction chamber is reduced to room temperature in a nitrogen atmosphere.

[0097] Example 2

[0098] The second embodiment of the present invention provides a high electron mobility transistor, which differs from the high electron mobility transistor in the first embodiment in that:

[0099] The Sc component in the AlScN layer accounts for 0.1%.

[0100] Example 3

[0101] The third embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0102] The Sc component in the AlScN layer accounts for 0.2%.

[0103] Example 4

[0104] The fourth embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0105] The Sc component in the AlScN layer accounts for 0.4%.

[0106] Example 5

[0107] The fifth embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0108] The AlScN layer is 30 nm thick.

[0109] Example 6

[0110] The sixth embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0111] The AlScN layer has a thickness of 50 nm.

[0112] Example 7

[0113] The seventh embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0114] The initial Si doping concentration in the AlSiN layer is 2 × 10⁻⁶. 17 cm -3 .

[0115] Example 8

[0116] The eighth embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0117] The initial Si doping concentration in the AlSiN layer is 5 × 10⁻⁶. 17 cm -3 .

[0118] Example 9

[0119] The ninth embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0120] The initial Si doping concentration in the AlSiN layer is 1.5 × 10⁻⁶. 18 cm -3 .

[0121] Example 10

[0122] The tenth embodiment of the present invention provides a high electron mobility transistor. The high electron mobility transistor in this embodiment differs from the high electron mobility transistor in the first embodiment in that:

[0123] The initial Si doping concentration in the AlSiN layer is 2 × 10⁻⁶. 18 cm -3 .

[0124] Comparative Example 1

[0125] The first comparative example of this invention provides a high electron mobility transistor. The high electron mobility transistor in this comparative example differs from the high electron mobility transistor in the first embodiment in that:

[0126] There is no composite buffer layer.

[0127] Please refer to Table 1 below, which shows the parameters corresponding to Embodiments 1 to 10 and Comparative Example 1 of the present invention.

[0128] Table 1

[0129]

[0130]

[0131] It should be noted that the high electron mobility transistors of Examples 1 to 10 and Comparative Example 1 were fabricated using the same process conditions.

[0132] Based on the data from Examples 1 to 10 and Comparative Example 1, it can be seen that by stacking a composite buffer layer on a silicon substrate, the lattice mismatch between the silicon substrate and the subsequently grown epitaxial layer is reduced, the crystal quality of the subsequently grown epitaxial layer is improved, the defect density is reduced, and the warpage can be adjusted, which is beneficial to improving the electrical performance of the device.

[0133] Based on the data from Examples 1 to 4, it can be seen that when the proportion of Sc in the AlScN layer is less than that in Example 1, the crystal quality is relatively worse, the dislocation density is relatively increased, the tensile stress is increased, the warping is increased, and the breakdown voltage is relatively worse. Conversely, when the proportion of Sc in the AlScN layer is more than that in Example 1, the crystal quality is relatively worse, the dislocation density is relatively increased, the compressive stress is increased, and the breakdown voltage is relatively worse.

[0134] Based on the data from Examples 1, 5, and 6, it can be seen that when the thickness of the AlScN layer is thinner than that of the AlScN layer in Example 1, the crystal quality is relatively worse, the dislocation density is relatively increased, the tensile stress is slightly increased, the warping is increased, and the breakdown voltage is relatively worse; conversely, when the thickness of the AlScN layer is thicker than that of the AlScN layer in Example 1, the crystal quality is relatively worse, the dislocation density is relatively increased, the compressive stress is relatively increased, and the breakdown voltage is relatively worse.

[0135] Based on the data from Examples 1, 7 to 10, it can be seen that when the initial doping concentration of Si in the AlSiN layer is less than that in the AlSiN layer of Example 1, the crystal quality is relatively worse, the dislocation density is relatively higher, the compressive stress is relatively higher, and the breakdown voltage is relatively worse. Conversely, when the initial doping concentration of Si in the AlSiN layer is more than that in the AlSiN layer of Example 1, the crystal quality is relatively worse, the dislocation density is relatively higher, the tensile stress is relatively higher, and the breakdown voltage is relatively worse.

[0136] In summary, by stacking a composite buffer layer on a silicon substrate, the lattice mismatch between the silicon substrate and the subsequently grown epitaxial layer can be reduced, thereby improving the crystal quality of the subsequently grown epitaxial layer, reducing the defect density, and adjusting the warpage, which is beneficial to improving the electrical performance of the device.

[0137] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0138] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A high electron mobility transistor, comprising a silicon substrate, characterized in that, The high electron mobility transistor also includes: A composite buffer layer, an AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially stacked on the silicon substrate. The composite buffer layer includes an AlScN layer stacked on the silicon substrate and an AlSiN layer stacked on the AlScN layer. The Si doping concentration in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer, and the Si doping concentration in the AlSiN layer is 1×10⁻⁶. 17 cm -3 -2×10 18 cm -3 The Sc component of the AlScN layer has a composition ratio of 0.1-0.4%.

2. The high electron mobility transistor according to claim 1, characterized in that, The thickness of the AlScN layer is 20nm-100nm.

3. The high electron mobility transistor according to claim 1, characterized in that, The thickness of the AlSiN layer is 50nm-150nm.

4. The high electron mobility transistor according to claim 1, characterized in that, The Si doping concentration in the AlSiN layer ranges from 1×10⁻⁶. 18 cm -3 Gradually decrease to 1×10 17 cm -3 .

5. The high electron mobility transistor according to claim 1, characterized in that, The thickness of the AlGaN buffer layer is 1μm-3μm.

6. The high electron mobility transistor according to claim 1, characterized in that, The GaN high-resistivity buffer layer is doped with carbon, and the carbon doping concentration is 1×10⁻⁶. 19 cm -3 -1×10 20 cm -3 .

7. A method for fabricating a high electron mobility transistor, characterized in that, The preparation method includes: Provide a silicon substrate; A composite buffer layer is grown on the silicon substrate. The composite buffer layer includes an AlScN layer grown on the silicon substrate and an AlSiN layer grown on the AlScN layer. The Si doping concentration in the AlSiN layer gradually decreases from the side closer to the AlScN layer to the side farther away from the AlScN layer. The Si doping concentration in the AlSiN layer is 1×10⁻⁶. 17 cm -3 -2×10 18 cm -3 The Sc component of the AlScN layer has a composition ratio of 0.1-0.

4. An AlGaN buffer layer, a GaN high-resistivity buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the composite buffer layer.

8. The method for fabricating a high electron mobility transistor according to claim 7, characterized in that, The growth steps of the composite buffer layer include: The temperature was adjusted to 1000℃-1200℃, the pressure was set to 30mbar-70mbar, and TMAl, Cp3Sc and NH3 and H2 were introduced at the same time as carrier gas to grow an AlScN layer with a thickness of 20nm-100nm on a silicon substrate. The temperature is adjusted to 1000℃-1200℃, the pressure is set to 30mbar-70mbar, and TMAl, SiH4 and NH3 are introduced simultaneously. H2 is used as the carrier gas to grow an AlSiN layer with a thickness of 50nm-150nm on the AlScN layer.

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