A composite RC-LIGBT device with a triple gate structure

Abstract

The application relates to a composite RC-LIGBT device with a three-gate structure, and belongs to the field of semiconductor power devices. The device comprises an LDMOS region and LIGBT regions located on both sides of the LDMOS region, and the two are isolated by SiO2. When the device is forward conducted, the sidewall of the LDMOS is inducted by the body-in-slot gate of the LIGBT to form a sidewall channel conduction, and meanwhile, the body-in-slot gate forms a slot-gate channel conduction, so that the LIGBT and the LDMOS are simultaneously forward conducted; during the transition process of the three modes when the device is forward conducted, the device is in a stable transition state without current mutation; when the device is reversely conducted, the parasitic PIN diode of the LDMOS region of the device realizes the reverse conduction capacity, and the planar channel gate injects electrons into the carrier distribution of the drift region. The application completely eliminates the snapback phenomenon, has the reverse conduction capacity, and improves the compromise relationship between the turn-off loss and the conduction voltage of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices and relates to a composite RC-LIGBT device with a three-gate structure. Background Technology

[0002] As a crucial component of power electronics technology, IGBTs (Inductively Coupled Transistors) have become a major development direction in power semiconductors due to their advantages of low driving power, fast switching speed, and strong conductivity, and their development is continuously driving the advancement of power electronics technology. SOI-based LIGBTs (Lateral Insulated Gate Bipolar Transistors) possess advantages such as good insulation performance, low parasitic capacitance, low leakage current, and high integration density, and are widely used in new energy vehicles, electric locomotives, home appliances, motor control, and smart grids, making them highly promising semiconductor power devices for the future market. However, due to its internal structural characteristics, a LIGBT is equivalent to a PNP transistor during reverse conduction. When the cathode is connected to a high potential, the gate to zero potential, and the anode to a low potential, the PN junction formed by the P-Collector and N-buffer at the collector is always in a reverse bias state, therefore, the LIGBT does not possess reverse conductivity. To enable reverse conduction in a LIGBT, an external freewheeling diode (FWD) is typically required. With technological advancements, researchers have proposed replacing a portion of the P-Collector of the collector with an N-Collector, enabling the integration of the freewheeling diode and LIGBT on a single silicon chip. This type of LIGBT is named RC-LIGBT. While RC-LIGBTs possess reverse conduction capability and achieve integration of the LIGBT and freewheeling diode, they also introduce new problems. During forward conduction, the gate voltage of the RC-LIGBT is gradually increased to channel inversion, with the anode connected to a high potential and the cathode to a low potential. At this time, electrons flow from the N-collector to the LIGBT. + The source region flows through the channel, through the drift region, and finally into the N-Collector, generating a potential difference V across the PN junction formed by the P-Collector / N-buffer. PN When the potential difference V PN When the voltage is less than 0.7V, only the voltage from N is present. + The injected electrons participate in conduction, and the RC-LIGBT operates in a unipolar conduction mode. As the anode voltage gradually increases, when V... PNAt voltages above 0.7V, the PN junction formed by the P-Collector / N-buffer begins to conduct. The P-Collector injects holes into the drift region and begins to modulate the conductivity with electrons, forming a bipolar conduction mode where holes and electrons conduct electricity together. Since the unipolar conduction mode involves high voltage and low current, while the bipolar conduction mode involves high current and low voltage, the transition from unipolar to bipolar mode causes a sudden change in current and voltage, resulting in a negative resistance phenomenon, also known as the snapback effect. This negative resistance effect significantly impacts the dynamic characteristics of the device, and it can also hinder the full turn-on of other devices in the circuit system when RC-LIGBTs are used in parallel at low temperatures. Therefore, eliminating the negative resistance effect has become an important research direction for RC-LIGBTs. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a composite RC-LIGBT device with a three-gate structure, which enables the RC-LIGBT device to have reverse conduction capability while eliminating the snapback phenomenon.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A composite RC-LIGBT device with a three-gate structure includes an LDMOS region and LIGBT regions located on both sides of the LDMOS region, separated by a SiO2 isolation layer 12. Both the LDMOS region and the LIGBT regions are located above the dielectric isolation layer, which is located above the substrate. The thickness of the SiO2 isolation layer can be varied as needed.

[0006] The LIGBT region comprises, in sequence, an emitter P+ region 1, an emitter N+ region 2, a body trench gate 3, an N-drift region 4, an N-buffer region 5, and a P-collector region 6, as well as a P-well region 7. The P-well region 7 is adjacent to the emitter P+ region 1 and the emitter N+ region 2 on its upper side, to the body trench gate 3 on its right side, and to the N-drift region 4 on its lower side. The collector of the LIGBT region is the P-collector region 6.

[0007] The LDMOS region includes, in sequence, an emitter P+ region 1, an emitter N+ region 2, a P-well region 7, an N-drift region 4, an N-buffer region 5, and an N-collector 11, and also includes a planar MOS channel gate 10. The lower side of the planar MOS channel gate 10 is adjacent to the emitter N+ region 2, the P-well region 7, and the N-drift region 4, respectively. The collector of the LDMOS region is the N-collector region 11.

[0008] Furthermore, the thickness of the planar MOS channel gate 10 can be changed as needed.

[0009] Furthermore, the in-body trench gate 3 includes a polysilicon gate 13 and a gate oxide layer 14, wherein the gate oxide layer 14 completely encapsulates the polysilicon gate 13. The thickness of the gate oxide layer 14 can be varied as needed.

[0010] Furthermore, the P-collector region 6 and the N-collector region 11 constitute the collector of the device. The planar MOS channel gate 10 of the LDMOS region and the body trench gate 3 of the LIGBT regions on both sides of the LDMOS region constitute the three-gate structure of the device.

[0011] Furthermore, the substrate 9 may be made of silicon, silicon carbide or gallium arsenide.

[0012] Furthermore, the present invention can conduct in both forward and reverse directions, and its conduction principles are as follows:

[0013] (1) During forward conduction, the conduction process of this invention consists of three steps:

[0014] Step 1: When the potential difference V between the PN junctions PN When the voltage is <0.7V, the sidewall gate formed by the body trench gate of the LIGBT region and the SiO2 isolation layer creates a sidewall channel in the LDMOS region. Electrons are injected from the N+ emitter of the LDMOS region, flow through the drift region of the LDMOS region, pass through the N-buffer region, and flow out through the N-collector region. At this time, the PN junction (P-collector / N-buffer) in the LIGBT region is not turned on, the LIGBT is in the cut-off state, there is no current, and the LDMOS is turned on.

[0015] The second step is that as the collector voltage of the LDMOS region and LIGBT region increases, the P-collector / N-buffer of the LIGBT region turns on, and the P-collector region begins to inject holes into the drift region of the LIGBT region, and the LIGBT turns on, forming a mixed conduction mode of the LIGBT region and the LDMOS region.

[0016] Third, the LIGBT region is in a bipolar conduction mode, and the current increases exponentially with the voltage. As the collector voltage continues to increase, the conduction of the composite RC-LIGBT device is mainly in the bipolar conduction mode of the LIGBT region.

[0017] (2) When reverse conduction occurs, the conduction of the LDMOS region can be divided into two parts of conduction current. Under the action of the planar MOS channel gate, a reverse channel current will be formed. In addition, the P-well region and N-drift region in the LDMOS region can be equivalent to a PN junction. At this time, the emitter is at a high potential, the PN junction is forward biased, and the N-collector region is a low barrier relative to electrons, allowing electron current to flow. In contrast, the P-well region, N-drift region, N-buffer and P-collector in the LIGBT region are equivalent to a PNP transistor structure. The PN junction formed by the P-well region and N-drift region is forward biased, while the PN junction formed by the N-buffer and P-collector is reverse biased, and electron current is not allowed to flow.

[0018] The beneficial effects of this invention are as follows: This invention uses a SiO2 isolation layer to completely isolate the N-collector and P-collector in the LDMOS region and the LIGBT region. During forward conduction, there is no conversion process from unipolar conduction to bipolar conduction, which can eliminate the snapback phenomenon. During reverse conduction, it has good independence. At the same time, by enabling the LIGBT and LDMOS to conduct together, this invention reduces the overall hole carrier concentration in the N-type drift region of the device. Therefore, the number of carriers that need to be extracted in the N-type drift region during turn-off is also reduced, thus reducing turn-off loss.

[0019] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0021] Figure 1 This is a schematic diagram of the composite RC-LIGBT device with a three-gate structure according to the present invention;

[0022] Figure 2 for Figure 1 Plan view of each section, Figure 2 (a) is Figure 1 A schematic diagram along section a. Figure 2 (b) is Figure 1 A schematic diagram along section b. Figure 2 (c) is Figure 1 A schematic diagram along section c. Figure 2 (d) is Figure 1 A schematic diagram along section d;

[0023] Figure 3 This diagram illustrates the circuit principle and current flow direction of the RC-LIGBT device of the present invention. Figure 3 (a) is the circuit schematic of the RC-LIGBT device. Figure 3 (b) is a schematic diagram of the current flow when the device is reverse-biased;

[0024] Figure 4 This is a schematic diagram showing the current flow direction of the device during forward conduction. Figure 4 (a) is a diagram showing the current flow direction in the LIGBT region during forward conduction. Figure 4 (b) is a diagram showing the current flow direction in the LDMOS region during forward conduction;

[0025] Figure 5 This is a schematic diagram showing the current flow direction of the device when it is in reverse conduction. Figure 5 (a) is a diagram showing the current flow direction in the LDMOS region during reverse conduction. Figure 5 (b) When reverse conduction occurs, a channel inversion layer is formed in the P-well region of the planar MOS channel gate in the LDMOS region;

[0026] Figure 6 The concentration N in the drift region d =2.8×10 15 A comparison chart of breakdown voltages for traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs, and novel RC-LIGBTs;

[0027] Figure 7 A comparison of the breakdown voltages of traditional LIGBT, SSA-LIGBT, TBSA-LIGBT, and novel RC-LIGBT at different drift region doping concentrations;

[0028] Figure 8 Forward conduction curves for traditional LIGBT, SSA-LIGBT, TBSA-LIGBT, and novel RC-LIGBT;

[0029] Figure 9 This is a graph showing the relationship between the trench gate depth in the LIGBT region and the overall on-state voltage of the device when the novel RC-LIGBT is forward-biased.

[0030] Figure 10 Reverse conduction curves for traditional LIGBT, SSA-LIGBT, TBSA-LIGBT, and novel RC-LIGBT;

[0031] Figure 11A comparison chart of turn-off losses for traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs, and novel RC-LIGBTs under the same on-voltage condition;

[0032] Figure 12 A comparison chart showing the trade-off relationship between turn-off loss and turn-on voltage for traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs, and novel RC-LIGBTs;

[0033] Figure 13 This is a schematic diagram of the main process flow of the new RC-LIGBT.

[0034] Figure reference numerals: 1-Emitter P+ region; 2-Emitter N+ region; 3-Bulk trench gate; 4-N-Drift region; 5-N-Buffer region; 6-P-Collector region; 7-P-Well region; 8-Dielectric isolation layer; 9-Substrate; 10-Planar MOS channel gate; 11-N-Collector region; 12-SiO2 isolation layer; 13-Polysilicon gate; 14-Gate oxide layer. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0037] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0038] like Figure 1 and Figure 2 As shown, a composite RC-LIGBT device with a three-gate structure is shown. The device includes an emitter P+ region 1, an emitter N+ region 2, a body trench gate 3, an N-drift region 4, an N-buffer region 5, a P-collector region 6, a P-well region 7, a dielectric isolation layer 8, a substrate 9, a planar MOS channel gate 10, an N-collector region 11, a SiO2 isolation layer 12, a polysilicon gate 13, and a gate oxide layer 14.

[0039] In this device, the device is divided into an LDMOS region (S2) in the middle and LIGBT regions (S1) on both sides of the isolation layer by a SiO2 isolation layer 12. The LDMOS region and the LIGBT region share the emitter P+ region 1, emitter N+ region 2 and P-well region 7 as emitters.

[0040] From left to right, the LIGBT horizontally comprises an emitter P+ region 1, an emitter N+ region 2, a body slot gate 3, an N-drift region 4, an N-buffer region 5, and a P-collector region 6, wherein emitter P+ region 1 and emitter N+ region 2 are connected to the emitter. The LIGBT region also includes a P-well region 7, which has emitter P+ region 1 and emitter N+ region 2 above it, body slot gate 3 on its right side, and N-drift region 4 below it.

[0041] The LDMOS, arranged horizontally from left to right, includes an emitter P+ region 1, an emitter N+ region 2, a P-well region 7, an N-drift region 4, an N-buffer region 5, and an N-collector region 11. The LDMOS also includes a planar MOS channel gate 10, which is connected to the emitter. The lower contacts, from left to right, are the emitter N+ region 2, the P-well region 7, and the N-drift region 4. The LDMOS is surrounded by a SiO2 isolation layer 12. During forward conduction, applying voltage to the body trench gate 3 in the LIGBT causes a sidewall channel current to conduct in the P-well region 7 of the LDMOS region. During reverse conduction, the emitter is connected to a high potential and the collector to a low potential. Reverse current conduction is generated through the planar MOS channel gate 10 forming a reverse channel current in the P-well region 7 and the PN junction formed by the P-well region 7 and the N-drift region 4.

[0042] The collector in the composite RC-LIGBT device, from left to right, includes a P-collector region 6, a SiO2 isolation layer 12, an N-collector region 11, a SiO2 isolation layer 12, and a P-collector region 6.

[0043] The drift region is formed by epitaxial growth and together with the substrate and dielectric isolation layer, it forms the SOI structure, namely silicon on insulator.

[0044] The mechanism of the composite RC-LIGBT proposed in this invention is as follows:

[0045] (1) By using a thin double SiO2 isolation layer as the gate oxide layer of the LDMOS region, when the LIGBT is forward-biased, the SiO2 isolation layer gains voltage while the bulk trench gate is pressurized. Induction charges are generated on both sides of the P-well region of the LDMOS region near the SiO2 isolation layer, forming a sidewall channel for conduction.

[0046] (2) The planar MOS channel gate in the LDMOS region is connected to the common emitter. During reverse conduction, the emitter is at a high potential. Induced charges are generated in the P-well region below the thin gate oxide layer of the planar MOS channel gate, forming channel conductivity. The PN junction formed by the P-well region and the drift region also conducts electricity. Figure 3 As shown in (b), the device utilizes LDMOS for reverse conduction.

[0047] (3) During forward conduction, the conduction process of the composite RC-LIGBT device consists of three steps:

[0048] Step 1: When the potential difference V between the PN junctions PNWhen the voltage is <0.7V, electrons are injected from the N+ emitter of the LDMOS region, flow through the drift region of the LDMOS, pass through the N-buffer region, and then flow out through the N-collector region. At this time, the PN junction (P-collector / N-buffer) in the LIGBT region is not turned on, and the device is in the LDMOS on-mode.

[0049] Step 2: As the collector voltage of the LDMOS region and LIGBT region increases, the P-collector / N-buffer of the LIGBT region turns on, and the P-collector region begins to inject holes into the drift region of the LIGBT region, and the LIGBT turns on, forming a mixed conduction mode of the LIGBT region and the LDMOS region.

[0050] Step 3: The LIGBT region is in a bipolar conduction mode, and the current increases exponentially with the voltage. As the collector voltage continues to increase, the conduction of the composite RC-LIGBT device is mainly in the bipolar conduction mode of the LIGBT region.

[0051] Therefore, the entire forward conduction process forms a conduction mode in which the LDMOS region is the main conductor in the first stage, the LIGBT region and the LDMOS region are mixed conduction modes in the second stage, and the LIGBT region is the main bipolar conduction mode in the third stage. Since the N-collector and P-collector in the collector of the LDMOS region and the LIGBT region are completely isolated, there is no conversion process from unipolar conduction to bipolar conduction in conventional RC-LIGBT devices. Therefore, there is no snapback phenomenon in conventional RC-LIGBT devices during the entire conduction process.

[0052] (4) During reverse conduction, the conduction of the LDMOS region can be divided into two conduction currents. Under the action of the planar MOS channel gate, a reverse channel current will be formed. In addition, the P-well region and drift region in the LDMOS region can be equivalent to a PN junction. At this time, the emitter is at a high potential, the PN junction is forward biased, and the N-collector region is a low potential barrier relative to electrons, allowing electron current to flow. In contrast, the P-well region, N-drift region, N-buffer, and P-collector in the LIGBT region are equivalent to a PNP transistor structure. The PN junction formed by the P-well region and N-drift region is forward biased, while the PN junction formed by the N-buffer and P-collector is reverse biased, and electron current is not allowed to flow. It can be seen that the composite RC-LIGBT device of the present invention has good independence in its reverse operation.

[0053] Using SENTAURUS simulation software, simulations of traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs, and the novel RC-LIGBT proposed in this invention were compared. The simulation parameters for the four structures were consistent, with the following parameters: total N-drift region thickness of 4 μm, carrier lifetime of 10 μs, ambient temperature of 300 K, length of 22 μm, and doping concentration of N... d The concentration of the N-buffer layer is adjustable.

[0054] Figure 4 The image shown is a simulation diagram of the forward conduction of the novel RC-LIGBT device. Figure 4 (a) shows the current flow curve in the LIGBT region when the device is forward-biased. When the device is forward-biased, the LIGBT region exhibits a bipolar conduction mode, with both electron and hole currents conducting. Figure 4 (b) is the current flow curve of the LDMOS region when the device is forward-biased. The LDMOS relies on the double SiO2 isolation layer that is close to the LIGBT trench gate to generate channel conduction. In the LDMOS, it is a unipolar conduction mode of electronic current conduction.

[0055] Figure 5 The diagram shown is a simulation of the reverse conduction of a novel RC-LIGBT device. During reverse conduction, the LIGBT region cannot conduct, and no current flows; only the LDMOS region undergoes reverse conduction. Figure 5 (a) shows the current flow curve when the device is reverse-biased, and the reverse-biased current flow curve exhibits the following characteristics: Figure 3 (b) shows the current flowing through the PN junction and the MOS current during reverse conduction, which increases the on-current density of the LDMOS during reverse conduction. Figure 5 (b) shows a distinct channel inversion layer that appears beneath the planar MOS channel gate when the device is reverse-biased.

[0056] Figure 6 The figure shows a concentration of 2.8 × 10⁻⁶ at room temperature (T = 300 K) in the drift region. 15 The breakdown voltage of traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs and the novel RC-LIGBT proposed in this invention were compared. Under the same structural parameters, the breakdown voltage of the novel RC-LIGBT is 264V, which is lower than that of other devices. The main reason is that the thin double SiO2 isolation layer is prone to breakdown when the device withstands voltage. Therefore, the breakdown voltage of this novel RC-LIGBT is lower.

[0057] Figure 7The figure shows a comparison of the breakdown voltages of traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs, and the novel RC-LIGBT at different drift region concentrations at room temperature (T = 300 K). The breakdown voltages of all devices initially rise to a maximum and then decrease as the drift region concentration changes. The novel RC-LIGBT shows the highest breakdown voltage at a concentration of 2.8 × 10⁻⁶ K. 15 The breakdown voltage reaches its maximum at a concentration of 2.9 × 10⁻⁶. 15 The breakdown voltage reaches its maximum at a concentration of 2.9 × 10⁻⁶. 15 The breakdown voltage reaches its maximum at a concentration of 3.0 × 10⁻⁶. 15 The breakdown voltage reaches its highest point at this time.

[0058] Figure 8 Simulations were performed on the concentration N in the drift region of traditional LIGBT, SSA-LIGBT, TBSA-LIGBT, and the novel RC-LIGBT. d 2.8×10 15 The figure shows the forward conduction voltage of traditional LIGBTs and the new RC-LIGBTs. As can be seen from the figure, the forward conduction voltage of traditional LIGBTs and the new RC-LIGBTs is lower than that of SSA-LIGBTs and TBSA-LIGBTs. SSA-LIGBTs clearly exhibit a significant snapback effect during forward conduction, showing a sudden change in current and voltage as they transition from unipolar to bipolar conduction (small current, large voltage) to large current, small voltage. The greater the distance between the anode P-collector and the anode N+, the smaller the snapback effect, but this results in wasted chip area. TBSA-LIGBTs, by increasing the resistance between the anode P-collector and the anode N+, almost completely shield the snapback effect. The new RC-LIGBTs do not have a transition from unipolar to bipolar conduction mode, achieving snapback-free operation.

[0059] Figure 9 Simulations were performed on the novel RC-LIGBT at a concentration N in the drift region. d 2.8×10 15 The effect of trench gate depth on the forward conduction of the device is as follows: when the trench gate depth Tg is less than 2.1 μm, the conduction voltage Von gradually decreases as the trench gate depth increases. When the trench gate depth Tg is greater than 2.1 μm, the minimum point of the decrease in conduction voltage Von tends to be flat.

[0060] Figure 10 Simulations were performed on traditional LIGBT, SSA-LIGBT, TBSA-LIGBT, and the novel RC-LIGBT at the drift region concentration N.d 2.8×10 15 The reverse conduction voltage was measured. The new RC-LIGBT had the lowest reverse conduction voltage at 0.94V. Because the SSA-LIGBT extends the length of its anode region, its reverse conduction voltage is higher; the longer the anode region of the SSA-LIGBT, the higher its reverse conduction voltage. The TBSA-LIGBT added two SiO2 trenches to the anode region to increase the on-resistance and shield the snapback effect, but this significantly increased the reverse conduction voltage to 3.46V.

[0061] Figure 11 The turn-off losses of traditional LIGBTs, SSA-LIGBTs, TBSA-LIGBTs, and a novel RC-LIGBT were simulated at a forward conduction voltage of 1.24V. Figure 11 It can be seen that when the forward conduction voltages of the four devices are the same, the new RC-LIGBT has the lowest turn-off loss, followed by the TBSA-LIGBT, the SSA-LIGBT has a higher turn-off loss than the TBSA-LIGBT, and the traditional LIGBT has the highest turn-off loss.

[0062] Figure 12 The forward conduction voltage V of traditional LIGBT, SSA-LIGBT, TBSA-LIGBT and novel RC-LIGBT were simulated. on With turn-off loss E off A compromise. All LIGBT devices at the forward conduction voltage V on When increased, the turn-off loss E off All will decrease. When all four devices are at the same on-state voltage V on At 1.24V, the turn-off loss E of the new RC-LIGBT off It reduces costs by 27% compared to traditional LIGBTs, 21% compared to SSA-LIGBTs, and 8% compared to TBSA-LIGBTs.

[0063] Figure 13The diagram shows the main fabrication process flow for the new RC-LIGBT device. The fabrication process is as follows: P-type... <100> A single-crystal substrate is oriented for zone melting to grow a SiO2 dielectric isolation layer, followed by epitaxial growth of the N-drift region of an RC-LIGBT to form an SOI structure. Based on the SOI structure, a trench region is etched in the N-drift region to grow the SiO2 isolation layer and the N-drift region of the LDMOS region. High-concentration ion implantation is performed, and the P-well, N+, and P+ regions on the left side are pushed together at high temperature. A trench gate is etched in the N-drift region to grow the bulk trench gate of the LIBGT region and the planar MOS channel gate of the LDMOS region. Next, ion implantation is performed on the surface to form the N-Collector and P-Collector of the LDMOS and LIBGT, respectively. Holes are drilled and emitter-collector metals are deposited. Finally, passivation and encapsulation are performed.

[0064] In the implementation process, according to the design requirements of specific devices, the present invention proposes a novel RC-LIGBT with a three-gate structure. In the specific fabrication, in addition to silicon (Si), the substrate material can also be replaced by semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A composite RC-LIGBT device with a three-gate structure, comprising a substrate (9) and a dielectric isolation layer (8), characterized in that: The device also includes an LDMOS region and LIGBT regions located on both sides of the LDMOS region. The LDMOS region and the LIGBT regions on both sides are separated by a SiO2 isolation layer (12). The LDMOS region and the LIGBT region are both located above the dielectric isolation layer (8), which is located above the substrate (9). The LIGBT region includes an emitter P+ region (1), an emitter N+ region (2), a body trench gate (3), an N-drift region (4), an N-buffer region (5), and a P-collector region (6) connected in sequence; the LIGBT region also includes a P-well region (7), which is adjacent to the emitter P+ region (1) and the emitter N+ region (2) on the upper side, adjacent to the body trench gate (3) on the right side, and adjacent to the N-drift region (4) on the lower side; The LDMOS region includes an emitter P+ region (1), an emitter N+ region (2), a P-well region (7), an N-drift region (4), an N-buffer region (5), and an N-collector (11) connected in sequence; the LDMOS region also includes a planar MOS channel gate (10), the lower side of which is adjacent to the emitter N+ region (2), the P-well region (7), and the N-drift region (4), respectively.

2. The composite RC-LIGBT device according to claim 1, characterized in that: The in-body trench gate (3) includes a polysilicon gate (13) and a gate oxide layer (14), wherein the gate oxide layer (14) completely encapsulates the polysilicon gate (13).

3. The composite RC-LIGBT device according to claim 1, characterized in that: The P-collector region (6) and the N-collector region (11) constitute the collector of the device.

4. The composite RC-LIGBT device according to claim 1, characterized in that: The planar MOS channel gate (10) of the LDMOS region and the body trench gate (3) of the LIGBT region on both sides of the LDMOS region constitute the three-gate structure of the device.

5. The composite RC-LIGBT device according to claim 1, characterized in that: The substrate (9) is made of silicon, silicon carbide or gallium arsenide.

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