Light emitting diode epitaxial wafer and preparation method thereof, LED

Abstract

The application discloses a light emitting diode epitaxial wafer and a preparation method and LED thereof, and relates to the field of semiconductor photoelectric devices. The light emitting diode epitaxial wafer comprises a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer and a P-type semiconductor layer arranged on the substrate in sequence, wherein the N-type semiconductor layer comprises M O O3 layer, an N-GaN layer and a thermal oxidation GaN layer, wherein the thermal oxidation GaN layer is obtained by thermal oxidation treatment of the GaN layer; the M O O3 layer is subjected to annealing treatment in an NH3 atmosphere after growth; and the thermal oxidation GaN layer is subjected to annealing treatment in an NH3 atmosphere after growth. By implementing the application, the voltage distribution uniformity of the LED can be improved, and the anti-static capability and surface flatness can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic devices, and more particularly to a light-emitting diode epitaxial wafer and its fabrication method, and an LED. Background Technology

[0002] Currently, GaN-based light-emitting diodes have been widely used in solid-state lighting and display fields, attracting increasing attention. In light-emitting diodes, the N-type semiconductor layer provides electrons and is a very important structure for epitaxial growth. However, existing N-type semiconductor layers still have the following problems: (1) Due to the high N-type doping concentration and two-dimensional block growth of the N-type semiconductor layer, the stress release effect is poor, so the stress and warping during its growth process are very large, making it difficult to do N-type at the edge of the epitaxial wafer. As a result, the closer to the edge of the epitaxial wafer, the less N-type doping there is, so the voltage at the edge of the epitaxial wafer increases significantly, and the voltage distribution uniformity of the epitaxial wafer is poor; (2) The lattice quality and surface flatness at the edge of the epitaxial wafer are relatively poor, which affects the surface flatness and antistatic ability of the epitaxial wafer; (3) The poor lattice quality of the N-type semiconductor layer causes accumulated defects to extend into the multi-quantum well layer, becoming non-radiative recombination centers of charge carriers, affecting its luminous efficiency; (4) The electrons provided by the N-type semiconductor layer move at a fast speed, while the holes move at a slow speed, resulting in electron-hole mismatch in the luminous region and easy entry into the P-type semiconductor layer, affecting the luminous efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an epitaxial wafer for a light-emitting diode and a method for preparing the same, which can improve the voltage distribution uniformity of the LED, enhance its antistatic capability and surface flatness, and improve its luminous efficiency.

[0004] The technical problem that this invention also aims to solve is to provide an LED with high voltage distribution uniformity, high anti-static capability and surface flatness, and high luminous efficiency.

[0005] To address the aforementioned problems, this invention discloses a light-emitting diode epitaxial wafer, comprising a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially disposed on the substrate. The N-type semiconductor layer comprises sequentially stacked M-type semiconductor layers. O The structure comprises an O3 layer, an N-GaN layer, and a thermally oxidized GaN layer, wherein the thermally oxidized GaN layer is obtained by thermally oxidizing the GaN layer.

[0006] The M O After the O3 layer is grown, it is annealed in an NH3 atmosphere.

[0007] After the thermally oxidized GaN layer is grown, it is annealed in an NH3 atmosphere.

[0008] As an improvement to the above technical solution, the M O The thickness of the O3 layer is 10nm to 50nm.

[0009] As an improvement to the above technical solution, the doping element of the N-GaN layer is Si, and the Si doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The thickness of the N-GaN layer is 1 μm to 2 μm.

[0010] As an improvement to the above technical solution, the thickness of the GaN layer is 150nm to 250nm, and the thickness of the thermally oxidized GaN layer is 10nm to 50nm.

[0011] As an improvement to the above technical solution, the GaN layer is subjected to thermal oxidation treatment in a high-temperature oxidation furnace at a temperature of 700℃~900℃ for 10min~20min and an O2 flow rate of 80sccm~120sccm.

[0012] As an improvement to the above technical solution, the M O The annealing temperature for the O3 layer is 450℃~550℃, the annealing pressure is 100torr~300torr, and the annealing time is 30s~120s;

[0013] The annealing temperature of the thermally oxidized GaN layer is 750℃~850℃, the annealing pressure is 100torr~300torr, and the annealing time is 30s~120s.

[0014] Accordingly, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, which includes:

[0015] A substrate is provided on which a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer are sequentially grown; the N-type semiconductor layer comprises sequentially stacked M... O The structure comprises an O3 layer, an N-GaN layer, and a thermally oxidized GaN layer, wherein the thermally oxidized GaN layer is obtained by thermally oxidizing the GaN layer.

[0016] The M O After the O3 layer is grown, it is annealed in an NH3 atmosphere.

[0017] After the thermally oxidized GaN layer is grown, it is annealed in an NH3 atmosphere.

[0018] As an improvement to the above technical solution, the MoO3 layer is grown by the ALD method, with Mo(CO)6 as the Mo source, O3 as the O source, Ar as the carrier gas, and the growth temperature being 150℃~200℃.

[0019] As an improvement to the above technical solution, the N-GaN layer is grown by MOCVD at a growth temperature of 1100℃~1150℃ and a growth pressure of 100 torr~500 torr.

[0020] The GaN layer is grown by MOCVD at a temperature of 1100℃ to 1300℃ and a pressure of 100 torr to 200 torr.

[0021] Accordingly, the present invention also discloses an LED, which includes the above-mentioned light-emitting diode epitaxial wafer.

[0022] Implementing this invention has the following beneficial effects:

[0023] In the epitaxial wafer of the light-emitting diode of the present invention, the N-type semiconductor layer includes M-type semiconductor layers stacked sequentially. O The invention first introduces an O3 layer, an N-GaN layer, and a thermally oxidized GaN layer. O O3 layer, M O The O3 layer can introduce a certain compressive stress, partially offsetting the tensile stress caused by the large difference in thermal expansion coefficients between the intrinsic GaN layer and the substrate. This alleviates the problem of epitaxial wafer warpage and cracking to a certain extent, allowing for more complete release of internal stress and warpage during subsequent N-GaN layer growth. Consequently, the N-type doping distribution is more uniform, improving the voltage distribution uniformity of the epitaxial wafer. Secondly, the present invention M... O After the O3 layer has grown, it is annealed in an NH3 atmosphere to make M O Nitrogen atoms are formed on the O3 layer to change its polarity, resulting in a more orderly arrangement of crystal atoms in the subsequently grown N-GaN layer. This reduces growth defects in the N-GaN layer, improves lattice quality, and enhances luminous efficiency. Furthermore, this invention grows a thermally oxidized GaN layer on the N-GaN layer. The thermally oxidized GaN layer, obtained by thermal oxidation of the GaN layer, has a large bandgap, which blocks electrons generated by the N-GaN layer. This reduces electron congestion caused by excessively high electron mobility in traditional N-type semiconductor layers, increases electron expansion, and improves luminous efficiency. Finally, after the thermally oxidized GaN layer is grown, it undergoes annealing in an NH3 atmosphere. Annealing alters the polarity of the thermally oxidized GaN layer, resulting in a more orderly arrangement of crystal atoms in the subsequently grown multi-quantum well layer. This improves the flatness of the multi-quantum well layer and enhances its antistatic properties. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a light-emitting diode epitaxial wafer in one embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of an N-type semiconductor layer in one embodiment of the present invention;

[0026] Figure 3 This is a flowchart of a method for preparing an epitaxial wafer for a light-emitting diode according to an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0028] refer to Figure 1 and Figure 2 This invention discloses a light-emitting diode epitaxial wafer, comprising a substrate 1 and, sequentially disposed on the substrate 1, a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-type semiconductor layer 7. The N-type semiconductor layer 4 comprises sequentially stacked M... O O3 layer 41, N-GaN layer 42, and thermally oxidized GaN layer 43.

[0029] In this invention, M is introduced. O O3 layer 41, M O The O3 layer 41 can introduce a certain compressive stress, which can partially offset the tensile stress caused by the large difference in thermal expansion coefficients between the intrinsic GaN layer 3 and the substrate 1. This can alleviate the problem of epitaxial wafer warpage and cracking to a certain extent, so that the stress and warpage inside the epitaxial wafer can be released more fully when the N-GaN layer 42 is grown subsequently. As a result, the N-type doping distribution is more uniform, and the voltage distribution uniformity of the epitaxial wafer is improved.

[0030] Specifically, M O The thickness of the O3 layer 41 is 5nm to 55nm. If the thickness is greater than 55nm, defects will occur; if the thickness is less than 5nm, warping cannot be effectively mitigated. Preferably, M... O The thickness of the O3 layer 41 is 10nm to 50nm, with examples of 15nm, 20nm, 25nm, 30nm, 35nm, 40nm or 45nm, but not limited to these.

[0031] Among them, M O After the O3 layer 41 was grown, it was annealed in an NH3 atmosphere to make M O Nitrogen atoms are formed on the O3 layer 41 to change its polarity, which makes the crystal atoms of the subsequently grown N-GaN layer 42 more orderly, reduces growth defects of the N-GaN layer 42, improves lattice quality, and improves luminescence efficiency.

[0032] Specifically, MO The O3 layer 41 is annealed at a temperature of 400℃~600℃, with an annealing pressure of 100 torr~300 torr and an annealing time of 30s~120s. Preferably, M O The O3 layer 41 annealing temperature is 450℃~550℃. Under these conditions, M is obtained. O The surface quality of layer 41 (O3) is relatively high.

[0033] The N-GaN layer 42 is doped with Si, but is not limited to Si. The Si doping concentration is 5.5 × 10⁻⁶. 17 cm -3 ~5.5×10 19 cm -3 If the Si doping concentration is > 5.5 × 10⁻⁶ 19 cm -3 This can lead to excessive stress, severe warping, and uneven Si doping; if the Si doping concentration is <5.5×10 17 cm -3 It is difficult to provide enough electrons. Preferably, the Si doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 For example, the doping concentration of Si is 6 × 10⁻⁶. 18 cm -3 8×10 18 cm -3 1×10 19 cm -3 2×10 19 cm -3 Or 4×10 19 cm -3 However, it is not limited to this.

[0034] Specifically, the thickness of the N-GaN layer 42 is 0.8 μm to 2.5 μm. If the thickness is greater than 2.5 μm, it will introduce too many defects and reduce luminous efficiency; if the thickness is less than 0.8 μm, it will be difficult to provide enough electrons. Preferably, the thickness of the N-GaN layer 42 is 1 μm to 2 μm, with exemplary examples being 1.2 μm, 1.4 μm, 1.6 μm, or 1.8 μm, but not limited thereto.

[0035] In this invention, a thermally oxidized GaN layer 43 is grown on an N-GaN layer 42. The thermally oxidized GaN layer 43 is obtained by thermally oxidizing the GaN layer. Specifically, the GaN layer undergoes thermal oxidation in a high-temperature oxidation furnace at a temperature of 650℃ to 950℃ for 10 to 20 minutes, with an O2 flow rate of 80 sccm to 120 sccm. Preferably, the temperature is 700℃ to 900℃. Under these conditions, the thermally oxidized GaN layer 43 exhibits high surface smoothness.

[0036] The obtained thermally oxidized GaN layer 43 is mainly composed of Ga2O3 and GaON components. The thermally oxidized GaN layer 43 has a large band gap, which blocks electrons generated by the N-GaN layer 42, reduces the electron congestion caused by the excessively high electron mobility in traditional N-type semiconductor layers, increases electron expansion, and improves luminous efficiency.

[0037] Specifically, the thickness of the GaN layer is 120nm to 300nm, preferably 150nm to 250nm, and exemplary are 180nm, 200nm, 220nm, or 240nm, but not limited thereto. Specifically, the thickness of the thermally oxidized GaN layer 43 is 8nm to 60nm. Within this thickness range, it can effectively block electrons. Preferably, the thickness of the thermally oxidized GaN layer 43 is 10nm to 50nm, exemplary are 15nm, 20nm, 25nm, 30nm, 35nm, or 40nm, but not limited thereto.

[0038] After the thermally oxidized GaN layer 43 is grown, it undergoes annealing in an NH3 atmosphere. Annealing alters the polarity of the thermally oxidized GaN layer, resulting in a more orderly arrangement of crystal atoms in the subsequently grown multi-quantum well layer 5, improving its flatness and antistatic properties. Specifically, the annealing temperature for the thermally oxidized GaN layer 43 is 700℃–900℃, the annealing pressure is 100 torr–300 torr, and the annealing time is 30s–120s. Preferably, the annealing temperature is 750℃–850℃. Under these conditions, the thermally oxidized GaN layer 43 exhibits high surface flatness.

[0039] The substrate 1 can be a sapphire substrate or a silicon substrate, but is not limited to these.

[0040] The nucleation layer 2 may be an AlN layer and / or an AlGaN layer, but is not limited thereto. The thickness of the nucleation layer 2 is 20nm to 100nm, with exemplary thicknesses of 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, or 90nm, but is not limited thereto.

[0041] The thickness of the intrinsic GaN layer 3 is 300nm to 800nm, with examples of 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm or 750nm, but not limited to these.

[0042] Among them, the multi-quantum-well layer 5 consists of alternating stacked InGaN quantum well layers and GaN quantum barrier layers, with a stacking period of 3 to 15. The thickness of a single InGaN quantum well layer is 2 nm to 5 nm. The thickness of a single GaN quantum barrier layer is 6 nm to 15 nm.

[0043] Among them, the electron blocking layer 6 is a periodic structure in which AlGaN layers and InGaN layers are grown alternately, with 3 to 15 periods and a thickness of 20 nm to 100 nm.

[0044] The doping element in the P-type semiconductor layer 7 is Mg, but it is not limited to Mg. The doping concentration of Mg in the P-type semiconductor layer 7 is 5 × 10⁻⁶. 17 cm -3 ~1×10 20 cm -3 The thickness of the P-type semiconductor layer 7 is 200nm to 300nm.

[0045] Accordingly, refer to Figure 3 The present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, which includes the following steps:

[0046] S100: Provides a substrate;

[0047] Specifically, the substrate is a sapphire substrate or a silicon substrate, but is not limited to these. A sapphire substrate is preferred.

[0048] Preferably, in one embodiment of the present invention, the substrate is loaded into MOCVD and annealed at 1000°C to 1200°C, 200 to 600 tor, in a hydrogen atmosphere for 5 to 8 minutes to remove impurities such as particles and oxides from the substrate surface.

[0049] S200: Nucleation layer is grown on the substrate;

[0050] Specifically, an AlGaN layer can be grown using MOCVD or PVD, but is not limited to these methods. Preferably, the AlGaN layer is grown using MOCVD at a growth temperature of 500℃–700℃ and a growth pressure of 200 torr–400 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source; H2 and N2 are used as carrier gases; TMAl is introduced as the Al source; and TMGa is introduced as the Ga source.

[0051] S300: Intrinsic GaN layers are grown on the nucleation layer;

[0052] Specifically, in one embodiment of the present invention, an intrinsic GaN layer is grown in MOCVD at a growth temperature of 1100°C to 1150°C and a growth pressure of 100 torr to 500 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as an N source; H2 and N2 are used as carrier gases, and TMGa is introduced as a Ga source.

[0053] S400: An N-type semiconductor layer is grown on an intrinsic GaN layer;

[0054] Specifically, the fabrication method of each N-type semiconductor layer includes:

[0055] S410: M grown on intrinsic GaN layer O O3 layer;

[0056] Specifically, in one embodiment of the present invention, M is grown by the ALD method. O The O3 layer was grown at a temperature of 150℃ to 200℃. The Mo source used during growth was Mo(CO)6, the O source was O3, and the carrier gas was Ar.

[0057] S420:M O The O3 layer was annealed in an NH3 atmosphere;

[0058] Specifically, in one embodiment of the present invention, MOCVD annealing is used, with an annealing temperature of 400℃~600℃, an annealing pressure of 100 torr~300 torr, and an annealing time of 30s~120s. Preferably, in another embodiment of the present invention, M... O The annealing temperature for the O3 layer is 450℃~550℃.

[0059] S430: M after annealing O An N-GaN layer is grown on the O3 layer;

[0060] Specifically, N-GaN layers are grown in MOCVD at temperatures ranging from 1100℃ to 1150℃ and growth pressures ranging from 100 torr to 500 torr. During growth, NH3 is introduced as the N source, SiH4 as the Si source, and TMGa as the Ga source into the MOCVD reaction chamber, with H2 and N2 used as carrier gases. Using a high growth temperature and low growth pressure is more conducive to improving the flatness of the epitaxial wafer.

[0061] S440: Thermally oxidized GaN layer grown on N-GaN layer;

[0062] S441: Growing a GaN layer on an N-GaN layer;

[0063] Specifically, GaN layers were grown using MOCVD at a temperature of 1100℃ to 1300℃ and a pressure of 100 torr to 200 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as the N source, H2 and N2 were used as carrier gases, and TEGa was introduced as the Ga source.

[0064] S442: Thermal oxidation treatment of GaN layer;

[0065] Specifically, in one embodiment of the present invention, the GaN layer obtained in step S441 is subjected to thermal oxidation treatment in a high-temperature oxidation furnace at a temperature of 650°C to 950°C for 10 to 20 minutes, with an O2 flow rate of 80 sccm to 120 sccm. Preferably, in another embodiment of the present invention, the treatment temperature is 700°C to 900°C.

[0066] S450: The thermally oxidized GaN layer is annealed in an NH3 atmosphere;

[0067] Specifically, in one embodiment of the present invention, MOCVD annealing is used, with an annealing temperature of 750℃~850℃, an annealing pressure of 100 torr~300 torr, and an annealing time of 30s~120s. Preferably, in another embodiment of the present invention, the annealing temperature is 750℃~850℃.

[0068] S500: A multi-quantum-well layer is grown on an N-type semiconductor layer;

[0069] Specifically, quantum well layers and quantum barrier layers are periodically grown in MOCVD to form multiple quantum well layers. The growth temperature of the quantum well layers is 700℃–800℃, and the growth pressure is 100 torr–500 torr. During growth, NH3 is introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source in the MOCVD reaction chamber. The growth temperature of the quantum barrier layers is 800℃–900℃, and the growth pressure is 100 torr–500 torr. During growth, NH3 is introduced as the N source, H2 and N2 as the carrier gases, and TEGa as the Ga source in the MOCVD reaction chamber.

[0070] S600: An electron blocking layer is grown on a multi-quantum-well layer;

[0071] Specifically, AlGaN and InGaN layers are periodically grown in MOCVD as electron blocking layers. The AlGaN layer is grown at a temperature of 900℃–1000℃ and a growth pressure of 100 torr–500 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source, N2 and H2 are used as carrier gases, TMAl is introduced as the Al source, and TMGa is introduced as the Ga source. The InGaN layer is grown at a temperature of 900℃–1000℃ and a growth pressure of 100 torr–500 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source, N2 and H2 are used as carrier gases, TMIn is introduced as the In source, and TMGa is introduced as the Ga source.

[0072] S700: A P-type semiconductor layer is grown on an electron blocking layer;

[0073] Specifically, a P-type semiconductor layer is grown in MOCVD at a temperature of 800℃ to 1000℃ and a pressure of 100 torr to 300 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as an N source, and Cp2Mg is introduced as a P-type doping source; H2 and N2 are used as carrier gases, and TMGa is introduced as a Ga source.

[0074] The present invention will be further described below with reference to specific embodiments:

[0075] Example 1

[0076] This embodiment provides a light-emitting diode epitaxial wafer, referenced... Figure 1 , Figure 2 It includes a substrate 1 and a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-type semiconductor layer 7 sequentially disposed on the substrate 1.

[0077] The substrate 1 is a sapphire substrate, the nucleation layer 2 is an AlGaN layer with a thickness of 30nm, and the intrinsic GaN layer 3 has a thickness of 400nm.

[0078] Among them, the N-type semiconductor layer 4 includes M layers stacked sequentially. O O3 layer 41, N-GaN layer 42, and thermally oxidized GaN layer 43. Among them, M... O The thickness of layer 41 (O3) is 55 nm. O After the O3 layer 41 was grown, it was annealed in an NH3 atmosphere at a temperature of 400℃, a pressure of 200 torr, and a time of 100s. The N-GaN layer 42 was doped with Si at a concentration of 5.5 × 10⁻⁶. 17 cm -3The thickness of the N-GaN layer 42 is 0.8 μm. The thermally oxidized GaN layer 43 is obtained by thermal oxidation of the GaN layer at a temperature of 650℃ for 15 min and an O2 flow rate of 100 sccm. The thickness of the GaN layer is 300 nm, and the thickness of the thermally oxidized GaN layer 43 is 60 nm. After the thermally oxidized GaN layer 43 is grown, it is annealed in an NH3 atmosphere at a temperature of 700℃, an annealing pressure of 200 torr, and an annealing time of 100 s.

[0079] Among them, the multi-quantum well layer 5 consists of alternating stacked InGaN quantum well layers and GaN quantum barrier layers, with a stacking period of 10. The thickness of a single InGaN quantum well layer is 3nm, and the thickness of a single GaN quantum barrier layer is 10nm.

[0080] Among them, electron blocking layer 6 is a periodic structure with alternating AlGaN and InGaN layers, with a period number of 8. The thickness of a single AlGaN layer is 6 nm, and the thickness of a single InGaN layer is 6 nm. The P-GaN layer 7 is doped with Mg at a doping concentration of 3.5 × 10⁻⁶. 19 cm -3 The thickness is 240nm.

[0081] The method for fabricating an epitaxial wafer for a light-emitting diode in this embodiment includes the following steps:

[0082] (1) Provide a substrate; load the substrate into MOCVD and anneal it at 1120℃, 400 torr, and hydrogen atmosphere for 6 min.

[0083] (2) Growing a nucleation layer on a substrate;

[0084] Specifically, the AlGaN layer was grown using MOCVD at a growth temperature of 620℃ and a growth pressure of 250 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as the N source; H2 and N2 were used as carrier gases; TMAl was introduced as the Al source; and TMGa was introduced as the Ga source.

[0085] (3) Grow an intrinsic GaN layer on the nucleation layer;

[0086] Specifically, intrinsic GaN layers were grown using MOCVD at a growth temperature of 1100℃ and a growth pressure of 250 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as the N source, and H2 and N2 were used as carrier gases, while TMGa was introduced as the Ga source.

[0087] (4) Grow an N-type semiconductor layer on the intrinsic GaN layer;

[0088] Specifically, the fabrication method of each N-type semiconductor layer includes:

[0089] (I) Growing M on intrinsic GaN layers O O3 layer;

[0090] Specifically, M is grown using the ALD method. O The O3 layer was grown at a temperature of 180℃. The Mo source used during growth was Mo(CO)6, the O source was O3, and the carrier gas was Ar.

[0091] (Ⅱ)M O The O3 layer was annealed in an NH3 atmosphere;

[0092] Specifically, MOCVD annealing was used, with an annealing temperature of 400℃, an annealing pressure of 200 torr, and an annealing time of 100s.

[0093] (III) M after annealing O An N-GaN layer is grown on the O3 layer;

[0094] Specifically, an N-GaN layer was grown in MOCVD at a growth temperature of 1120℃ and a growth pressure of 300 torr. During growth, NH3 was introduced as the N source, SiH4 as the Si source, and TMGa as the Ga source into the MOCVD reaction chamber, with H2 and N2 used as carrier gases.

[0095] (Ⅳ) Growth of thermally oxidized GaN layer on N-GaN layer;

[0096] (i) Growing a GaN layer on an N-GaN layer;

[0097] Specifically, GaN layers were grown using MOCVD at a temperature of 1200℃ and a pressure of 150 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as the N source, H2 and N2 were used as carrier gases, and TEGa was introduced as the Ga source.

[0098] (ii) Thermal oxidation treatment of GaN layer;

[0099] Specifically, the GaN layer obtained in step (i) is subjected to thermal oxidation in a high-temperature oxidation furnace at a temperature of 650°C for 15 min and an O2 flow rate of 100 sccm.

[0100] (V) The thermally oxidized GaN layer was annealed in an NH3 atmosphere;

[0101] Specifically, MOCVD annealing was used, with a processing temperature of 700℃, an annealing pressure of 200 torr, and an annealing time of 100s.

[0102] (5) Growing a multi-quantum-well layer on an N-type semiconductor layer;

[0103] Specifically, quantum well layers and quantum barrier layers are periodically grown in MOCVD to obtain multiple quantum well layers;

[0104] The quantum well layer is grown at a temperature of 750℃ and a growth pressure of 300 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source, N2 is introduced as the carrier gas, TEGa is introduced as the Ga source, and TMIn is introduced as the In source. The quantum barrier layer is grown at a temperature of 820℃ and a growth pressure of 300 torr. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source, H2 and N2 are introduced as the carrier gases, and TEGa is introduced as the Ga source.

[0105] (6) Grow an electron blocking layer on a multi-quantum-well layer;

[0106] Specifically, AlGaN and InGaN layers are periodically grown in MOCVD as electron blocking layers. The AlGaN layer is grown at 950℃ and 250 torr at a growth pressure. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source, N2 and H2 are used as carrier gases, TMAl is introduced as the Al source, and TMGa is introduced as the Ga source. The InGaN layer is grown at 950℃ and 250 torr at a growth pressure. During growth, NH3 is introduced into the MOCVD reaction chamber as the N source, N2 and H2 are used as carrier gases, TMIn is introduced as the In source, and TMGa is introduced as the Ga source.

[0107] (7) Grow a P-type semiconductor layer on the electron blocking layer;

[0108] Specifically, a P-type semiconductor layer was grown in MOCVD at a growth temperature of 900℃ and a growth pressure of 200 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as an N source, and Cp2Mg was introduced as a P-type doping source; H2 and N2 were used as carrier gases, and TMGa was introduced as a Ga source.

[0109] Example 2

[0110] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that M O The thickness of layer 41 (O3) is 30 nm.

[0111] Everything else is the same as in Example 1.

[0112] Example 3

[0113] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 2 in that M O The O3 layer 41 annealing temperature is 450℃.

[0114] Everything else is the same as in Example 2.

[0115] Example 4

[0116] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 3 in that the Si doping concentration in the N-GaN layer 42 is 1×10⁻⁶. 19 cm -3 The thickness of the N-GaN layer 42 is 1.6 μm.

[0117] Everything else is the same as in Example 3.

[0118] Example 5

[0119] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 4 in that the thickness of the GaN layer is 200 nm and the thickness of the thermally oxidized GaN layer 43 is 30 nm.

[0120] Everything else is the same as in Example 4.

[0121] Example 6

[0122] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 5 in that the thermal oxidation temperature of the GaN layer 43 is 700°C.

[0123] Everything else is the same as in Example 5.

[0124] Example 7

[0125] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 6 in that the thermal oxidation GaN layer 43 is annealed at a temperature of 750°C.

[0126] Everything else is the same as in Example 6.

[0127] Comparative Example 1

[0128] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the N-type semiconductor layer 4 does not include the M-type semiconductor layer. O The O3 layer 41 and the thermally oxidized GaN layer 43 are prepared in the same way as in Example 1, but the preparation steps and annealing steps for these two layers are not included in the preparation method.

[0129] Comparative Example 2

[0130] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that the N-type semiconductor layer 4 does not include a thermally oxidized GaN layer 43. Correspondingly, the fabrication method omits the preparation and annealing steps for this layer. Furthermore, M... O After the O3 layer 41 is grown, no annealing treatment is performed; all other aspects are the same as in Example 1.

[0131] Comparative Example 3

[0132] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that the N-type semiconductor layer 4 does not include a thermally oxidized GaN layer 43. Correspondingly, the preparation step and annealing step of this layer are not included in the preparation method. All other aspects are the same as in Example 1.

[0133] Comparative Example 4

[0134] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that the thermally oxidized GaN layer 43 is not annealed after growth, but otherwise it is the same as Example 1.

[0135] The epitaxial wafers of the light-emitting diodes obtained in Examples 1-7 and Comparative Examples 1-4 were tested using the following specific testing methods:

[0136] (1) Take 20 epitaxial wafers prepared in each example and comparative example, measure their working voltage, and calculate their relative standard deviation, which is the working voltage uniformity.

[0137] (2) Brightness: The epitaxial wafer was fabricated into a chip with a vertical structure of 10mil×24mil, and its luminous brightness was tested;

[0138] (3) Antistatic capability test: Antistatic performance test: The antistatic performance of the base chip is tested using an electrostatic meter under the HBM (human body discharge model) model. The percentage of chips that can withstand reverse 6000V static electricity is tested.

[0139] (4) Roughness: Surface roughness was tested using an atomic force microscope (AFM, model NanoScope MultiMode).

[0140] The specific results are as follows:

[0141]

[0142] As can be seen from the table, when the traditional N-type semiconductor layer (Comparative Example 1) is replaced with the N-type semiconductor layer structure of the present invention, the working voltage uniformity is improved from 0.13 to 0.11, indicating that the N-type semiconductor layer of the present invention can effectively improve the working voltage uniformity. When the traditional N-type semiconductor layer (Comparative Example 1) is replaced with the N-type semiconductor layer structure of the present invention, the brightness is increased from 193.2mw to 195.1mw, the antistatic capability is increased from 94.5% to 96.2%, and the surface roughness is reduced from 0.22nm to 0.20nm, indicating that the N-type semiconductor layer of the present invention can improve luminous efficiency, improve antistatic capability, and reduce surface roughness.

[0143] Furthermore, a comparison between Example 1 and Comparative Examples 2-4 shows that when the N-type semiconductor layer structure in this invention is changed, it is difficult to effectively improve the uniformity of voltage distribution, increase brightness, improve antistatic ability, and reduce surface roughness.

[0144] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light-emitting diode epitaxial wafer, comprising a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially disposed on the substrate, characterized in that, The N-type semiconductor layer includes M layers stacked sequentially. O The system comprises an O3 layer, an N-GaN layer, and a thermally oxidized GaN layer, wherein the thermally oxidized GaN layer is obtained by thermally oxidizing the GaN layer at a temperature of 700℃~900℃ for 10min~20min and an O2 flow rate of 80sccm~120sccm. The N-GaN layer is doped with Si, and the Si doping concentration is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The thickness of the N-GaN layer is 1 μm to 2 μm; The M O After the O3 layer is grown, it is annealed in an NH3 atmosphere. After the thermally oxidized GaN layer is grown, it is annealed in an NH3 atmosphere.

2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The M O The thickness of the O3 layer is 10nm~50nm.

3. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The thickness of the GaN layer is 150nm~250nm, and the thickness of the thermally oxidized GaN layer is 10nm~50nm.

4. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The M O The annealing temperature for the O3 layer is 450℃~550℃, the annealing pressure is 100 torr~300 torr, and the annealing time is 30s~120s. The annealing temperature of the thermally oxidized GaN layer is 750℃~850℃, the annealing pressure is 100 torr~300 torr, and the annealing time is 30s~120s.

5. A method for preparing a light-emitting diode epitaxial wafer, used to prepare a light-emitting diode epitaxial wafer as described in any one of claims 1 to 4, characterized in that, include: A substrate is provided on which a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer are sequentially grown; the N-type semiconductor layer comprises sequentially stacked M... O The structure comprises an O3 layer, an N-GaN layer, and a thermally oxidized GaN layer, wherein the thermally oxidized GaN layer is obtained by thermally oxidizing the GaN layer. The M O After the O3 layer is grown, it is annealed in an NH3 atmosphere. After the thermally oxidized GaN layer is grown, it is annealed in an NH3 atmosphere.

6. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, The MoO3 layer was grown by the ALD method, with Mo(CO)6 as the Mo source, O3 as the O source, Ar as the carrier gas, and the growth temperature being 150℃~200℃.

7. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, The N-GaN layer is grown by MOCVD at a growth temperature of 1100℃~1150℃ and a growth pressure of 100 torr~500 torr. The GaN layer is grown by MOCVD at a temperature of 1100℃~1300℃ and a growth pressure of 100 torr~200 torr.

8. A light-emitting diode, characterized in that, Includes a light-emitting diode epitaxial wafer as described in any one of claims 1 to 4.

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