A kind of overcurrent protection and detection circuit suitable for class AB output stage

Abstract

The application discloses a kind of overcurrent protection and detection circuit suitable for AB class output stage, belong to integrated circuit field, including pull current overcurrent protection module, filling current protection module and overcurrent / short circuit detection module.Pull current overcurrent protection module is connected with AB class output stage, for limiting the pull current of AB class output stage, protect output stage PMOS power tube;Filling current overcurrent protection module is connected with AB class output stage, for limiting the filling current of AB class output stage, protect output stage NMOS power tube;Overcurrent / short circuit detection module is simultaneously connected with the pull current overcurrent protection module, the filling current overcurrent protection module of module, for generating overcurrent or short circuit signal;AB class output stage is used for power amplifier last stage, for driving large current load.The application can limit load current in time when overcurrent or short circuit occurs in circuit, avoid damaging to circuit, make circuit more safe and stable.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an overcurrent protection and detection circuit suitable for Class AB output stages. Background Technology

[0002] Compared to Class A amplifiers, Class AB amplifiers offer reduced quiescent power consumption and improved power conversion efficiency, while exhibiting lower distortion compared to Class B amplifiers. Therefore, most power amplifier output stages utilize a Class AB architecture. Power amplifiers with Class AB output stages are commonly used in audio circuits such as headphone drivers, offering the ability to drive high currents.

[0003] Generally, the width-to-length ratio of output power PMOS transistors can reach 10,000 times. When the amplifier output is short-circuited to the power supply or ground, a current greater than 1A will be generated. This large transient current can not only damage the output transistor, but may even cause the entire circuit system to collapse. Therefore, overcurrent detection and protection circuits are crucial.

[0004] The core technology of overcurrent protection and detection circuits is current sensing. Currently, there are three ways to sense current: 1) connect a resistor in series with the power transistor to convert the current magnitude into a voltage difference across the resistor; 2) use a sampling MOSFET (scaled down) connected in parallel with the power transistor to sense the current; 3) sense the output current by combining a current-sensing resistor and a current-sensing MOSFET.

[0005] However, the first method not only sacrifices the amplifier's output swing, but also, due to the temperature-dependent characteristics of the resistors, causes the current limit value to be affected by process technology and temperature. The second method, while not reducing the output swing, has a sampling current proportional to the load current; under high load currents, especially when short-circuited to ground or power supply, the quiescent current will increase significantly. The third method is a combination of the first and third methods, using an additional parallel MOSFET to sense the current, with a resistor connected in series with the MOSFET to reduce the quiescent current, but the current limit value remains inaccurate. To avoid this situation, an overcurrent protection and detection circuit is urgently needed. Summary of the Invention

[0006] The purpose of this invention is to provide an overcurrent protection and detection circuit suitable for Class AB output stages, so as to solve the problems in the background art.

[0007] To solve the above technical problems, the present invention provides an overcurrent protection and detection circuit suitable for Class AB output stages, including a source current overcurrent protection module, a sink current protection module, and an overcurrent / short circuit detection module;

[0008] The overcurrent protection module is connected to the Class AB output stage and is used to limit the sourcing current of the Class AB output stage and protect the PMOS power transistor of the output stage.

[0009] The sinking current overcurrent protection module is connected to the AB class output stage and is used to limit the sinking current of the AB class output stage to protect the NMOS power transistor of the output stage.

[0010] The overcurrent / short circuit detection module is connected to both the pull-in current overcurrent protection module and the sink current overcurrent protection module to generate overcurrent or short circuit signals.

[0011] The Class AB output stage is used as the last stage of the power amplifier to drive high-current loads.

[0012] In one embodiment, the class AB output stage includes a PMOS transistor MPP and an NMOS transistor MNP; wherein,

[0013] The source of the PMOS transistor MPP is connected to the power supply VDD, and the gate and drain are both connected to the source current overcurrent protection module; the source of the NMOS transistor MNP is grounded, and the gate and drain are both connected to the sink current overcurrent protection module.

[0014] The drain of the PMOS transistor MPP is connected to the drain of the NMOS transistor MNP to form the VOUT output terminal of the class AB output stage. This output terminal VOUT can be connected to an external load capacitor and resistor to drive a large current.

[0015] In one embodiment, the traction current overcurrent protection module includes a traction current overcurrent limiting unit, a traction current foldback current limiting unit, and a traction current detection unit;

[0016] The pull-up current overcurrent limiting unit is connected to both the VOUT output terminal of the AB class output stage and the gate of the PMOS transistor MPP, and is used for pull-up current monitoring and overcurrent limiting.

[0017] The current pull-back current limiting unit is connected to both the VOUT output terminal of the AB class output stage and the internal port of the current pull-back overcurrent limiting unit, and is used to limit the current short-circuited to ground at the VOUT output terminal;

[0018] The current traction detection unit is connected to the internal port of the current traction overcurrent limiting unit and the internal port of the current traction return current limiting unit, and is used to amplify the overcurrent detection and short-circuit to ground detection signals in reverse.

[0019] The current sourcing overcurrent protection module has a current sourcing overcurrent detection signal of VS1 and a short circuit to ground detection signal of VS2; a high level signal VS1 indicates overcurrent, and a high level signal VS2 indicates short circuit.

[0020] In one embodiment, the pull-up current overcurrent limiting unit includes NMOS transistors MN1 to MN5, PMOS transistors MP1 to MP5, and a PMOS sampling transistor MPR;

[0021] The gate of NMOS transistor MN1 is connected to the VOUT output terminal, and its source is connected to the source of PMOS transistor MP1. The gate and drain of PMOS transistor MP1 are connected to the source of NMOS transistor MN2.

[0022] The drain of PMOS transistor MP2 is connected to both the drain and gate of NMOS transistor MN2, and the source of NMOS transistor MN2 is connected to the drain of NMOS transistor MN3.

[0023] The gate of the PMOS sampling transistor MPR is connected to the gate of the PMOS transistor MPP, and the drain is connected to the source of the PMOS transistor MP3. The gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2, and the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN4.

[0024] The drain of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5 and the drain of NMOS transistor MN5. The gate of NMOS transistor MN5 is connected to the gate and drain of NMOS transistor MN4. The drain of PMOS transistor MP5 is connected to the gate of PMOS transistor MPP.

[0025] The drain of NMOS transistor MN1, the source of PMOS transistor MP2, the source of PMOS sampling transistor MPR, the source of PMOS transistor MP4, and the source of PMOS transistor MP5 are all connected to the power supply VDD; the sources of NMOS transistors MN3 to MN5 are all grounded.

[0026] In one embodiment, the pull-back current limiting unit includes a PMOS transistor MP6, an NMOS transistor MN6, and a resistor R1; the source of the PMOS transistor MP6 and the first terminal of the resistor R1 are both connected to the power supply VDD, the drain of the PMOS transistor MP6 is connected to the gate of the PMOS transistor MPP, the gate is connected to the second terminal of the resistor R1 and the drain of the NMOS transistor MN6, the gate of the NMOS transistor MN6 is connected to the drain of the PMOS transistor MP3, and the source of the NMOS transistor MN6 is connected to the VOUT output terminal.

[0027] In one embodiment, the current sourcing detection unit includes NMOS transistors MN7 and MN8, and PMOS transistors MP7 and MP8; the sources of PMOS transistors MP7 and MP8 are both connected to the power supply VDD, and the sources of NMOS transistors MN7 and MN8 are both grounded.

[0028] The gate of PMOS transistor MP7 is connected to the drain of NMOS transistor MN5, and the drain is connected to signal VS1; the gate of PMOS transistor MP8 is connected to the drain of NMOS transistor MN6, and the drain is connected to signal VS2.

[0029] The gate and drain of NMOS transistor MN7 are both connected to signal VS1; the gate and drain of NMOS transistor MN8 are both connected to signal VS2.

[0030] In one embodiment, the sinking current overcurrent protection module includes a sinking current overcurrent limiting unit, a sinking current foldback current limiting unit, and a sinking current detection unit.

[0031] The sink current overcurrent limiting unit is connected to both the VOUT output terminal of the AB class output stage and the gate of the NMOS transistor MNP, and is used for sink current monitoring and overcurrent limiting.

[0032] The sinking current foldback current limiting unit is connected to both the VOUT output terminal of the AB class output stage and the internal port of the sinking current overcurrent limiting unit, and is used to limit the current from the VOUT output terminal to the power supply when short-circuited.

[0033] The sinking current detection unit is connected to the internal port of the sinking current overcurrent limiting unit and the internal port of the sinking current foldback current limiting unit, and is used to amplify the overcurrent detection and short circuit to power supply detection signals in reverse.

[0034] The sinking current overcurrent protection module has a sinking current overcurrent detection signal of VS3 and a short circuit to power supply detection signal of VS4; a low level of signal VS3 indicates a short circuit, and a low level of signal VS4 indicates a short circuit.

[0035] In one embodiment, the sink current overcurrent limiting unit includes NMOS transistors MN9 to MN13, PMOS transistors MP9 to MP13, and an NMOS sampling transistor MNR;

[0036] The drain of PMOS transistor MP10 is simultaneously connected to the source of PMOS transistor MP11, the drain and gate of NMOS transistor MN9, and the gate and drain of PMOS transistor MP11 are simultaneously connected to the drain of NMOS transistor MN10. The source of NMOS transistor MN9 is connected to the source of PMOS transistor MP9, and the gate of PMOS transistor MP9 is connected to the OUT output terminal.

[0037] The gate of PMOS transistor MP13 is connected to both the gate and drain of PMOS transistor MP12. The drain of PMOS transistor MP13 is connected to both the gate of NMOS transistor MN13 and the drain of NMOS transistor MN12. The drain of NMOS transistor MN13 is connected to the gate of NMOS transistor MNP.

[0038] The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN11, the gate of NMOS transistor MN11 is connected to the drain of NMOS transistor MN10, the source of NMOS transistor MN11 is connected to the drain of NMOS sampling transistor MNR, and the gate of NMOS sampling transistor MNR is connected to the gate of NMOS transistor MNP.

[0039] The drain of PMOS transistor MP9, the source of PMOS transistor MP10, the source of NMOS sampling transistor MNR, the source of NMOS transistor MN12, and the source of NMOS transistor MN13 are all grounded; the source of PMOS transistor MP10, the source of PMOS transistor MP12, and the source of PMOS transistor MP13 are all connected to the power supply VDD.

[0040] In one embodiment, the current sinking and foldback limiting unit includes a PMOS transistor MP14, an NMOS transistor MN14, and a resistor R2; the source of the PMOS transistor MP14 is connected to the OUT output terminal, the gate is connected to the drain of the NMOS transistor MN11, the drain is connected to both the first end of the resistor R2 and the gate of the NMOS transistor MN14, the second end of the resistor R2 is grounded, the drain of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MNP, and the source is grounded.

[0041] In one embodiment, the sink current detection unit includes PMOS transistors MP15 and MP16, and NMOS transistors MN15 and MN16; the sources of PMOS transistors MP15 and MP16 are both connected to the power supply VDD, and the sources of NMOS transistors MN15 and MN16 are both grounded.

[0042] The gate and drain of PMOS transistor MP15 are both connected to signal VS3, and the gate and drain of PMOS transistor MP16 are both connected to signal VS4.

[0043] The drain of NMOS transistor MN15 is connected to signal VS3, and its gate is connected to the drain of PMOS transistor MP13; the drain of NMOS transistor MN16 is connected to signal VS4, and its gate is connected to the drain of PMOS transistor MP14.

[0044] In one embodiment, the overcurrent / short-circuit detection module includes two buffers, two inverters, and three OR gates; wherein,

[0045] The inputs of the two buffers are signals VS1 and VS2 from the current sourcing overcurrent protection module, respectively, and the outputs of the two buffers are the inputs of an OR gate. The inputs of the two inverters are signals VS3 and VS4 from the current sourcing overcurrent protection module, respectively, and the outputs of the two inverters are the inputs of another OR gate. The outputs of these two OR gates are the inputs of a third OR gate, and the relationship between the output signal VFLAG of the third OR gate and its inputs is as follows: When VS1 is high, VS2 is high, VS3 is low, or VS4 is low, the VFLAG signal is high, indicating that there is an overcurrent in the circuit, either pulling or sinking, or that the circuit is short-circuited to the power supply or ground. Users can shut down the circuit by detecting the VFLAG signal.

[0046] This invention provides an overcurrent protection and detection circuit suitable for Class AB output stages. It can promptly limit the load current when an overcurrent or short circuit occurs, preventing damage to the circuit and making it safer and more stable. Compared with existing technologies, this invention has the following advantages:

[0047] (1) The transient power consumption is smaller. A MOS transistor is connected in series at the drain of the traditional MOS sampling transistor that is parallel to the power transistor to avoid excessive current when the sampling MOS transistor is transiently turned on.

[0048] (2) The sampling current is more accurate, so that the drain of the sampling MOS transistor is as close as possible to the output of the amplifier, further reducing the channel modulation effect;

[0049] (3) The short-circuit power consumption is smaller, and a foldback current limiting circuit is added to the circuit; when the circuit is short-circuited to the power supply or ground, the circuit will further limit the load current.

[0050] (4) The short-circuit limiting current value is smaller than the overcurrent limiting current value, which also means lower power consumption. Attached Figure Description

[0051] Figure 1 This invention provides a block diagram of an overcurrent protection and detection circuit suitable for Class AB output stages.

[0052] Figure 2 This is a schematic diagram of a current-carrying overcurrent protection module.

[0053] Figure 3 For the V in the overcurrent protection module N3 V N2 A schematic diagram showing the curve of VOUT voltage variation.

[0054] Figure 4 This is a schematic diagram of the overcurrent protection module.

[0055] Figure 5 This is a schematic diagram of the overcurrent / short circuit detection module.

[0056] Figure 6 This is a schematic diagram of the simulation setup for a Class AB amplifier with overcurrent protection and detection circuitry.

[0057] Figure 7 A schematic diagram of the transient simulation results with an 8Ω resistor connected to the load for simulation settings.

[0058] Figure 8 A schematic diagram of the overcurrent transient simulation results with a 4Ω resistor connected to the load, as shown in the simulation settings.

[0059] Figure 9 This is a schematic diagram of the transient simulation results of VOUT short-circuiting to ground.

[0060] Figure 10 This is a schematic diagram of the transient simulation results of VOUT under power supply short circuit. Detailed Implementation

[0061] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of an overcurrent protection and detection circuit suitable for Class AB output stages proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0062] This invention provides an overcurrent protection and detection circuit suitable for Class AB output stages, and its block diagram is as follows. Figure 1 As shown, the overcurrent protection and detection circuit mainly includes a source current overcurrent protection module, a sink current overcurrent protection module, and an overcurrent / short circuit detection module.

[0063] The Class AB output stage is the last stage of the power amplifier, used to drive large load currents; the first and second stages of the power amplifier (if any) can be implemented using existing technologies. Figure 1 As shown, the Class AB output stage includes a PMOS transistor MPP and an NMOS transistor MNP; the gate port of the PMOS transistor MPP is VP1, and the gate port of the NMOS transistor MNP is VN1. The drains of the PMOS transistor MPP and the NMOS transistor MNP are connected, and their drains are connected to the port VOUT, which is connected to an external load. In this embodiment, the aspect ratio of the PMOS transistor MPP is 11294, and the aspect ratio of the NMOS transistor MNP is 3753.

[0064] When the circuit experiences a current surge or a short circuit to ground at port VOUT, the PMOS transistor MPP, being the main power transistor, withstands a large current. Therefore, the current surge overcurrent protection module primarily samples the current of the PMOS transistor MPP and generates an overcurrent detection signal VS1 (high level for overcurrent) and a short circuit to ground detection signal VS2 (high level for short circuit).

[0065] When the circuit experiences current sinking or a short circuit to the power supply at port VOUT, the NMOS transistor MNP, being the primary power transistor, withstands a large current. Therefore, the current sinking overcurrent protection module primarily samples the current of the NMOS transistor MNP and generates an overcurrent detection signal VS3 (low level indicates overcurrent) and a short circuit to power supply detection signal VS4 (low level indicates short circuit).

[0066] Signals VS1, VS2, VS3, and VS4 serve as inputs to the overcurrent / short-circuit detection module, undergoing a series of combinational logic steps to output the final overcurrent / short-circuit signal VFLAG.

[0067] like Figure 2The diagram shows the structural schematic of the sourcing current overcurrent protection module and the Class AB output stage. The sourcing current overcurrent protection module mainly includes a sourcing current overcurrent limiting unit, a sourcing current foldback limiting unit, and a sourcing current detection unit. The sourcing current overcurrent limiting unit contains a PMOS sampling transistor MPR, which is a proportional copy of the PMOS transistor MPP in the Class AB output stage (W / L). MPP :(W / L) MPR = 144:1, where (W / L) MPP It is the width-to-length ratio (W / L) of the PMOS transistor MPP. MPR This is the width-to-length ratio of the PMOS sampling transistor MPR. The gate of the PMOS sampling transistor MPR is connected to the gate of the PMOS transistor MPP, and the drain of the PMOS sampling transistor MPR is connected to the source of the PMOS transistor MP3.

[0068] The NMOS transistors MN1, MN2, and MN3, and the PMOS transistors MP1, MP2, and MP3 form a current-source voltage follower circuit (VOUT), see [link to circuit description]. Figure 2 The dashed box in the image. To reduce the channel length modulation effect and make the copy current of the PMOS sampling transistor MPR more accurate, the drain voltage V of the PMOS sampling transistor MPR is... N3 The voltage should be as close as possible to the port VOUT voltage. Therefore, the design of the PMOS transistor MP3 is particularly critical in this embodiment. The drain voltage of the PMOS sampling transistor MPR... Where V N1 It is the drain voltage of PMOS transistor MP2. This represents the source-gate voltage of the PMOS transistor MP3. The PMOS transistor MP3 has a relatively large aspect ratio, making... therefore in This represents the threshold voltage of PMOS transistor MP3. In this embodiment, the quiescent current of PMOS transistor MP2 in the saturation region is 5uA, and the quiescent current of NMOS transistor MN3 in the saturation region is 10uA. The gate of NMOS transistor MN1 is connected to port VOUT. When the voltage at port VOUT is extremely low, NMOS transistor MN1 is turned off, no current flows, and NMOS transistor MN3 enters the linear region. N1 Reaching the minimum value, in This represents the source-gate voltage of NMOS transistor MN2. When in This represents the threshold voltage of NMOS transistor MN1. VOUT represents the source-gate voltage of PMOS transistor MP1. NMOS transistor MN1 gradually turns on; the larger the VOUT voltage, the larger the conduction current of NMOS transistor MN1. NMOS transistor MN3 gradually transitions from the linear region to the saturation region, and its quiescent current also continuously increases. The source voltage VOUT of NMOS transistor MN2... N2The potential continues to rise. The potential also continues to rise. Therefore, when when V N1 ∝VOUT, Designed in this embodiment Then V N3 ≈VOUT. V N3 V N2 The curve showing the change in voltage with VOUT is shown below. Figure 3 .Depend on Figure 3 It can be seen that when VOUT voltage > 1.6V, V N3 It is close to VOUT. In summary, this current-pull VOUT voltage follower circuit has the following two advantages: 1) When the amplifier suddenly short-circuits to ground, it limits the conduction current of the PMOS sampling transistor MPR, reducing transient power consumption. When short-circuited to ground, the gate port voltage (i.e., VP1) of the PMOS transistor MPP may suddenly drop to 0, and the PMOS sampling transistor MPR will directly conduct. Adding PMOS transistor MP3 will limit the path current, further reducing power consumption; 2) When At that time, V N3 ≈VOUT, reducing the channel length modulation effect, making the MPR copy current of the PMOS sampling transistor more accurate.

[0069] The overcurrent limiting current is determined by PMOS transistor MP4, whose gate is connected to a current source circuit. This current source circuit is not shown in this embodiment, but those skilled in the art can design it themselves using existing technology. In this embodiment, the quiescent current of PMOS transistor MP4 in the saturation region is 50μA. NMOS transistors MN4 and MN5 form a current mirror, with their width-to-length ratio (W / L) being... MN4 :(W / L) MN5 = 20:1. Therefore, it can be deduced that the limiting current of the PMOS sampling transistor MPR is 1mA, and the overcurrent limiting current of the PMOS transistor MPP is 144mA (theoretical value). When the pull-up current is small, the sampling current of the PMOS sampling transistor MPR is less than 1mA, the copy current of the NMOS transistor MN5 is <50μA, the PMOS transistor MP4 is in the linear region, and the drain voltage V of the PMOS transistor MP4 is... N5 When the voltage is close to the power supply voltage, PMOS transistor MP5 turns off, having no effect on the circuit. N5 The inverting output voltage VS1 of the common-source transistor MP7 is low. When the pull-up current is large, the sampling PMOS transistor MPR current approaches or exceeds 1mA, the copy current of NMOS transistor MN5 approaches 50uA, and PMOS transistor MP4 transitions from the linear region to the saturation region. N5As the voltage gradually decreases, PMOS transistor MP5 gradually turns on, forcing the voltage of VP1 to rise and limiting the pull-up current. N5 When the inverted output VS1 of the common-source stage MP7 is high, it means that the overcurrent protection is enabled.

[0070] When port VOUT is directly short-circuited to ground, the circuit can no longer function properly. The source current should be limited to a lower level (far below the overcurrent limit of 144mA) to reduce power consumption. Therefore, a source current foldback limiting unit is added to the source current overcurrent protection module to further limit the source current during short circuits to ground. The source current foldback limiting unit includes PMOS transistor MP6, NMOS transistor MN6, and resistor R1. When a short circuit to ground occurs, the source current overcurrent limiting unit is activated first. The PMOS sampling transistor MPR copies a large current, causing the drain voltage V of PMOS transistor MP3 to... N4 The voltage rises. Simultaneously, the VOUT voltage is 0, causing... in This represents the gate-source voltage of NMOS transistor MP6. This represents the threshold voltage of NMOS transistor MP6; when NMOS transistor MN6 is turned on, the voltage difference across resistor R1 increases, and the gate voltage V of PMOS transistor MP6... N6 A voltage drop causes PMOS transistor MP6 to conduct, forcing the gate of PMOS transistor MPP to rise and limiting the pull-up current. At this time, the copy current of the PMOS sampling transistor MPR in the pull-up current overcurrent limiting unit decreases, and the short-circuit limiting current of the pull-up current overcurrent protection module in this embodiment becomes 18mA, far lower than the overcurrent limiting current of 144mA (theoretical value). This means a lower short-circuit current limit, which will further reduce power consumption. Similarly, V N6 When the inverted output VS2 of the common-source stage MP8 is high, it means that the short-circuit protection is enabled.

[0071] like Figure 4 The diagram shows the structural schematic of the sink current overcurrent protection module and the Class AB output stage. The sink current overcurrent protection module mainly includes a sink current overcurrent limiting unit, a sink current foldback limiting unit, and a sink current detection unit. The sink current overcurrent limiting unit contains an NMOS sampling transistor MNR. The NMOS sampling transistor MNR is a proportional copy of the NMOS transistor MNP in the Class AB output stage, (W / L). MNP :(W / L) MNP = 144:1, (W / L) MNP This is the width-to-length ratio (W / L) of the NMOS transistor MNP. MNP This is the width-to-length ratio of the NMOS sampling transistor MNR. The gate of the NMOS sampling transistor MNR is connected to the gate of the NMOS transistor MNP, and the drain of the NMOS sampling transistor MNR is connected to the source of the NMOS transistor MN11.

[0072] A current sinking voltage follower circuit (VOUT) is composed of PMOS transistors MP9, MP10, and MP11, and NMOS transistors MN9, MN10, and MN11, as shown in [link to circuit description]. Figure 4 The dashed box in the diagram. The principle of the sinking current VOUT voltage follower is similar to that of the sourcing current circuit, and will not be elaborated further. When Source voltage of NMOS transistor MN11 when Designed in this embodiment Then V N7 ≈VOUT. Wherein, These represent the threshold voltages of PMOS transistor MP9 and NMOS transistor MN11, respectively. This represents the gate-source voltage of NMOS transistor MN9. This represents the source-gate voltage of the PMOS transistor MP11.

[0073] The overcurrent limiting current is determined by the NMOS transistor MN12, whose gate is connected to a current source circuit. This current source circuit is not shown in this embodiment, but those skilled in the art can design it themselves using existing technology. In this embodiment, the quiescent current of the NMOS transistor MN12 in the saturation region is 60μA. The PMOS transistors MP13 and MP12 form a current mirror, and their width-to-length ratio (W / L) is... MP12 :(W / L) MP13 = 20:1. Therefore, it can be deduced that the overcurrent limiting current of the NMOS sampling transistor MNR is 1.2mA, and the overcurrent limiting current of the NMOS transistor MNP is 173mA (theoretical value). The principle is similar to that of the source current overcurrent limiting principle, and will not be elaborated further. A low level on VS3 indicates that the sink current overcurrent protection is enabled.

[0074] Similarly, the sinking current overcurrent protection module includes a sinking current foldback current limiting unit to further limit the source current to the power supply short circuit. The sinking current foldback current limiting unit includes a PMOS transistor MP14, an NMOS transistor MN14, and a resistor R2. The principle is similar to that of the source current foldback current limiting unit and will not be elaborated further. In this embodiment, the short-circuit limiting current of the sinking current overcurrent protection module becomes 39mA, far lower than the overcurrent limiting current of 173mA (theoretical value). VS4 is low, indicating that the power supply short-circuit protection is enabled.

[0075] like Figure 5 The diagram shown is of the overcurrent / short circuit detection module, which mainly includes two buffers, two inverters, and three OR gates. The relationship between VFLAG and the input is: The meaning is as follows: When VS1 is high, or VS2 is high, or VS3 is low, or VS4 is low, the VFLAG output is high, indicating that there is an overcurrent in the circuit, or that the circuit has a short circuit to the power supply or ground; the user can shut down the circuit by detecting the VFLAG signal.

[0076] This embodiment uses simulation to further and more thoroughly illustrate the embodiment.

[0077] like Figure 6 The diagram shows a simulation setup for a Class AB amplifier with overcurrent protection and detection circuitry. It includes the Class AB amplifier, two matching resistors R4 and R5, a load capacitor C1, and a load resistor R3. Resistors R4 and R5 have the same value, providing unity gain. The load capacitor C1 has a capacitance of 47uF, and the load resistor R3 simulates the resistance of an earphone and can be set to 8Ω, 16Ω, 32Ω, etc.

[0078] Figure 6 The transient simulation results with an 8Ω resistor connected to the load under simulation settings are as follows: Figure 7 As shown. By Figure 7 It can be seen that VOUT output is normal, and peak-to-peak value VPP = 2V. (See diagram I) MPP I is the quiescent current of the PMOS transistor MPP in the Class AB output stage. MNP This represents the quiescent current of the NMOS transistor MNP in the Class AB output stage. Figure 7 The peak pull-in current was 114.8mA and the peak sink current was 115.7mA, both of which did not exceed the overcurrent limit.

[0079] Figure 6 The simulation results of transient overcurrent with a load connected to a 4Ω resistor are as follows: Figure 8 As shown. By Figure 8 It can be seen that the VOUT voltage is significantly distorted, with a peak-to-peak value of VPP = 2V. The source current is limited to 137mA, and the sink current is limited to 164mA. Therefore, the actual circuit's source current overcurrent limit is 137mA, which is not much different from the theoretical analysis value of 144mA; the sink current overcurrent limit is 164mA, which is not much different from the theoretical analysis value of 173mA. Simultaneously, when the source current reaches the overcurrent limit, VS1 is at a high level; when the sink current reaches the overcurrent limit, VS3 is at a low level.

[0080] like Figure 9 The figure shows the transient simulation results of VOUT short-circuiting to ground. Figure 9 It can be seen that VOUT is short-circuited to ground in 100μs-103μs. At this time, the pull-out current changes from the original overcurrent limit of 135mA to 18mA, and the sink current is small. At the same time, VS1 changes from high level to low level, and VS2 changes from low level to high level, which means that the circuit has short-circuited to ground.

[0081] like Figure 10 The figure shows the transient simulation results of VOUT relative to the ground power supply. Figure 10 It can be seen that VOUT is short-circuited to the power supply in 100μs-103μs. At this time, the sink current changes from the original overcurrent limit of 157mA to 39mA, and the pull current is small. At the same time, VS3 changes from low level to high level, and VS4 changes from high level to low level, which means that the circuit has short-circuited to the power supply.

[0082] This invention employs a MOSFET parallel to the power transistor to sense the current. A MOSFET is connected in series with the drain of the MOSFET sampling transistor to prevent excessive current during transient conduction of the sampling MOSFET. Simultaneously, the drain of the MOSFET sampling transistor follows VOUT, reducing channel modulation effects and making the sampling current more accurate. Secondly, a foldback current limiting unit is added to the circuit. When a short circuit to power or ground occurs, this unit further limits the load current. This short-circuit limiting current value is smaller than the overcurrent limiting current value, which also means lower power consumption, providing a safe and stable operating environment for the circuit.

[0083] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An overcurrent protection and detection circuit suitable for Class AB output stages, characterized in that, Includes a sourcing current overcurrent protection module, a sinking current protection module, and an overcurrent / short circuit detection module; The overcurrent protection module is connected to the Class AB output stage and is used to limit the sourcing current of the Class AB output stage and protect the PMOS power transistor of the output stage. The sinking current overcurrent protection module is connected to the AB class output stage and is used to limit the sinking current of the AB class output stage to protect the NMOS power transistor of the output stage. The overcurrent / short circuit detection module is connected to both the pull-in current overcurrent protection module and the sink current overcurrent protection module to generate overcurrent or short circuit signals. The Class AB output stage is used as the last stage of the power amplifier to drive high-current loads; The Class AB output stage includes a PMOS transistor (MPP) and an NMOS transistor (MNP); wherein... The source of the PMOS transistor MPP is connected to the power supply VDD, and the gate and drain are both connected to the source current overcurrent protection module; the source of the NMOS transistor MNP is grounded, and the gate and drain are both connected to the sink current overcurrent protection module. The drain of the PMOS transistor MPP is connected to the drain of the NMOS transistor MNP to form the VOUT output terminal of the AB class output stage. This output terminal VOUT can be connected to an external load capacitor and resistor to drive a large current. The traction current overcurrent protection module includes a traction current overcurrent limiting unit, a traction current foldback current limiting unit, and a traction current detection unit; The pull-up current overcurrent limiting unit is connected to both the VOUT output terminal of the AB class output stage and the gate of the PMOS transistor MPP, and is used for pull-up current monitoring and overcurrent limiting. The current pull-back current limiting unit is connected to both the VOUT output terminal of the AB class output stage and the internal port of the current pull-back overcurrent limiting unit, and is used to limit the current short-circuited to ground at the VOUT output terminal; The current traction detection unit is connected to the internal port of the current traction overcurrent limiting unit and the internal port of the current traction return current limiting unit, and is used to amplify the overcurrent detection and short-circuit to ground detection signals in reverse. The spooling current overcurrent protection module uses VS1 for spooling current overcurrent detection and VS2 for short circuit to ground detection. A high level signal VS1 indicates overcurrent, and a high level signal VS2 indicates short circuit. The sink current overcurrent protection module includes a sink current overcurrent limiting unit, a sink current foldback current limiting unit, and a sink current detection unit. The sink current overcurrent limiting unit is connected to both the VOUT output terminal of the AB class output stage and the gate of the NMOS transistor MNP, and is used for sink current monitoring and overcurrent limiting. The sinking current foldback current limiting unit is connected to both the VOUT output terminal of the AB class output stage and the internal port of the sinking current overcurrent limiting unit, and is used to limit the current from the VOUT output terminal to the power supply when short-circuited. The sinking current detection unit is connected to the internal port of the sinking current overcurrent limiting unit and the internal port of the sinking current foldback current limiting unit, and is used to amplify the overcurrent detection and short circuit to power supply detection signals in reverse. The sinking current overcurrent protection module has a sinking current overcurrent detection signal of VS3 and a short circuit to power supply detection signal of VS4; a low level of signal VS3 indicates a short circuit, and a low level of signal VS4 indicates a short circuit.

2. The overcurrent protection and detection circuit for Class AB output stages as described in claim 1, characterized in that, The overcurrent limiting unit includes NMOS transistors MN1~MN5, PMOS transistors MP1~MP5, and a PMOS sampling transistor MPR; The gate of NMOS transistor MN1 is connected to the VOUT output terminal, and its source is connected to the source of PMOS transistor MP1. The gate and drain of PMOS transistor MP1 are connected to the source of NMOS transistor MN2. The drain of PMOS transistor MP2 is connected to both the drain and gate of NMOS transistor MN2, and the source of NMOS transistor MN2 is connected to the drain of NMOS transistor MN3. The gate of the PMOS sampling transistor MPR is connected to the gate of the PMOS transistor MPP, and the drain is connected to the source of the PMOS transistor MP3. The gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2, and the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN4. The drain of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5 and the drain of NMOS transistor MN5. The gate of NMOS transistor MN5 is connected to the gate and drain of NMOS transistor MN4. The drain of PMOS transistor MP5 is connected to the gate of PMOS transistor MPP. The drain of NMOS transistor MN1, the source of PMOS transistor MP2, the source of PMOS sampling transistor MPR, the source of PMOS transistor MP4, and the source of PMOS transistor MP5 are all connected to the power supply VDD; the sources of NMOS transistors MN3 to MN5 are all grounded.

3. The overcurrent protection and detection circuit for AB class output stages as described in claim 2, characterized in that, The current pull-back current limiting unit includes a PMOS transistor MP6, an NMOS transistor MN6, and a resistor R1. The source of the PMOS transistor MP6 and the first terminal of the resistor R1 are both connected to the power supply VDD. The drain of the PMOS transistor MP6 is connected to the gate of the PMOS transistor MPP. The gate is connected to both the second terminal of the resistor R1 and the drain of the NMOS transistor MN6. The gate of the NMOS transistor MN6 is connected to the drain of the PMOS transistor MP3. The source of the NMOS transistor MN6 is connected to the VOUT output terminal.

4. The overcurrent protection and detection circuit for Class AB output stages as described in claim 3, characterized in that, The current retrieval detection unit includes NMOS transistors MN7 and MN8, and PMOS transistors MP7 and MP8; the sources of PMOS transistors MP7 and MP8 are both connected to the power supply VDD, and the sources of NMOS transistors MN7 and MN8 are both grounded. The gate of PMOS transistor MP7 is connected to the drain of NMOS transistor MN5, and the drain is connected to signal VS1; the gate of PMOS transistor MP8 is connected to the drain of NMOS transistor MN6, and the drain is connected to signal VS2. The gate and drain of NMOS transistor MN7 are both connected to signal VS1; the gate and drain of NMOS transistor MN8 are both connected to signal VS2.

5. The overcurrent protection and detection circuit for Class AB output stages as described in claim 4, characterized in that, The overcurrent limiting unit includes NMOS transistors MN9~MN13, PMOS transistors MP9~MP13, and an NMOS sampling transistor MNR; The drain of PMOS transistor MP10 is simultaneously connected to the source of PMOS transistor MP11, the drain and gate of NMOS transistor MN9, and the gate and drain of PMOS transistor MP11 are simultaneously connected to the drain of NMOS transistor MN10. The source of NMOS transistor MN9 is connected to the source of PMOS transistor MP9, and the gate of PMOS transistor MP9 is connected to the OUT output terminal. The gate of PMOS transistor MP13 is connected to both the gate and drain of PMOS transistor MP12. The drain of PMOS transistor MP13 is connected to both the gate of NMOS transistor MN13 and the drain of NMOS transistor MN12. The drain of NMOS transistor MN13 is connected to the gate of NMOS transistor MNP. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN11, the gate of NMOS transistor MN11 is connected to the drain of NMOS transistor MN10, the source of NMOS transistor MN11 is connected to the drain of NMOS sampling transistor MNR, and the gate of NMOS sampling transistor MNR is connected to the gate of NMOS transistor MNP. The drain of PMOS transistor MP9, the source of PMOS transistor MP10, the source of NMOS sampling transistor MNR, the source of NMOS transistor MN12, and the source of NMOS transistor MN13 are all grounded; the source of PMOS transistor MP10, the source of PMOS transistor MP12, and the source of PMOS transistor MP13 are all connected to the power supply VDD.

6. The overcurrent protection and detection circuit for AB class output stages as described in claim 5, characterized in that, The current sinking and foldback limiting unit includes a PMOS transistor MP14, an NMOS transistor MN14, and a resistor R2. The source of the PMOS transistor MP14 is connected to the OUT output terminal, and its gate is connected to the drain of the NMOS transistor MN11. The drain is connected to both the first end of the resistor R2 and the gate of the NMOS transistor MN14. The second end of the resistor R2 is grounded. The drain of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MNP, and its source is grounded.

7. The overcurrent protection and detection circuit for AB class output stages as described in claim 6, characterized in that, The current sinking detection unit includes PMOS transistors MP15 and MP16, and NMOS transistors MN15 and MN16; the sources of PMOS transistors MP15 and MP16 are both connected to the power supply VDD, and the sources of NMOS transistors MN15 and MN16 are both grounded. The gate and drain of PMOS transistor MP15 are both connected to signal VS3, and the gate and drain of PMOS transistor MP16 are both connected to signal VS4. The drain of NMOS transistor MN15 is connected to signal VS3, and its gate is connected to the drain of PMOS transistor MP13; the drain of NMOS transistor MN16 is connected to signal VS4, and its gate is connected to the drain of PMOS transistor MP14.

8. The overcurrent protection and detection circuit for Class AB output stages as described in claim 7, characterized in that, The overcurrent / short-circuit detection module includes two buffers, two inverters, and three OR gates; wherein... The inputs of the two buffers are signals VS1 and VS2 from the current sourcing overcurrent protection module, respectively, and the outputs of the two buffers are the inputs of an OR gate. The inputs of the two inverters are signals VS3 and VS4 from the current sourcing overcurrent protection module, respectively, and the outputs of the two inverters are the inputs of another OR gate. The outputs of these two OR gates are the inputs of a third OR gate, and the relationship between the output signal VFLAG of the third OR gate and its inputs is as follows: When VS1 is high, VS2 is high, VS3 is low, or VS4 is low, the VFLAG signal is high, indicating that there is an overcurrent in the circuit, or that the circuit has a short circuit to the power supply or ground; the user can shut down the circuit by detecting the VFLAG signal.

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