A dynamic comparator and a method for offset calibration thereof

Abstract

This invention relates to a dynamic comparator and its offset calibration method. The dynamic comparator includes: a control module that generates a comparison clock signal and a calibration control signal; a voltage comparison module that compares the magnitude of an input voltage based on the comparison clock signal and outputs a voltage comparison result, wherein the input circuit of the voltage comparison module includes a first input transistor and a second input transistor, the gate of the first input transistor being connected to a first input voltage, and the gate of the second input transistor being connected to a second input voltage; and an offset calibration module that adjusts the substrate bias voltage of the first and second input transistors based on the comparison clock signal and the calibration control signal to compensate for the input offset voltage. This invention enables offset voltage calibration with a small area and low power consumption, improving the accuracy of the dynamic voltage comparator.

Description

Technical Field

[0001] This invention relates to the field of dynamic comparator technology, and in particular to a dynamic comparator and its offset calibration method. Background Technology

[0002] Signals such as temperature, humidity, sound, and pressure that exist in nature are all analog signals, while integrated circuits process mostly digital signals. Since ADCs can convert continuous analog signals into discrete digital signals, analog-to-digital converters (ADCs) are indispensable as a bridge between analog and digital signals.

[0003] SAR ADCs are gaining increasing attention due to their low power consumption and suitability for advanced manufacturing processes. However, comparator misalignment can lead to reduced ADC accuracy during design, making comparator calibration crucial.

[0004] Traditional comparator offset calibration techniques often employ input offset voltage storage or output voltage storage, storing the voltage by adding a large storage capacitor to the signal transmission path. This method is unsuitable for high-speed, high-precision ADCs. Another approach involves adding an auxiliary input transistor and adjusting its gate voltage to compensate for the input transistor's offset. However, this method, due to the addition of an extra input transistor, results in significant input noise, negatively impacting ADC performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a dynamic comparator and its offset calibration method, which can achieve offset voltage calibration with small area and low power consumption.

[0006] The technical solution adopted by this invention to solve its technical problem is: to provide a dynamic comparator, comprising:

[0007] The control module generates a comparison clock signal and a calibration control signal;

[0008] The voltage comparison module compares the magnitude of the input voltage based on the comparison clock signal and outputs the voltage comparison result. When the first input voltage is higher than the second input voltage, the first output port outputs a high level and the second output port outputs a low level. When the first input voltage is lower than the second input voltage, the first output port outputs a low level and the second output port outputs a high level. The input circuit of the voltage comparison module includes a first input transistor and a second input transistor. The gate of the first input transistor is connected to the first input voltage, and the gate of the second input transistor is connected to the second input voltage.

[0009] The offset calibration module adjusts the substrate bias voltage of the first and second input transistors based on the comparison clock signal and the calibration control signal, thereby compensating for the input offset voltage.

[0010] Furthermore, the offset calibration module includes:

[0011] The first calibration module adjusts the substrate bias voltage of the first input transistor based on the comparison clock signal and the calibration control signal. The input port of the first calibration module is connected to the second output port of the comparison module, and the output port of the first calibration module is connected to the substrate of the separately led-out first input transistor.

[0012] The second calibration module adjusts the substrate bias voltage of the second input transistor based on the comparison clock signal and the calibration control signal. The input port of the second calibration module is connected to the first output port of the comparison module, and the output port of the second calibration module is connected to the substrate of the separately led-out second input transistor.

[0013] Furthermore, the first calibration module includes a first calibration switch, one end of which is connected to the second output port of the comparison module, and the other end of which is connected to one end of a second calibration switch. The other end of the second calibration switch is simultaneously connected to one end of a first calibration capacitor and one end of a third calibration switch. The other end of the first calibration capacitor is grounded. The other end of the third calibration switch is simultaneously connected to one end of the second calibration capacitor and the substrate of the first input transistor. The other end of the second calibration capacitor is grounded. The second calibration module includes a fourth calibration switch, one end of which is connected to the first output port of the comparison module, and the other end of which is connected to one end of a fifth calibration switch. The other end of the fifth calibration switch is simultaneously connected to one end of a third calibration capacitor and one end of a sixth calibration switch. The other end of the third calibration capacitor is grounded. The other end of the sixth calibration switch is simultaneously connected to one end of the fourth calibration capacitor and the substrate of the second input transistor. The other end of the fourth calibration capacitor is grounded.

[0014] Furthermore, the calibration control signal includes a first control signal and a second control signal. The first calibration switch and the fourth calibration switch are controlled by the first control signal, the second calibration switch and the fifth calibration switch are controlled by a comparison clock signal, and the third calibration switch and the sixth calibration switch are controlled by the second control signal.

[0015] Furthermore, the first and second input transistors are manufactured using a deep N-well process.

[0016] The technical solution adopted by this invention to solve its technical problem is: to provide an offset calibration method for any of the dynamic comparators described above, characterized in that it includes:

[0017] Offset detection stage: Short-circuit the first input port and the second input port of the voltage comparison module, and set the voltage of the first calibration capacitor and the third calibration capacitor to a high level or a low level according to the output result of the voltage comparison module;

[0018] Offset calibration stage: Charge sharing is established between the first calibration capacitor and the second calibration capacitor, and charge sharing is also established between the third calibration capacitor and the fourth calibration capacitor. The substrate bias voltage of the first input transistor and the second input transistor is adjusted by adjusting the voltage of the second calibration capacitor and the fourth calibration capacitor, thereby compensating for the input offset voltage.

[0019] Furthermore, during the offset detection phase, the first control signal controls the first calibration switch and the fourth calibration switch to close, the comparison clock signal controls the second calibration switch and the fifth calibration switch to close, and the second control signal controls the third calibration switch and the sixth calibration switch to open.

[0020] Furthermore, during the misalignment calibration phase, the first control signal controls the first calibration switch and the fourth calibration switch to open, and the second control signal controls the third calibration switch and the sixth calibration switch to close.

[0021] Furthermore, when the dynamic comparator is applied to a successive approximation analog-to-digital converter, it further includes the following steps before the offset detection stage:

[0022] The first control signal is set to be the signal generated by shifting the last shift signal required by the voltage comparison module in the successive approximation analog-to-digital converter to complete the normal comparison once more.

[0023] The second control signal is set as the sampling enable signal of the successive approximation analog-to-digital converter, which is a signal that triggers the successive approximation analog-to-digital converter to perform a sampling operation.

[0024] Beneficial effects

[0025] By employing the above-mentioned technical solution, this invention has the following advantages and positive effects compared with the prior art: This invention utilizes a comparator to detect the offset voltage, and uses the high and low levels output from the output terminal to charge and discharge the capacitor in the calibration module, thereby adjusting the substrate bias voltage of the corresponding input transistor, and further adjusting the threshold voltage of the input transistor to compensate for the offset voltage. This invention does not require the addition of large capacitors and auxiliary input transistors, nor does it require a large amount of memory and control lines. It not only effectively reduces the offset of the dynamic preamplifier and improves the conversion accuracy of the comparator, but also has the advantages of small area and low power consumption, making it particularly suitable for successive approximation analog-to-digital converters. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the first embodiment of the present invention;

[0027] Figure 2 This is a circuit diagram of the first embodiment of the present invention;

[0028] Figure 3 This is a timing diagram of the first embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the substrate bias voltage change of the input tube in the first embodiment of the present invention. Detailed Implementation

[0030] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0031] The first embodiment of the present invention relates to a dynamic comparator, such as... Figure 1 As shown, it includes:

[0032] Control module: Generates comparison clock signal clkc and calibration control signals s_cal and clks.

[0033] Voltage Comparison Module: This module compares the input voltages based on a comparison clock signal and outputs the comparison result. When the first input voltage is higher than the second input voltage, the first output port Vop outputs a high level, and the second output port Von outputs a low level. When the first input voltage is lower than the second input voltage, the first output port Vop outputs a low level, and the second output port Von outputs a high level. The input circuit of the voltage comparison module includes a first input transistor M1 and a second input transistor M2, both using deep N-well technology. The gate of the first input transistor M1 is connected to the first input voltage, and the gate of the second input transistor M2 is connected to the second input voltage.

[0034] Offset calibration module: Based on the comparison clock signal clkc and calibration control signals s_cal and clks, the substrate bias voltage of the first input transistor M1 and the second input transistor M2 is adjusted to compensate for the input offset voltage. Specifically, it includes:

[0035] A first calibration module used to adjust the substrate bias voltage of the first input transistor M1 has its input port connected to the second output port of the comparison module, and its output port connected to the substrate of the separately led-out first input transistor M1.

[0036] The second calibration module, used to adjust the substrate bias voltage of the second input transistor M2, has its input port connected to the first output port of the comparison module, and its output port connected to the substrate of the separately led-out second input transistor M2.

[0037] More specifically, such as Figure 2 As shown, the first calibration module includes a first calibration switch S1. One end of the first calibration switch S1 is connected to the second output port Von of the comparison module, and the other end is connected to one end of a second calibration switch S2. The other end of the second calibration switch S2 is simultaneously connected to the first calibration capacitor C. LSB1 One end of the first calibration capacitor C is connected to one end of the third calibration switch S3. LSB1 The other end is grounded, and the other end of the third calibration switch S3 is simultaneously connected to the second calibration capacitor C. CAL1 One end of the first input transistor M1 is connected to the substrate, and the second calibration capacitor C is connected to the substrate. CAL1 The other end is grounded.

[0038] The second calibration module includes a fourth calibration switch S4. One end of the fourth calibration switch S4 is connected to the first output port Vop of the comparison module, and the other end is connected to one end of a fifth calibration switch S5. The other end of the fifth calibration switch S5 is simultaneously connected to the third calibration capacitor C. LSB2 One end of the third calibration capacitor C is connected to one end of the sixth calibration switch S6. LSB2 The other end is grounded, and the other end of the sixth calibration switch S6 is simultaneously connected to the fourth calibration capacitor C. CAL2 One end of the second input transistor M2 is connected to the substrate, and the fourth calibration capacitor C is connected to the substrate. CAL2 The other end is grounded.

[0039] Specifically, the first calibration switch S1 and the fourth calibration switch S4 are controlled by the first control signal s_cal, the second calibration switch S2 and the fifth calibration switch S5 are controlled by the comparison clock signal clkc, and the third calibration switch S3 and the sixth calibration switch S6 are controlled by the second control signal clks.

[0040] The offset calibration principle will be explained below through the application of this embodiment in a successive approximation analog-to-digital converter (SAR DAC).

[0041] Ideally, a comparator has no offset voltage, and its output depends only on the magnitude of the input signal. However, when an offset voltage exists, the comparator will produce an erroneous output within a certain range. Assume... Figure 2 The comparator in the code has an offset voltage of 10mV. Therefore, the output of the comparison will be incorrect in the range of 0mV > Vip - Vin > -10mV.

[0042] The timing of the calibration work is as follows Figure 3 As shown, clks is the sampling enable signal, clkc is the comparator's comparison clock signal, and s_cal is the calibration enable signal. s_cal can be generated by a shift register, adding one bit after generating the shift signal required for normal SAR ADC comparison, for calibration. That is, this calibration circuit adds a comparison cycle for calibration after the comparator completes normal comparison. After the SAR ADC completes all comparisons, the difference between the comparator's input signals is within 1 LSB. Next, the comparator's inputs are shorted to detect the offset voltage value. The comparator's output reflects the polarity of the offset voltage; for example, when the offset voltage is positive, Vop outputs 1, and vice versa.

[0043] By controlling the calibration switches, the first input port Vip of the voltage comparator module is shorted to the second input port Vin. The first control signal s_cal controls the first calibration switch S1 and the fourth calibration switch S4 to close, the comparison clock signal clkc controls the second calibration switch S2 and the fifth calibration switch S5 to close, and the second control signal clks controls the third calibration switch S3 and the sixth calibration switch S6 to open. At this time, the comparator output will charge the first calibration capacitor C. LSB1 Third calibration capacitor C LSB2 The voltage on the top plate is set to either high or low.

[0044] Then, the first control signal s_cal controls the first calibration switch S1 and the fourth calibration switch S4 to open, and the second control signal clks controls the third calibration switch S3 and the sixth calibration switch S6 to close. At this time, the first calibration capacitor C LSB1 With the second calibration capacitor C CAL1 Charge sharing occurs between them, and the third calibration capacitor C LSB2 With the fourth calibration capacitor C CAL2 Charge sharing occurs between them. This allows adjustment of the substrate bias voltage V of the two input transistors of the comparator. fb1 V fb2 This allows for the adjustment of the threshold voltages of the two input transistors to compensate for the offset voltage.

[0045] The second embodiment of the present invention relates to an offset calibration method for a dynamic comparator, comprising:

[0046] Disorder detection phase:

[0047] The first input port Vip of the voltage comparator module is shorted to the second input port Vin. The first control signal s_cal controls the first calibration switch S1 and the fourth calibration switch S4 to close, the comparison clock signal clkc controls the second calibration switch S2 and the fifth calibration switch S5 to close, and the second control signal clks controls the third calibration switch S3 and the sixth calibration switch S6 to open. At this time, the offset calibration module adjusts the first calibration capacitor C according to the output result of the voltage comparator module. LSB1 and the third calibration capacitor C LSB2 Charging or discharging is performed. At this time, when the offset voltage is positive, Vop outputs a high level, depressing the third calibration capacitor C. LSB2 The top plate voltage is set to high level, Von output is low level, and the first calibration capacitor C is set to high level. LSB1 The top plate voltage is set to low; conversely, when the offset voltage is negative, Vop outputs a low level, and the third calibration capacitor C... LSB2 The top plate voltage is set to low, Von outputs a high level, and the first calibration capacitor C is activated. LSB1 The voltage on the top plate is set to high level.

[0048] Offset calibration phase:

[0049] The first control signal s_cal controls the first calibration switch S1 to open, and the second control signal clks controls the third calibration switch S3 to close, causing the first calibration capacitor C to... LSB1 With the second calibration capacitor C CAL1 Charge sharing occurs between them, by adjusting the second calibration capacitor C. CAL1 The top plate voltage is used to adjust the substrate bias voltage of the first input transistor M1, thereby compensating for the input offset voltage.

[0050] The first control signal s_cal controls the fourth calibration switch S4 to open, and the second control signal clks controls the sixth calibration switch S6 to close, causing the third calibration capacitor C to... LSB2 With the fourth calibration capacitor C CAL2 Charge sharing occurs between them, by adjusting the fourth calibration capacitor C. CAL2 The top plate voltage is used to adjust the substrate bias voltage of the second input transistor M2, thereby compensating for the input offset voltage.

[0051] When this dynamic comparator is applied to a successive approximation analog-to-digital converter, the first control signal s_cal is set to the signal generated by shifting the last shift signal required for the analog-to-digital converter to complete a normal comparison.

[0052] The second control signal clks is set as the sampling enable signal of the analog-to-digital converter, which is the signal that triggers the analog-to-digital converter to perform a sampling operation.

[0053] The following description further elaborates on this embodiment by applying it to a successive approximation analog-to-digital converter (SAR DAC).

[0054] Ideally, a comparator has no offset voltage, and its output depends only on the magnitude of the input signal. However, when an offset voltage exists, the comparator will produce an erroneous output within a certain range. Assume... Figure 2 The comparator in the code has an offset voltage of 10mV. Therefore, the output of the comparison will be incorrect in the range of 0mV > Vip - Vin > -10mV.

[0055] The timing of the calibration work is as follows Figure 3 As shown, clks is the sampling enable signal, clkc is the comparator's comparison clock signal, and s_cal is the calibration enable signal. s_cal can be generated by a shift register, adding one bit after generating the shift signal required for normal SAR ADC comparison, for calibration. That is, this calibration circuit adds a comparison cycle for calibration after the comparator completes normal comparison. After the SAR ADC completes all comparisons, the difference between the comparator's input signals is within 1 LSB. Next, the comparator's inputs are shorted to detect the offset voltage value. The comparator's output reflects the polarity of the offset voltage; for example, when the offset voltage is positive, Vop outputs 1, and vice versa.

[0056] The following describes the specific process for calibrating the offset voltage:

[0057] If the offset voltage is positive. For example... Figure 2 As shown, the ADC first performs normal quantization. After the last bit is quantized, the comparator offset voltage is detected. s_cal is set high, switches S1 and S4 are closed, shorting the differential input of the comparator, and then the comparator performs the comparison. When clkc is high, switches S2 and S5 are closed. At this time, the comparator outputs Vop as 1 and Von as 0.

[0058] For the second calibration module on the right side of the comparator, the comparator output will be relative to C. LSB2 During charging, the voltage at the top plate becomes VDD. Then the ADC performs the next stage of sampling; when clks is high, switch S6 is closed, and capacitor C... LSB2 With C CAL2 Charge sharing occurs, and after sharing is complete, V fb2 The values ​​are as follows

[0059]

[0060] Among them, V fb2[n] represents C during the nth calibration cycle. CAL2 Top plate voltage, C LSB2 C CAL2 These represent the capacitor C. LSB2 With C CAL2 The capacitance value. It can be seen that V fb2 The value will increase during the calibration process, and the increased value is related to C. LSB2 and C CAL2 It is related to the capacitance ratio.

[0061] For the first calibration module on the left side of the comparator, the comparator output will be C LSB1 The voltage at the top plate becomes VSS. Then the ADC performs the next stage of sampling; clks is high, switch S3 is closed, and capacitor C... LSB1 With C CAL1 Charge sharing occurs, and after sharing is complete, V fb1 The values ​​are as follows

[0062]

[0063] As can be seen, since the voltage on CLSB1 is 0, after charge sharing, V fb1 The voltage value remains unchanged and stays at 0.

[0064] It is also known that, due to the substrate bias effect, the threshold voltage of the MOSFET changes as follows:

[0065]

[0066] Among them, V TH V represents the threshold voltage of the MOSFET. TH0 Represents zero bias voltage, V SB Φ represents the voltage between the source and substrate of a MOSFET. F γ represents the Fermi potential of a metal-oxide-semiconductor junction, and γ represents the modulation coefficient.

[0067] When V fb2 The voltage gradually increases, and the threshold voltage V of M2... TH As the voltage is gradually decreased, the driving capability of transistor M2 becomes stronger, while the driving capability of transistor M1 remains unchanged. This can offset part of the offset voltage value. During the continuous calibration process, V... fb2 Gradually increase until V TH The changes offset all the effects of the offset voltage.

[0068] When the offset voltage becomes 0, the next calibration will still have a comparator output of 1, and V will be charged after the charge sharing. fb2 As the voltage increases, the offset voltage will change from positive to negative. During the next calibration process, the comparator output will become 0. LSB2The voltage is VSS, and after charge sharing, V fb2 Become

[0069]

[0070] V can be seen fb2 It will decrease, and the comparator output will become 1 again on the next calibration. After that, V fb2 It will fluctuate around this value until the calibration stabilizes. Throughout the calibration process, V... fb2 The trend of change is as follows Figure 4 As shown.

[0071] In summary, this invention utilizes a comparator to detect offset voltage and adjusts the top-plate voltage of the capacitor in the calibration circuit by using the high and low levels output at the output terminal. This, in turn, adjusts the threshold voltage of the input transistor to compensate for the offset voltage. This invention eliminates the need for large capacitors and auxiliary input transistors, as well as a large amount of memory and control lines. It not only effectively reduces the offset of the dynamic preamplifier and improves the conversion accuracy of the comparator, but also has the advantages of low area and low power consumption, making it particularly suitable for successive approximation analog-to-digital converters.

Claims

1. A dynamic comparator, characterized in that, include: The control module generates a comparison clock signal and a calibration control signal; A voltage comparison module compares the magnitude of the input voltage based on the comparison clock signal and outputs the voltage comparison result. When the first input voltage is higher than the second input voltage, the first output port outputs a high level and the second output port outputs a low level. When the first input voltage is lower than the second input voltage, the first output port outputs a low level and the second output port outputs a high level. The input circuit of the voltage comparison module includes a first input transistor and a second input transistor. The gate of the first input transistor is connected to the first input voltage, and the gate of the second input transistor is connected to the second input voltage. An offset calibration module adjusts the substrate bias voltage of the first input transistor and the second input transistor based on the comparison clock signal, the calibration control signal, and the voltage comparison result, thereby compensating for the input offset voltage. The offset calibration module includes: The first calibration module adjusts the substrate bias voltage of the first input transistor based on the comparison clock signal and the calibration control signal. The input port of the first calibration module is connected to the second output port of the comparison module, and the output port of the first calibration module is connected to the substrate of the separately led-out first input transistor. The second calibration module adjusts the substrate bias voltage of the second input transistor based on the comparison clock signal and the calibration control signal. The input port of the second calibration module is connected to the first output port of the comparison module, and the output port of the second calibration module is connected to the substrate of the separately led-out second input transistor. The first calibration module includes a first calibration switch, one end of which is connected to the second output port of the comparison module, and the other end of which is connected to one end of a second calibration switch. The other end of the second calibration switch is simultaneously connected to one end of a first calibration capacitor and one end of a third calibration switch. The other end of the first calibration capacitor is grounded. The other end of the third calibration switch is simultaneously connected to one end of the second calibration capacitor and the substrate of the first input transistor. The other end of the second calibration capacitor is grounded. The second calibration module includes a fourth calibration switch, one end of which is connected to the first output port of the comparison module, and the other end of which is connected to one end of a fifth calibration switch. The other end of the fifth calibration switch is simultaneously connected to one end of a third calibration capacitor and one end of a sixth calibration switch. The other end of the third calibration capacitor is grounded. The other end of the sixth calibration switch is simultaneously connected to one end of the fourth calibration capacitor and the substrate of the second input transistor. The other end of the fourth calibration capacitor is grounded.

2. The dynamic comparator according to claim 1, characterized in that, The calibration control signal includes a first control signal and a second control signal. The first calibration switch and the fourth calibration switch are controlled by the first control signal, the second calibration switch and the fifth calibration switch are controlled by a comparison clock signal, and the third calibration switch and the sixth calibration switch are controlled by the second control signal.

3. The dynamic comparator according to claim 1, characterized in that, The first and second input transistors are manufactured using a deep N-well process.

4. A dynamic comparator offset calibration method as described in any one of claims 1 to 3, characterized in that, include: Offset detection stage: Short-circuit the first input port and the second input port of the voltage comparison module, and set the voltage of the first calibration capacitor and the third calibration capacitor to a high level or a low level according to the output result of the voltage comparison module; Offset calibration stage: Charge sharing is established between the first calibration capacitor and the second calibration capacitor, and charge sharing is also established between the third calibration capacitor and the fourth calibration capacitor. The substrate bias voltage of the first input transistor and the second input transistor is adjusted by adjusting the voltage of the second calibration capacitor and the fourth calibration capacitor, thereby compensating for the input offset voltage.

5. The dynamic comparator offset calibration method according to claim 4, characterized in that, During the offset detection phase, the first control signal controls the first and fourth calibration switches to close, the comparison clock signal controls the second and fifth calibration switches to close, and the second control signal controls the third and sixth calibration switches to open.

6. The dynamic comparator offset calibration method according to claim 5, characterized in that, During the offset calibration phase, the first control signal controls the first calibration switch and the fourth calibration switch to open, and the second control signal controls the third calibration switch and the sixth calibration switch to close.

7. The dynamic comparator offset calibration method according to claim 6, characterized in that, When the dynamic comparator is applied to a successive approximation analog-to-digital converter, prior to the offset detection stage, it further includes: The first control signal is set to be the signal generated by shifting the last shift signal required by the voltage comparison module in the successive approximation analog-to-digital converter to complete the normal comparison once more. The second control signal is set as the sampling enable signal of the successive approximation analog-to-digital converter, which is a signal that triggers the successive approximation analog-to-digital converter to perform a sampling operation.

Images