A stable and reliable low-resource serial capture device and method

Abstract

The application discloses a stable and reliable low-resource-occupying serial capturing device and method, and belongs to the field of millimeter wave communication and signal processing. The existing single carrier modulation demodulation system capturing method cannot meet the requirements of high-speed information transmission, low resource occupation and reliable data capturing. According to the influence of actual clock signal uncertainty and clock jitter on sampling data, one frame of complete sampling data of the receiving end is stored by overlapping storage design, the hardware logic resource occupation is reduced, the sampling sample deviation caused by the jitter of the actual hardware clock source is avoided, and the complete data used for correlation processing is effectively reserved. In order to avoid the false correlation peak caused by oversampling of the signal and misjudgment, the method of obtaining the maximum value of the correlation peak and secondary capturing judgment is adopted, the accurate real-time capturing of the synchronization header in the single carrier modulation demodulation system and the effective information output are realized under the condition of low RAM resource occupation rate and high-speed information transmission.

Description

Technical Field

[0001] This invention relates to the fields of millimeter-wave communication and signal processing, specifically to a stable and reliable low-resource-consumption serial acquisition device and method, which can be used at the receiving end of a communication system to perform coarse synchronization of sampled signals, and is a prerequisite for establishing communication between cooperating parties. Background Technology

[0002] The purpose of data acquisition is to find the synchronization header of the sampled data, determine the start position of each data frame, and achieve coarse synchronization of the signal. This is the first step in establishing communication between cooperating parties. Acquisition can search for the arrival time of a data frame. Common acquisition methods generally locate the synchronization header in a data frame by performing correlation operations between the received data and the local synchronization sequence in the time dimension. The acquisition module is generally the first module of the communication receiver and needs to have high-speed and stable performance. However, due to problems such as clock jitter and spurious correlation peaks caused by signal oversampling, the acquisition methods of existing single-carrier modulation and demodulation systems cannot meet the requirements of high-speed information transmission, low resource consumption, and reliable data acquisition.

[0003] In hardware system design, the requirements for clock signals are extremely stringent, serving as a reference for signal timing. However, in reality, the output period of a clock source is theoretically not a fixed value but varies over time. This uncertainty can lead to clock jitter and other problems in actual communication, affecting the sampled data. Furthermore, input data typically needs to be buffered before capture-related processing. Hardware storage resources are limited; when a data frame is designed to be too long, it will consume a significant amount of RAM, resulting in insufficient available hardware logic resources. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned problems and propose a stable and reliable serial acquisition device and method with low resource consumption. By using an overlapping storage design to buffer the received end sampling data, and by using the calculation of the correlation peak maximum and a secondary acquisition decision, the real-time acquisition and effective information output of the synchronization head in a single-carrier modulation and demodulation system can be achieved under conditions of low RAM resource consumption and high-speed information transmission.

[0005] The technical solution adopted in this invention is as follows:

[0006] A stable and reliable low-resource-consumption serial capture device includes a data buffer module, a capture processing module, a comparison and decision module, a counting module, a flag register module, and a state switching module, wherein:

[0007] The data caching module is used to cache the sampled multi-channel parallel input data in the slow acquisition phase using overlapping caching; in the fast acquisition phase, it starts caching N numbers before the synchronization header arrives, where N is related to the number of parallel channels.

[0008] The capture processing module is used to read data from the data buffer module during the slow capture phase and use serial sliding correlation to obtain the correlation value between the sampled data frame and the local synchronization sequence; during the fast capture phase, it reads data from the data buffer module, correlates it with the local synchronization sequence, and performs FFT transformation to obtain MN FFT transformation results; where M is a set value.

[0009] The comparison and decision module is used in the slow acquisition phase to compare the correlation value calculated by sliding correlation with the acquisition threshold T, and take the maximum correlation value greater than the threshold as the captured correlation peak value to initially locate the synchronization head; in the fast acquisition phase, it finds the maximum value in the FFT transform result, finds the starting position of the synchronization head corresponding to the maximum value through the correspondence of discrete Fourier transform, and confirms whether the synchronization head address obtained in the slow acquisition phase is accurate.

[0010] The counter module is mainly used to cyclically count the sampling points cached in the data cache module;

[0011] The flag register module is used to store various flag variables of the comparison and decision module;

[0012] The state switching module is used to control the state switching of the capture system and the processing flow of each module according to the various flag variables stored in the flag register module, and to control the data buffer module to output the required data according to the synchronization header address; the entire capture system state includes empty state, slow capture state, fast capture state and data output state.

[0013] Furthermore, the specific method of overlapping caching in the data caching module is as follows:

[0014] Set the data buffer length RAM_LENGTH, buffer a segment of length RAM_LENGTH in a data frame, and mark the sample point number of the buffer segment in the data frame. Record the starting data sample point number as A and the ending data sample point number as B. When buffering the next segment, when the sample point number in the data frame is (A+B) / 2, data buffering is performed, and the buffer length is RAM_LENGTH.

[0015] A stable and reliable low-resource-consumption serial capture method includes the following steps:

[0016] Step 1: During the slow acquisition phase, the multi-channel parallel data sampled by the ADC is buffered using an overlapping buffer method.

[0017] Step 2: During the slow capture phase, data is read sequentially from the cache, and the relevant values ​​are calculated using a sliding correlation calculation method.

[0018] Step 3: Determine if the correlation value is greater than the capture threshold. Take the maximum correlation value that is greater than the threshold as the captured correlation peak value to initially locate the synchronization head.

[0019] Step 4: Enter the fast acquisition phase. N numbers are buffered before the synchronization head arrives, for a total of MN sampling points. The buffered data is correlated with the local sequence and subjected to FFT transformation to obtain MN FFT transformation results. The maximum value among the FFT transformation results is found, and the synchronization head start position corresponding to the maximum value is found through the correspondence of discrete Fourier transform. Here, M is a set value, and N is related to the number of parallel paths.

[0020] Step 5: Based on the synchronization header start position obtained in the fast acquisition phase, confirm whether the synchronization header address obtained in the slow acquisition phase is accurate. If the address is correct, it is considered that the synchronization header of the data frame has been accurately located; otherwise, return to step 4.

[0021] Furthermore, in step 1, the specific method of overlapping caching is as follows:

[0022] Set the data buffer length RAM_LENGTH, buffer a segment of length RAM_LENGTH in a data frame, and mark the sample point number of the buffer segment in the data frame. Record the starting data sample point number as A and the ending data sample point number as B. When buffering the next segment, when the sample point number in the data frame is (A+B) / 2, data buffering is performed, and the buffer length is RAM_LENGTH.

[0023] Furthermore, step 3 is implemented as follows:

[0024] When the correlation value C is greater than the threshold T, the correlation peak is initially found, and the correlation value C is stored in the register. In the next clock cycle, another correlation value C' is obtained. If the correlation value C' is less than the correlation value in the register, it means that the correlation value C is a maximum correlation value, and the slow acquisition success flag is pulled high; otherwise, the register value is updated, and the comparison of the correlation value in the next clock cycle continues.

[0025] The beneficial effects of this invention are as follows:

[0026] 1. Millimeter-wave ultra-high-speed communication and high-bandwidth signal processing technologies place higher demands on signal acquisition, rendering traditional single-carrier modulation acquisition methods inapplicable. This invention uses a shallow RAM to overlap and buffer high-speed sampled data, reducing hardware logic resource consumption while avoiding sampling deviations caused by jitter in the actual hardware clock source, effectively preserving complete data frames for related processing.

[0027] 2. The present invention adopts the method of finding the maximum value of the correlation peak, that is, finding the correlation peak value that is greater than the capture threshold, and the correlation peak numerically satisfies the condition that it is greater than the left and right correlation values, thus avoiding the generation of false correlation peaks due to signal oversampling, which would lead to misjudgment of the correlation peak value.

[0028] 3. This invention improves the stability and reliability of the acquisition results through a two-stage acquisition process. In the slow acquisition state, correlation processing and comparison decision are performed to initially obtain the starting position of the synchronization head. In the fast acquisition state, FFT transformation is performed on the correlation data to analyze the correlation peak changes in the frequency domain. Through the correspondence of discrete Fourier transform, the starting position of the synchronization head in the time domain is finally determined. Through the above dual acquisition in the time and frequency domains, accurate acquisition of the received signal is achieved. Attached Figure Description

[0029] Figure 1 This is a flowchart of the method of the present invention.

[0030] Figure 2 This is a diagram showing the relationships between the sub-modules of this invention.

[0031] Figure 3 This is a schematic diagram of the overlapping design structure of the present invention.

[0032] Figure 4 This is a Matlab simulation image of the relevant peaks captured in this invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0034] A stable and reliable low-resource-consumption serial capture device includes a data buffer module, a capture processing module, a comparison and decision module, a counting module, a flag register module, and a state switching module. The relationships between the sub-modules are as follows: Figure 2 As shown.

[0035] The entire acquisition system consists of four states: empty state, slow acquisition state, fast acquisition state, and data output state.

[0036] The data caching module is used to cache input data and output useful data by address indexing RAM. The data caching module is controlled by the capture system state. During the slow capture phase, it uses overlapping caching to cache the sampled multi-channel parallel input data; during the fast capture phase, it starts caching N numbers before the synchronization header arrives, where N is related to the number of parallel channels.

[0037] The data cache module's storage RAM is a simple dual-port RAM, with its input port A having a width of 384 bits and a depth of 9; and its output port B having a width of 12 bits and a depth of 288. The read / write addresses control the data input / output and the overlapping design. Each data storage depth is 256, with an overlapping storage depth of 128. See the diagram for the overlapping storage design. Figure 3 The specific method for overlapping caching is as follows:

[0038] Set the data buffer length RAM_LENGTH, buffer a segment of length RAM_LENGTH in a data frame, and mark the sample point number of the buffer segment in the data frame. Record the starting data sample point number as A and the ending data sample point number as B. When buffering the next segment, when the sample point number in the data frame is (A+B) / 2, data buffering is performed, and the buffer length is RAM_LENGTH.

[0039] The state switching module consists of the four states mentioned above. At the start of capture, it jumps from an empty state to a slow capture state. In the slow state, if the capture_flag1 flag is high, it switches to a fast capture state; otherwise, it maintains the current state. In the fast capture state, if the capture_flag2 flag is high, it switches to a data output state; otherwise, it maintains the current state. If no relevant peak is captured for a long time, i.e., the count flag temp_diff is greater than the set parameter, it jumps back to an empty state. After the output data is finished, it switches to an empty state. In each state, if the reset signal is high, it jumps back to an empty state.

[0040] The capture processing module is used to read data from the data buffer module during the slow capture phase and use serial sliding correlation to obtain the correlation value between the sampled data frame and the local synchronization sequence. During the fast capture phase, it reads data from the data buffer module, correlates it with the local synchronization sequence, and performs FFT transformation to obtain MN FFT transformation results, where M is a set value. The quantized local synchronization sequence is stored in the local register, and the serial correlation register is set to 48. The quantized local synchronization sequence and the sampled data read from RAM are used to perform serial sliding correlation calculation. After a certain delay, the calculated correlation value is output according to the clock.

[0041] The comparison and decision module exists in both slow and fast acquisition states. Its purpose is to find the maximum correlation peak that meets the conditions. In the simulation, the acquisition threshold value T is set to 350. In the slow acquisition phase, the correlation value calculated by sliding correlation is compared with the acquisition threshold value T. The maximum correlation value that is greater than the threshold is taken as the captured correlation peak value, and the synchronization head is initially located. In the fast acquisition phase, the maximum value in the FFT transform result is found. The starting position of the synchronization head corresponding to the maximum value is found through the correspondence of discrete Fourier transform, and the accuracy of the synchronization head address obtained in the slow acquisition phase is confirmed.

[0042] The counter module mainly includes data information such as the sequence number count of the frame data in the input buffer, the count required for the overlapping design, and the output count.

[0043] The flag register module is mainly used to register capture success flags and output enable signals in various states, providing flag information for capture process control such as comparison decision and state switching.

[0044] Specifically, refer to Figure 1 This method includes the following steps:

[0045] Step 1: Set the frame structure for transmitted data. In the frame structure design, select a PN sequence of length 42 with good autocorrelation as the start of the synchronization header, used for signal acquisition at the receiving end. Refer to the following for the transmitting end frame structure design. Figure 3 The length of the synchronization header reaching the receiving end after oversampling is 48.

[0046] Step 2: After the transmitted data is sampled by the ADC, it is sent to the acquisition processing module via 32 parallel signals from both the I and Q channels. Because the I and Q data are input in parallel and the signal rate is relatively fast, a slow acquisition state is first entered to buffer the input data. The buffer RAM is set as a simple dual-port RAM, with its input port A having a width of 384 bits and a depth of 9; and its output port B having a width of 12 bits and a depth of 288. In high-speed communication systems, to avoid the impact of clock jitter on the sampled data, this invention uses an overlapping buffering method for half of the data to ensure complete storage of the sampled data while reducing resource consumption.

[0047] Overlapping cache design, such as Figure 3 As shown, the RAM depth is 288, which is much smaller than the frame length of 131008. After caching begins, the first 256 bytes of RAM_LENGTH data from the first frame are first stored in RAM. After storage, the data is read out and sliding correlation processing is performed. After comparing and determining the correlation values, the search waits for the arrival of the next storage segment.

[0048] Generally, the processing time is short, meaning the segment to be stored can be found as soon as the second frame of data arrives. For ease of hardware implementation, the overlapping portion is designed to be half the storage length, RAM_LENGTH / 2 = 128. This means that 256 depth data is buffered starting from the 128th sampling point of the second frame, and so on. Furthermore, the frame length is an integer multiple of the storage length. When the buffered segment returns to the beginning of a frame, the first 128 data points repeat the sampling points from the end of the previous frame. This storage mode is only suitable for data storage during slow capture.

[0049] Step 3: In slow capture state, the RAM stored data is correlated with the local synchronization sequence. The RAM read address is controlled to read out the sampled data with a bit width of 12 bits in sequence. The data is correlated with the local cache synchronization sequence, i.e., the 48 PN sequences after sampling and quantization, through relative sliding. The data sliding correlation register has a length of 48. The correlation process is a shift, multiply and accumulate process. After calculating the result, the modulus value is the correlation value.

[0050] Step 4: After the correlation operation is completed, it is necessary to determine whether the correlation value is greater than the capture threshold T. In the simulation, the capture threshold T is set to 350. Because of signal oversampling, two adjacent correlation peaks may exist, that is, both adjacent correlation peaks are greater than the decision threshold T, resulting in a false correlation peak. Therefore, when comparing the decision, it is necessary to find the true correlation peak, that is, to obtain the maximum value of the correlation peak. Based on the correlation value calculated per clock cycle of the sliding correlation in Step 3, when the correlation value C is greater than the threshold T, it is considered that the correlation peak has been initially found, and the value is temporarily stored in the register. In the correlation operation of the next clock cycle, another correlation value C' is obtained. If the correlation value C' is less than the correlation value in the register, it means that the correlation value C is a maximum correlation value, that is, the capture is successful in the current state, the slow capture success flag capture_flag1 is pulled high, and the fast capture state is entered for frame header relocation; otherwise, the register value is updated and the current state continues.

[0051] Step 5: After successfully finding the synchronization header in the slow acquisition state, switch to the fast acquisition state. In the fast acquisition state, RAM storage only needs to buffer data starting N sampling points before the frame header arrives. Considering the case of 32 parallel inputs, this invention takes N as 64 and M as 2, buffering a total of 128 sampling points for correlation and FFT processing. When data arrives at this position, buffering begins. The buffered data is correlated with the local sequence and subjected to FFT transformation to obtain MN FFT transformation results. The maximum value among these results is found, and the corresponding synchronization header time-domain start position is found through the discrete Fourier transform correspondence.

[0052] Step 6: Verify the accuracy of the synchronization header address obtained in the slow acquisition state. If the synchronization header address is confirmed to be correct, the synchronization header of the data frame is considered to have been accurately located, and data can be output according to the required information. Through dual acquisition decisions in the time and frequency domains, the location of the synchronization header can be reliably and stably found. See Matlab simulation for capturing the relevant peaks. Figure 4 .

[0053] The simulation results of this method are as follows:

[0054] 1. Conditions

[0055] Capture the synchronization header sequence: PN sequence

[0056] Sliding related register length: 48

[0057] Frame length: 131008

[0058] Vivado emulation clock frequency: 200MHz

[0059] Related latency: 320ns

[0060] FFT transform points: 128

[0061] 2. Results Analysis

[0062] This method completes the synchronization header capture of the received end sampled data under the above conditions, and the results are as follows: Figure 4 As shown in the Matlab simulation data graph of the captured correlation peak, there are obvious captured correlation peaks, and the peak data are consistent with the hardware implementation results, demonstrating the effectiveness of the method of the present invention.

[0063] In summary, this invention proposes a stable and reliable low-resource-consumption serial acquisition device and method. By employing an overlapping storage design to completely buffer the received-end sampled data frames, it reduces hardware logic resource consumption while avoiding sampling deviations caused by jitter in the actual hardware clock source, effectively preserving complete data frames for correlation processing. By utilizing correlation peak maxima and secondary acquisition decision, it avoids misjudgments caused by spurious correlation peaks resulting from signal oversampling. This enables accurate real-time acquisition and effective information output of the synchronization head in a single-carrier modulation and demodulation system under conditions of low RAM resource consumption and high-speed information transmission.

[0064] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A stable and reliable serial capture device with low resource consumption, characterized in that, It includes a data caching module, a capture processing module, a comparison and decision module, a counting module, a flag register module, and a state switching module, among which: The data caching module is used to cache the sampled multi-channel parallel input data in the slow acquisition phase using overlapping caching; in the fast acquisition phase, it starts caching N numbers before the synchronization header arrives, where N is related to the number of parallel channels. The capture processing module is used to read data from the data buffer module during the slow capture phase and use serial sliding correlation to obtain the correlation value between the sampled data frame and the local synchronization sequence; during the fast capture phase, it reads data from the data buffer module, correlates it with the local synchronization sequence, and performs FFT transformation to obtain MN FFT transformation results; where M is a set value. The comparison and decision module is used in the slow acquisition phase to compare the correlation value calculated by sliding correlation with the acquisition threshold T, and take the maximum correlation value greater than the threshold as the captured correlation peak value to initially locate the synchronization head; in the fast acquisition phase, it finds the maximum value in the FFT transform result, finds the starting position of the synchronization head corresponding to the maximum value through the correspondence of discrete Fourier transform, and confirms whether the synchronization head address obtained in the slow acquisition phase is accurate. The counter module is used to cyclically count the sampling points cached in the data cache module; The flag register module is used to store various flag variables of the comparison and decision module; The state switching module is used to control the state switching of the capture system and the processing flow of each module according to the various flag variables stored in the flag register module, and to control the data buffer module to output the required data according to the synchronization header address; the entire capture system state includes empty state, slow capture state, fast capture state and data output state; The specific method of overlapping caching in the data caching module is as follows: Set the data buffer length RAM_LENGTH, buffer a segment of length RAM_LENGTH in a data frame, and mark the sample point number of the buffer segment in the data frame. Record the starting data sample point number as A and the ending data sample point number as B. When buffering the next segment, when the sample point number in the data frame is (A+B) / 2, data buffering is performed, and the buffer length is RAM_LENGTH.

2. A stable and reliable serial acquisition method with low resource consumption, characterized in that, Includes the following steps: Step 1: During the slow acquisition phase, the multi-channel parallel data sampled by the ADC is buffered using an overlapping buffer method. Step 2: During the slow capture phase, data is read sequentially from the cache, and the relevant values ​​are calculated using a sliding correlation calculation method. Step 3: Determine if the correlation value is greater than the capture threshold. Take the maximum correlation value that is greater than the threshold as the captured correlation peak value to initially locate the synchronization head. Step 4: Enter the fast acquisition phase. N numbers are buffered before the synchronization head arrives, for a total of MN sampling points. The buffered data is correlated with the local sequence and subjected to FFT transformation to obtain MN FFT transformation results. The maximum value among the FFT transformation results is found, and the synchronization head start position corresponding to the maximum value is found through the correspondence of discrete Fourier transform. Here, M is a set value, and N is related to the number of parallel paths. Step 5: Based on the synchronization header start position obtained in the fast acquisition phase, confirm whether the synchronization header address obtained in the slow acquisition phase is accurate. If the address is correct, it is considered that the synchronization header of the data frame has been accurately located; otherwise, return to step 4. In step 1, the specific method of overlapping caching is as follows: Set the data buffer length RAM_LENGTH, buffer a segment of length RAM_LENGTH in a data frame, and mark the sample point number of the buffer segment in the data frame. Record the starting data sample point number as A and the ending data sample point number as B. When buffering the next segment, when the sample point number in the data frame is (A+B) / 2, data buffering is performed, and the buffer length is RAM_LENGTH.

3. The stable and reliable low-resource-consumption serial acquisition method according to claim 2, characterized in that, Step 3 is implemented as follows: When the correlation value C is greater than the threshold T, the correlation peak is initially found, and the correlation value C is stored in the register. In the next clock cycle, another correlation value C' is obtained. If the correlation value C' is less than the correlation value in the register, it means that the correlation value C is a maximum correlation value, and the slow acquisition success flag is pulled high; otherwise, the register value is updated, and the comparison of the correlation value in the next clock cycle continues.

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