A method, system, apparatus and medium for SDH eye diagram detection and correction

Abstract

The application discloses an SDH eye diagram detection and correction method, system, device and storage medium, wherein the method comprises the following steps: acquiring a plurality of frame signals of each of a plurality of SDH eye diagrams; determining alarm error code information according to the plurality of frame signals; and determining the left boundary and the right boundary of the SDH eye diagram according to the alarm error code information. The method can improve the noise and jitter of digital signals in transmission, improve the integrity, stability and reliability of digital signal transmission, and improve the problems of SDH transmission chain data error code degradation and service loss of an SDH self-healing network element device. The application can be widely applied to the technical field of signal transmission.

Description

Technical Field

[0001] This application relates to the field of signal transmission technology, and in particular to an SDH eye diagram detection and correction method, system, device and storage medium. Background Technology

[0002] With the development of communication technology, the application of SDH bidirectional self-healing ring networks built using digital cross-connect (SDXC) equipment is becoming increasingly widespread. SDXC has strict requirements for clock quality and primarily uses a master-slave clock synchronization method within the ring network. The highest-level clock in the network is called the reference master clock or reference clock, also known as the gateway element clock. A series of hierarchical clocks are cascaded below the gateway element clock, and each level clock is synchronized with its predecessor, i.e., the synchronization clock extracted by the next-level network element from the received signal. SDH allows the mixed transmission of PDH signals at different rates (2Mbit / s, 34Mbit / s, 140Mbit / s). SDH's unique pointer adjustment can cause significant phase jumps and frequency differences at the SDH / PDH network boundary. Combined with the performance differences of network elements within the network, as the number of cascaded network element links increases, noise during the synchronization allocation process and drift caused by temperature changes will gradually degrade the clock synchronization quality of the last network element in the synchronization transmission chain, leading to bit errors in the transmission channel and even service loss. Therefore, there are still technical problems that need to be solved in this field. Summary of the Invention

[0003] The purpose of this application is to at least partially solve one of the technical problems existing in the prior art.

[0004] Therefore, one objective of the embodiments of this application is to provide an SDH eye diagram detection and correction method, system, apparatus and storage medium that can improve the integrity, stability and reliability of digital signal transmission.

[0005] To achieve the above technical objectives, the technical solution adopted in this application includes: an SDH eye diagram detection and correction method, comprising: acquiring several frame signals of each of the SDH eye diagrams; determining alarm error information based on the several frame signals; and determining the left and right boundaries of the SDH eye diagram based on the alarm error information.

[0006] In addition, the SDH eye diagram detection and correction method according to the above embodiments of the present invention may also have the following additional technical features:

[0007] Furthermore, in this embodiment of the application, the step of acquiring several frame signals of several SDH eye diagrams specifically includes: acquiring N frame signals of each SDH eye diagram in several SDH eye diagrams sequentially within a first preset time period; wherein, the clock phase parameter difference between any two adjacent SDH eye diagrams in the several SDH eye diagrams is 10 degrees; N is an integer, N≥6.

[0008] Furthermore, in this embodiment of the application, the alarm error information includes left alarm error information and right alarm error information. The step of determining the left and right boundaries of the SDH eye diagram based on the alarm error information specifically includes: determining the left boundary of the SDH eye diagram based on the left alarm error information; and determining the right boundary of the SDH eye diagram based on the right alarm error information.

[0009] Further, in this embodiment of the application, the alarm error information includes left alarm error information and right alarm error information. The step of determining the alarm error information based on the plurality of frame signals specifically includes: traversing and scanning each frame signal of all the plurality of SDH eye diagrams to the left along the time axis of the SDH eye diagram, and determining the frame signal with a phase transition of 180 degrees to 0 degrees or a rising edge or a falling edge as the left signal; determining the left alarm error information based on the left signal; traversing and scanning each frame signal of all SDH eye diagrams to the right along the time axis of the SDH eye diagram, and determining the frame signal with a phase transition of 180 degrees to 0 degrees or a rising edge or a falling edge in any SDH eye diagram as the right signal; determining the right alarm error information based on the right signal.

[0010] Furthermore, in this embodiment of the application, the method further includes determining the optimal sampling point based on the left eye diagram and the right eye diagram.

[0011] Furthermore, in this embodiment of the application, the step of determining the optimal sampling point based on the left eye diagram and the right eye diagram specifically includes: determining the clock phase parameter corresponding to the left signal as the first sampling parameter and determining the clock phase parameter corresponding to the right signal as the second sampling parameter; and determining the optimal sampling point based on the first sampling parameter and the second sampling parameter.

[0012] Furthermore, in this embodiment of the application, the step of determining the optimal sampling point based on the first sampling parameter and the second sampling parameter specifically includes: subtracting the first sampling parameter and the second sampling parameter to obtain a first sampling difference; taking the absolute value of the first sampling difference to obtain a first absolute value; and taking half of the first absolute value as the optimal sampling point.

[0013] On the other hand, embodiments of this application also provide an SDH eye diagram detection and correction system, comprising: an acquisition unit, configured to acquire several frame signals of each of the SDH eye diagrams; a first processing unit, configured to determine alarm error information based on the several frame signals; and a second processing unit, configured to determine the left boundary and right boundary of the SDH eye diagram based on the alarm error information.

[0014] On the other hand, this application also provides an SDH eye diagram detection and correction device, comprising:

[0015] At least one processor;

[0016] At least one memory for storing at least one program;

[0017] When the at least one program is executed by the at least one processor, the at least one processor implements an SDH eye diagram detection and correction method as described in any one of the inventions.

[0018] In addition, this application also provides a storage medium storing processor-executable instructions, which, when executed by a processor, are used to perform an SDH eye diagram detection and correction method as described in any of the preceding claims.

[0019] The advantages and beneficial effects of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application:

[0020] This application can acquire several frames of signals from each of several SDH eye diagrams; determine alarm error information based on the several frames of signals; determine the left and right boundaries of the SDH eye diagram based on the alarm error information; and complete eye diagram detection and correction based on the left and right boundaries. This application can improve noise and jitter in digital signal transmission, and enhance the integrity, stability, and reliability of digital signal transmission. It can also improve the problems of data error degradation and service loss in the SDH transmission link of SDH self-healing network elements. Attached Figure Description

[0021] Figure 1 This is a schematic diagram illustrating the steps of an SDH eye diagram detection and correction method in a specific embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram illustrating the steps of determining the left and right boundaries of the SDH eye diagram based on alarm error information in a specific embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram illustrating the steps of determining alarm error information based on several frame signals in a specific embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram illustrating the steps of determining the optimal sampling point based on the left eye image and the right eye image in a specific embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram illustrating the steps of determining the optimal sampling point based on the first sampling parameter and the second sampling parameter in a specific embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of a system for implementing another SDH eye diagram detection and correction method in a specific embodiment of the present invention;

[0027] Figure 7 This is a flowchart illustrating the SDH eye diagram detection and correction method in another specific embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of left boundary search in a specific embodiment of the present invention;

[0029] Figure 9 This is a schematic diagram of right boundary search in a specific embodiment of the present invention;

[0030] Figure 10 This is a schematic diagram of the optimal sampling point in a specific embodiment of the present invention;

[0031] Figure 11 This is a schematic diagram of the structure of an SDH eye diagram detection and correction system in a specific embodiment of the present invention;

[0032] Figure 12 This is a schematic diagram of the structure of the SDH eye diagram detection and correction device in a specific embodiment of the present invention. Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings, illustrates the principles and processes of the SDH eye diagram detection and correction method, system, apparatus, and storage medium in the embodiments of the present invention.

[0034] With the development of communication technology, the application of SDH bidirectional self-healing ring networks built using digital cross-connect devices (SDXC) is becoming increasingly widespread. SDXC has strict requirements for clock quality and primarily uses a master-slave clock synchronization method within the ring network. The highest-level clock in the network is called the reference master clock or reference clock, also known as the gateway element clock. A series of hierarchical clocks are cascaded below the gateway element clock, and each level of clock is synchronized with its predecessor, i.e., the synchronization clock extracted by the next-level network element from the received signal. SDH allows the mixed transmission of PDH signals at different rates (2 Mbit / s, 34 Mbit / s, 140 Mbit / s). SDH's unique pointer adjustment can cause significant phase jumps and frequency differences at the SDH / PDH network boundary. Combined with the performance differences of network elements within the network, as the number of cascaded network element links increases, noise during the synchronization allocation process and drift caused by temperature changes will gradually degrade the clock synchronization quality of the last network element in the synchronization transmission chain, leading to bit errors in the transmission channel and even service loss.

[0035] Therefore, ensuring the stability and reliability of data transmission between self-healing network-level networking devices, quickly detecting the transmission quality of digital signals, and improving the noise and jitter of digital signals during transmission are urgent problems that need to be solved.

[0036] To address the aforementioned technical problems, this application provides an SDH eye diagram detection and correction method. (Refer to...) Figure 1 , Figure 1 This is a schematic diagram illustrating the steps of an SDH eye diagram detection and correction method. Figure 1 The method may include, but is not limited to, steps S101-S103.

[0037] S101. Obtain several frames of signal from each of the several SDH eye diagrams.

[0038] It should be noted that "several SDH eye diagrams" can refer to several SDH eye diagrams that differ from each other by a certain clock phase parameter. "Several frames of signal" can refer to several frames of any one of the SDH eye diagrams.

[0039] In some feasible embodiments of this application, the processing circuit or system can first be electrically or signal-connected to the signal acquisition module. Through signal and data transmission between the modules or system, the processing circuit or system can ultimately obtain several frames of signals from each of the SDH eye diagrams. This processing circuit or system can acquire the several frames of signals acquired by the signal acquisition module via wired or wireless connection. It should be noted that the aforementioned limited connection methods can include the connection between the mobile device and the processing module, the connection between the processing module and the signal acquisition module, and wired connections between other known or future-developed devices and the processing module; while the aforementioned wireless connection methods can include, but are not limited to, 3G / 4G / 5G connections, WiFi connections, Bluetooth connections, WiMAX connections, Zigbee connections, UWB (Ultra Wide Band) connections, and other known or future-developed wireless connection methods.

[0040] S102. Determine the alarm error information based on several frame signals.

[0041] It is understandable that alarm error information can be used for subsequent alarms, and it can correspond to a frame signal with a phase transition of 180 degrees to 0 degrees or with a rising or falling edge.

[0042] In some feasible embodiments of this application, the processor can determine alarm error information from several frame signals through a specific detection strategy in several SDH eye diagrams, and this alarm error information can correspond to an SDH eye diagram.

[0043] S103. Based on the alarm error information, determine the left and right boundaries of the SDH eye diagram.

[0044] It is understandable that each SDH eye diagram can have both a left and a right boundary. Alarm error information can correspond to either a left or right boundary.

[0045] In some feasible embodiments of this application, the processor can determine the left boundary of the corresponding SDH eye diagram based on the alarm error information. After determining the left boundary, the processor can also determine the corresponding right boundary based on the alarm error information.

[0046] Furthermore, the step of acquiring several frames of signals from several SDH eye diagrams may include, but is not limited to, step 201.

[0047] S201. Within a first preset time period, acquire N frame signals of each SDH eye diagram in a plurality of SDH eye diagrams in sequence; wherein, the clock phase parameter difference between any two adjacent SDH eye diagrams in the plurality of SDH eye diagrams is 10 degrees; N is an integer, N≥6.

[0048] Understandably, the first preset time can be any time, which can be adjusted according to user needs and hardware characteristics, while N can be any integer greater than or equal to 6. Each SDH has a specific order; that is, within the first preset time, six or more frames of signals from each SDH eye diagram are acquired sequentially.

[0049] Furthermore, referring to Figure 2 , Figure 2 This is a schematic diagram illustrating the steps of determining the left and right boundaries of the SDH eye diagram based on alarm error information. Figure 2 In this process, alarm error information may include left alarm error information and right alarm error information. The step of determining the left and right boundaries of the SDH eye diagram based on the alarm error information may include, but is not limited to, steps S301-S302.

[0050] S301. Determine the left boundary of the SDH eye diagram based on the left alarm error information.

[0051] S302. Determine the right boundary of the SDH eye diagram based on the right alarm error information.

[0052] In some feasible embodiments of this application, alarm error information may include left alarm error information and right alarm error information. Both left and right alarm error information can be determined by a built-in processing strategy. Left alarm error information can correspond to the determination of the left boundary of the SDH eye diagram, while right alarm error information can correspond to the determination of the left boundary of the SDH eye diagram.

[0053] Furthermore, referring to Figure 3 , Figure 3 This is a schematic diagram illustrating the steps for determining alarm error information based on several frame signals. Figure 3 In this process, the alarm error information may include left alarm error information and right alarm error information. The step of determining the alarm error information based on several frame signals may include, but is not limited to, steps S401-S404.

[0054] S401. Along the time axis of the SDH eye diagram to the left, traverse and scan each frame signal of all several SDH eye diagrams, and determine the frame signal with a phase transition of 180 degrees to 0 degrees or with a rising edge or falling edge as the left signal.

[0055] S402. Determine the left alarm error code information based on the left signal.

[0056] S403. Traverse along the time axis of the SDH eye diagram and scan each frame signal of all SDH eye diagrams to the right. Determine the frame signal in any SDH eye diagram that has a phase transition from 180 degrees to 0 degrees or has a rising or falling edge as the right signal.

[0057] S404. Determine the right alarm error code information based on the right signal.

[0058] In some embodiments of this application, the processor can scan each frame signal of all SDH eye diagrams along the time axis to the left, determining that a frame signal with a 180-degree to 0-degree phase transition or a rising or falling edge is a left signal. After obtaining the left signal, a left alarm error message can be generated and sent to the next-level processor. The next-level processor can determine the frame signal as the left boundary based on the left alarm error message. After determining the left boundary, the processor scans each frame signal of all SDH eye diagrams along the time axis to the right, determining that a frame signal with a 180-degree to 0-degree phase transition or a rising or falling edge in any SDH eye diagram is a right signal, and sends it to the next-level processor. The next-level processor can determine the frame signal as the right boundary based on the right alarm error message.

[0059] Furthermore, referring to Figure 4 , Figure 4 This is a schematic diagram illustrating the steps for determining the optimal sampling point based on the left and right eye images. Figure 4 In this application, the SDH eye diagram detection and correction method may further include, but is not limited to, step S501, determining the optimal sampling point based on the left and right eye diagrams. (Referring to...) Figure 4 , Figure 4 Yes. In Figure 4 In step S501, determining the optimal sampling point based on the left and right eye diagrams may include, but is not limited to, steps S601-S602:

[0060] S601. Determine the clock phase parameter corresponding to the left signal as the first sampling parameter and determine the clock phase parameter corresponding to the right signal as the second sampling parameter;

[0061] S602. Determine the optimal sampling point based on the first sampling parameter and the second sampling parameter.

[0062] In some feasible embodiments of this application, after the processor determines that the clock phase parameter corresponding to the left signal is the first sampling parameter and the clock phase parameter corresponding to the right signal is the second sampling parameter, it can input them into a specific calculation formula to finally obtain an optimal sampling point.

[0063] Furthermore, referring to Figure 5 , Figure 5 This is a schematic diagram illustrating the steps for determining the optimal sampling point based on the first and second sampling parameters. Figure 5 In this process, the step of determining the optimal sampling point based on the first sampling parameter and the second sampling parameter may include, but is not limited to, steps S701-S703.

[0064] S701. Subtract the first sampling parameter from the second sampling parameter to obtain the first sampling difference;

[0065] S702. Take the absolute value of the first sampling difference to obtain the first absolute value;

[0066] S703, take half of the first absolute value as the optimal sampling point.

[0067] In some feasible embodiments of this application, the processor can subtract the first sampling parameter and the second sampling parameter to obtain a first sampling difference; then the processor can take the absolute value of the first sampling difference to obtain a first absolute value; finally, half of the first absolute value is taken as the optimal sampling point. Specifically, the following formula for determining the optimal sampling point can be referred to:

[0068] ΔUI_sel=|UI_1-UI_0| / 2

[0069] In the above formula, ΔUI_sel is the optimal sampling point, UI_1 is the first sampling parameter, and UI_0 is the second sampling parameter.

[0070] The following is in conjunction with the appendix Figure 6 and appendix Figure 7 Explanation of the specific calculation principles of this application:

[0071] Reference Figure 6The system that executes the algorithm in this application may include a clock phase-locked loop processing unit, a data sampling processing unit, an SDH frame parsing processing unit, and a calculation and control processing unit. The clock phase-locked loop (PLL) processing unit can extract and synchronize the line recovery clock, and output sampling clocks and SDH synchronization clocks of different phases according to the input phase adjustment parameters; the data sampling processing unit can extract bitstream data and convert it into parallel data under the driving of the sampling clock; the SDH frame parsing processing unit can perform frame descrambling, frame positioning, and parsing of SDH high-order overhead alarms and B1B2 errors, and transmit alarm and error information to the calculation and main control processing unit module; the calculation and control processing unit can perform the following functions: 1) start and exit eye diagram detection according to the alarm and error status obtained from SDH frame parsing; 2) automatically perform left and right boundary scanning of the eye diagram; 3) synchronously output phase adjustment parameters to the PLL processing unit for reference clock phase adjustment; 4) automatically calculate and determine the clock phase point of the best sampling point based on the phase data results obtained from the left and right boundary scanning, and lock the best decision time (best sampling time point) of the current eye diagram.

[0072] In this embodiment, the first preset time is 1 second, and the signal of each SDH eye diagram consists of 16 frames. The specific process can be found in [reference needed]. Figure 7 , Figure 8 , Figure 9 as well as Figure 10 .

[0073] exist Figure 7 In this context, the process may include:

[0074] 1. First, the FPGA software determines whether the current channel meets the conditions for initiating eye diagram detection and calibration. If the conditions are met, the workflow begins; otherwise, it continues to wait for the start signal. The main start conditions include: 1) The SDH channel has not undergone eye diagram detection and calibration; 2) Eye diagram detection and calibration have been completed, but due to SDH channel degradation (severe alarm errors, channel interruption and reconnection, etc.), it is waiting for the channel to recover; 3) Eye diagram detection and calibration are performed manually.

[0075] 2. After the workflow is started, the search and processing flow for the left boundary of the eye diagram begins. The steps for searching and processing the left boundary are described below:

[0076] 1) Start the search timer, set a timer of 1 second. If the left boundary state cannot be scanned after 1 second of loop detection, exit the current search and start again.

[0077] 2) Decrease the clock phase parameter by 10 degrees, output a sampling clock with a phase reduced by 10 degrees (clock phase shifted 10 degrees to the left), wait for 2 milliseconds (2 milliseconds has been used to collect 16 frames of data), and read the alarm error status output by the frame parsing module.

[0078] 3) Based on the historical alarm error rate of the decreasing phase adjustment, a comparative analysis is performed with the currently acquired alarm error rate. The analysis and processing logic is as follows: a) If the state of the acquisition channel after each clock phase adjustment is no alarm and no error, while the current acquired data is in a state with alarms and errors, i.e., the left boundary point of the eye diagram, the current phase adjustment parameter is recorded as UI_0; b) If it is not the case in a), then continue to execute the workflow of 1), 2), and 3) until timeout and exit;

[0079] 4) The criteria for determining the left boundary of the eye diagram are: when the sampling clock phase changes from 180 degrees to 0 degrees or increases / decreases in fixed steps (e.g., 10 degrees each time), the sampled data, after frame parsing, exhibits a transition from no alarm errors to alarm errors (i.e., a transition from good to bad channel data transmission quality); the left boundary search diagram is shown below. Figure 8 As shown

[0080] 3. Right boundary search will only be initiated when the left boundary point of the eye diagram is found. The right boundary search workflow is described as follows:

[0081] 1) After confirming that the left boundary point has been found, start the right boundary search timer for 1 second. If the right boundary state cannot be scanned after 1 second of loop detection, exit the current search and start the search from the left boundary again.

[0082] 2) Increment the clock phase parameter by 10 degrees, output a sampling clock with an increased phase of 10 degrees (clock phase shifted 10 degrees to the right), wait for 2 milliseconds, and read the alarm error status output by the frame parsing module.

[0083] 3) Based on the historical alarm error rate of incremental phase adjustment, a comparative analysis is performed with the currently acquired alarm error rate. The analysis and processing logic is as follows: b) If the state of the acquired channel after each incremental clock phase adjustment is no alarm and no error, while the current acquired data is in a state with alarms and errors, that is, the right boundary point of the eye diagram, the current phase adjustment parameter is recorded as UI_1; c) If it is not the case in b) above, then continue to execute the workflow of 1), 2), and 3) until timeout and exit;

[0084] 4) The criteria for determining the right boundary of the eye diagram are the same as those for determining the left boundary. A diagram illustrating the right boundary search is shown below. Figure 9 As shown.

[0085] 4. After searching the left and right boundaries, the phase adjustment parameter values ​​UI_0 and UI_1 can be obtained respectively. The absolute phase difference between the left and right boundary points is: ΔUI = |UI_1 - UI_0|, where ΔUI is denoted as the eye diagram width. The eye diagram width is used to determine if data calibration is required (eye diagram width greater than 0.5UI). If the eye diagram width meets the calibration requirements, the optimal decision time (optimal sampling point) is counted based on the current eye diagram width. The optimal sampling point UI_sel = ΔUI / 2, which is the midpoint of the eye diagram width. If the eye diagram width does not meet the calibration requirements, the process returns to the initial workflow and repeats until the optimal sampling point is found. A diagram of the optimal sampling point is shown below. Figure 10 As shown.

[0086] In addition, refer to Figure 11 ,and Figure 1 Corresponding to the method described above, this application also provides an SDH eye diagram detection and correction system in its embodiments. The system may include an acquisition unit 1001, a first processing unit 1002, and a second processing unit 1003. The acquisition unit 1001 can be used to acquire several frame signals of each SDH eye diagram from several SDH eye diagrams; the first processing unit 1002 can be used to determine alarm error information based on the several frame signals; and the second processing unit 1003 can be used to determine the left and right boundaries of the SDH eye diagram based on the alarm error information.

[0087] It should be noted that the acquisition module can be any integrated circuit module or microprocessor module obtained by integrating a chip with processing functions and its peripheral circuits using existing integration technology. Similarly, the processing module can also be any integrated circuit module or microprocessor module obtained by integrating a chip with processing functions and its peripheral circuits using existing integration technology. The processing module may also include one or more memories. These memories can be used to store mapping table information or retrieval results, etc.

[0088] In some feasible embodiments of this application, the acquisition unit 1001 can be located in the same gateway or a device with a processor as the first processing module 1002. The acquisition unit 1001 can acquire several frame signals from each of the several SDH eye diagrams through a chip inside its processor. The first processing unit 1002 can be used to determine alarm error information based on the several frame signals. The second processing unit can determine the left and right boundaries of the SDH eye diagram based on the alarm error information. The acquisition unit 1001 can be any hardware unit connected to the processor inside the gateway or device. The specific device connection methods and device settings between the acquisition unit 1001 and the first processing unit 1002, and between the first processing unit 1002 and the second processing unit 1003, are not limited.

[0089] It should be noted that the content of the above-described SDH eye diagram detection and correction method embodiments is applicable to this SDH eye diagram detection and correction system embodiment. The specific functions implemented by this SDH eye diagram detection and correction system embodiment are the same as those of the above-described SDH eye diagram detection and correction method embodiments, and the beneficial effects achieved are also the same as those achieved by the above-described SDH eye diagram detection and correction method embodiments.

[0090] and Figure 1 Corresponding to the method, this application also provides an SDH eye diagram detection and correction device, the specific structure of which can be referred to Figure 12 ,include:

[0091] At least one processor 1011;

[0092] At least one memory 1012 is used to store at least one program;

[0093] When at least one program is executed by at least one processor, the SDH eye diagram detection and correction method is implemented by at least one processor.

[0094] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0095] and Figure 1 Corresponding to the method described above, this application also provides a storage medium storing processor-executable instructions, which are used to execute the SDH eye diagram detection and correction method when executed by the processor.

[0096] It is understood that the content of the above-described SDH eye diagram detection and correction method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above-described SDH eye diagram detection and correction method embodiments, and the beneficial effects achieved are also the same as those achieved in the above-described SDH eye diagram detection and correction method embodiments.

[0097] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0098] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0099] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several programs to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequential list of executable programs for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can retrieve and execute a program from or in conjunction with such a program execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit a program for use by or in conjunction with a program execution system, apparatus, or device.

[0101] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0102] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0103] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0104] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0105] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method for SDH eye diagram detection and correction, characterized in that, include: Acquire several frame signals for each of the SDH eye diagrams; Based on the aforementioned frame signals, the alarm error information is determined; Based on the alarm error information, determine the left and right boundaries of the SDH eye diagram; The alarm error information includes left alarm error information and right alarm error information. The step of determining the alarm error information based on the plurality of frame signals specifically includes: Moving left along the time axis of the SDH eye diagram, traverse and scan each frame signal of all several SDH eye diagrams to determine the frame signal with a phase transition of 180 degrees to 0 degrees or with a rising or falling edge as the left signal. The left alarm error information is determined based on the left signal; Iterate along the time axis of the SDH eye diagram to the right for each frame signal of all SDH eye diagrams, and determine the frame signal in any SDH eye diagram that has a phase transition from 180 degrees to 0 degrees or has a rising or falling edge as the right signal; The right alarm error information is determined based on the right signal.

2. The SDH eye diagram detection and correction method according to claim 1, characterized in that, The step of acquiring several frames of signals from several SDH eye diagrams specifically includes: Within a first preset time period, N frame signals of each of the SDH eye diagrams in several SDH eye diagrams are acquired sequentially; Wherein, the clock phase parameter difference between any two adjacent SDH eye diagrams in the plurality of SDH eye diagrams is 10 degrees; N is an integer, N≥6.

3. The SDH eye diagram detection and correction method according to claim 1, characterized in that, The alarm error information includes left alarm error information and right alarm error information. The step of determining the left and right boundaries of the SDH eye diagram based on the alarm error information specifically includes: The left boundary of the SDH eye diagram is determined based on the left alarm error information; The right boundary of the SDH eye diagram is determined based on the right alarm error information.

4. The SDH eye diagram detection and correction method according to claim 1, characterized in that, The method further includes determining the optimal sampling point based on the left and right signals.

5. The SDH eye diagram detection and correction method according to claim 4, characterized in that, The step of determining the optimal sampling point based on the left and right signals specifically includes: The clock phase parameter corresponding to the left signal is determined as the first sampling parameter, and the clock phase parameter corresponding to the right signal is determined as the second sampling parameter. The optimal sampling point is determined based on the first sampling parameter and the second sampling parameter.

6. The SDH eye diagram detection and correction method according to claim 5, characterized in that, The step of determining the optimal sampling point based on the first sampling parameter and the second sampling parameter specifically includes: The first sampling difference is obtained by subtracting the first sampling parameter and the second sampling parameter; Take the absolute value of the first sampling difference to obtain the first absolute value; The optimal sampling point is half of the first absolute value.

7. A system for implementing the SDH eye diagram detection and correction method as described in any one of claims 1-6, characterized in that, include: The acquisition unit is used to acquire several frame signals of each of the SDH eye diagrams in several SDH eye diagrams; The first processing unit is used to determine alarm error information based on the plurality of frame signals; The second processing unit is used to determine the left and right boundaries of the SDH eye diagram based on the alarm error information.

8. An SDH eye diagram detection and correction device, characterized in that... include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the SDH eye diagram detection and correction method as described in any one of claims 1-6.

9. A storage medium storing processor-executable instructions, characterized in that, The processor-executable instructions, when executed by the processor, are used to perform an SDH eye diagram detection and correction method as described in any one of claims 1-6.

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