A parallel implementation method and system of a quantum attack-resistant SPHINCS+ signature algorithm for a GPU

Abstract

The application discloses a GPU anti-quantum attack SPHINCS+ signature algorithm parallel implementation method and system, and through four-layer parallel strategies, including first-stage inter-tree parallel, second-stage inter-node parallel, third-stage intra-node parallel and fourth-stage hash function parallel, a GPU anti-quantum attack SPHINCS + signature method is obtained through the design of the parallel, deployment and implementation modules. + signature method is obtained through the design of the parallel, deployment and implementation modules.

Description

Technical Field

[0001] This invention belongs to the field of network security technology, specifically relating to a parallel implementation method and system for the GPU-based quantum attack-resistant SPHINCS+ signature algorithm. Background Technology

[0002] Cybersecurity is a comprehensive discipline encompassing network device security, network information security, and network software security. Secure transmission of information is a part of network information security, primarily involving cryptography. Digital signature methods can indicate whether data has been tampered with after transmission over the network; they are a ubiquitous network authentication technology. Among these, SPHINCS... + It is a hash-based digital signature method that can resist quantum threats and was selected as the next standardization method in 2022.

[0003] The quantum threat refers to the possibility that methods like Shor and Grover could use quantum computers to break existing cryptographic systems such as RSA, DSA, and ECDSA. If large-scale quantum computers with sufficient computing power are developed, breaking existing cryptographic systems will become feasible. With the rapid development of quantum computers, researching methods to resist the quantum threat is becoming increasingly important. Previously, XMSS and LMS methods were the only standardized quantum-resistant signature methods, along with SPHINCS. + Both are hash-based methods, but they differ in that they are stateful methods with certain limitations, such as synchronizing state across multiple devices. SPHINCS, on the other hand... + It is a stateless method, therefore there are no restrictions on its use.

[0004] However, due to the use of stateless modules, the computational cost of stateless methods is higher than that of stateful methods. Therefore, in order to improve SPHINCS... + The usability of signature methods urgently needs to be improved, and the efficiency of method execution needs to be enhanced. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the shortcomings of the prior art by providing a parallel implementation method and system for the quantum attack-resistant SPHINCS+ signature algorithm for GPUs, thereby solving the problems of SPHINCS... + The technical problem that digital signature methods cannot effectively utilize the parallel operation of GPU multi-core architecture.

[0006] The present invention adopts the following technical solution:

[0007] A parallel implementation method for the quantum attack-resistant SPHINCS+ signature algorithm on GPUs includes the following steps:

[0008] S1, according to SPHINCS+ The parameter set, GPU architecture information and internal structure design parallelization scheme include first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism and fourth-level hash function parallelism.

[0009] S2. Based on the four-level parallel scheme obtained in step S1, deploy the first-level inter-tree parallel scheme to obtain the code for deploying the first-level parallel scheme, including the parallel schemes for FORS signature generation and FORS signature verification.

[0010] S3. Based on the four-level parallel scheme determined in step S1 and the code of the first-level parallel scheme obtained in step S2, deploy the second-level inter-node parallel scheme to obtain the code of two-level parallelism, including the parallel construction scheme of XMSS tree and FORS tree.

[0011] S4. Based on the four-level parallel scheme determined in step S1 and the two-level parallel code obtained in step S3, deploy the third-level intra-node parallel scheme to obtain the three-level parallel code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + Parallel schemes for signature verification;

[0012] S5. Based on the four-level parallel scheme determined in step S1 and the three-level parallel code obtained in step S4, deploy the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions executed in parallel.

[0013] Specifically, step S1 is as follows:

[0014] S101. Use a GPU architecture information collection tool to collect information on the number of GPU cores, including the number of multiprocessors, the number of cores on each multiprocessor, and the total number of cores;

[0015] S102, via SPHINCS + The parameter set and the total number of GPU cores determined in step S101 determine the maximum parallelism;

[0016] S103. Determine the number of parallel stages to be used based on the maximum parallelism and internal structure determined in step S102.

[0017] Furthermore, in step S103, the parallel stages are deployed in a manner from low to high level.

[0018] Specifically, step S2 is as follows:

[0019] S201. Based on the number of parallel levels determined in step S1, deploy the first-level parallel scheme for generating key pairs into the FORS signature generation method to obtain the first-level parallel FORS parallel signature generation method. Multiple FORS trees are constructed independently and in parallel using multiple threads, and GPU synchronization technology is used at the end.

[0020] S202. Based on the number of parallel levels determined in step S1, deploy the first-level parallel scheme for generating key pairs into the FORS signature verification method to obtain the first-level parallel FORS parallel signature verification method. Multiple threads are used to independently and in parallel authenticate multiple FORS trees, and GPU synchronization technology is used at the end.

[0021] Specifically, step S3 is as follows:

[0022] S301. Based on the number of parallel levels determined in step S1 and the first-level FORS parallel signature generation method obtained in step S2, deploy the second-level parallel scheme for FORS signature generation to obtain the two-level FORS parallel signature generation method of the first and second levels. Divide the threads into several groups and construct the FORS tree independently and in parallel with each group.

[0023] S302. Deploy the second-level parallel scheme for parallel construction of the XMSS tree according to the parallel level determined in step S1, and obtain the second-level parallel construction scheme for the XMSS tree, constructing the XMSS tree in parallel with threads.

[0024] Furthermore, during the construction of the FORS tree and XMSS tree, each thread processes the computation of one node independently, and performs GPU synchronization operations after the construction of one layer of nodes in the tree is completed.

[0025] Specifically, step S4 is as follows:

[0026] S401. Deploy WOTS based on the parallel level determined in step S1 and the second-level XMSS tree parallel construction scheme obtained in step S3. + The third-level parallel scheme for key pair generation yields a two-level parallel XMSS tree construction algorithm for the second and third levels.

[0027] S402. Deploy the third-level WOTS according to the number of parallel stages determined in step S1. + The signature generation scheme yields a third-level WOTS. + The parallel signature scheme allows threads to independently and in parallel complete multiple n-byte calculations;

[0028] S403. Deploy the third-level WOTS according to the number of parallel stages determined in step S1. + The signature verification scheme yields a third-level WOTS. + The parallel signature verification scheme enables threads to independently and in parallel complete multiple n-byte calculations.

[0029] Furthermore, in step S401, the leaf nodes of the XMSS tree use WOTS. + Key pair generation, independent and parallel computation, each task is an n-byte computation, and threads independently and in parallel complete multiple n-byte computations.

[0030] Specifically, step S5 is as follows:

[0031] S501. Based on the parallel level determined in step S1 and the two-level XMSS tree parallel construction scheme obtained in step S4, deploy the fourth-level parallel scheme of the hash function so that the threads execute the hash function in parallel.

[0032] S502. Based on the parallel level determined in step S1 and the two-level FORS parallel signature generation algorithm obtained in step S3, deploy the fourth-level parallel scheme of the hash function, so that the threads execute the hash function in parallel.

[0033] S503. Based on the parallel level determined in step S1 and the two-level FORS parallel signature verification algorithm obtained in step S2, deploy the fourth-level parallel scheme of the hash function, so that the threads execute the hash function in parallel.

[0034] Secondly, embodiments of the present invention provide a parallel implementation system for the quantum attack-resistant SPHINCS+ signature algorithm using a GPU, comprising:

[0035] Design modules, based on SPHINCS + The parameter set, GPU architecture information and internal structure design parallelization scheme include first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism and fourth-level hash function parallelism.

[0036] The first-level module, based on the four-level parallel scheme obtained from the design module, deploys the first-level inter-tree parallel scheme, resulting in the code for deploying the first-level parallel scheme, including the parallel schemes for FORS signature generation and FORS signature verification.

[0037] The second-level module, based on the four-level parallel scheme determined by the design module and the code of the first-level parallel scheme obtained by the first-level module, deploys the second-level inter-node parallel scheme to obtain the code of two-level parallelism, including the parallel construction scheme of XMSS tree and FORS tree.

[0038] The third-level module, based on the four-level parallel scheme determined by the design module and the two-level parallel code obtained from the second-level module, deploys the intra-node parallel scheme of the third-level module, resulting in three-level parallel code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + Parallel schemes for signature verification;

[0039] The output module, based on the four-level parallel scheme determined by the design module and the three-level parallel code obtained from the third-level module, deploys the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions executed in parallel.

[0040] Compared with the prior art, the present invention has at least the following beneficial effects:

[0041] A parallel implementation method for the quantum attack-resistant SPHINCS+ signature algorithm on GPUs is proposed. This method adapts to the GPU architecture, determines the parallel scheme, and implements SPHINCS through five levels of parallelism: first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism. + Parallelism on the GPU. This allows for customization based on the specific GPU model and SPHINCS. + The parameters allow for the deployment of adapted parallel schemes. Furthermore, by providing a four-level parallel scheme, efficient parallelism can be achieved from small-scale to ultra-large-scale operations, providing a parallelization theory for fully utilizing GPU architecture.

[0042] Furthermore, by using GPU information, parameter sets, and internal structure to select a parallel scheme, we can ensure that the parallel scheme with the highest parallel efficiency is selected.

[0043] Furthermore, since the first level of parallelism is more efficient than the second level, the second level is more efficient than the third level, and the third level is more efficient than the fourth level, when the number of threads is small, the earlier levels of parallelism should be deployed first, while when the number of threads is large, deploying multiple levels of parallelism can provide higher parallelism.

[0044] Furthermore, by deploying a first-level parallel scheme for FORS signature generation and signature verification, multiple FORS trees can be computed in parallel. This is the most efficient parallel scheme, which can guarantee a high speedup ratio and significantly reduce the time for signature generation and signature verification.

[0045] Furthermore, by deploying a second-level parallel scheme for the XMSS tree and FORS tree, the leaf nodes are constructed in parallel, further reducing signature generation and verification time with only a small loss of parallel efficiency, while also reducing key pair generation time.

[0046] Furthermore, by providing WOTS + Key pair generation, WOTS + Signature generation and WOTS + The signature verification deployment employs a third-level parallel scheme, allowing threads to process n bytes of computation on an average basis. This maintains partial parallel efficiency while further increasing the degree of parallelism and speedup, thereby further shortening the time for key pair generation, signature generation, and signature verification.

[0047] Furthermore, by parallelizing all parallelizable hash functions in the program, the program's parallelism and speedup are further improved, shortening the time for key pair generation, signature generation, and signature verification, allowing the program to fully utilize GPU performance.

[0048] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0049] In summary, this invention provides XMSS tree construction, FORS parallel construction, and WOTS. + Multiple parallel construction schemes are proposed; strategically, a four-level parallel strategy provides a method for selecting the parallelism level, choosing the parallelism strategy based on the specific parameter set, GPU architecture, and algorithm structure, resulting in a GPU-resistant quantum attack scheme. + Parallel and efficient implementation of the signature method.

[0050] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0051] Figure 1 For SPHINCS + A schematic diagram of a four-level parallel framework. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0054] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0055] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0056] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0057] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0058] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0059] This invention provides a parallel implementation method for the quantum-resistant SPHINCS+ signature algorithm for GPUs. It employs a four-layer parallel strategy, including first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism. By combining the decisions of the multi-level parallel scheme, a quantum-resistant SPHINCS signature algorithm for GPUs is obtained. + A parallel implementation method for the signature method is presented. Through the design of parallelization, deployment, and implementation modules, a quantum-resistant SPHINCS implementation for GPUs is derived. + A parallel implementation system for signature methods.

[0060] Please see Figure 1 This invention discloses a parallel implementation method for the quantum attack-resistant SPHINCS+ signature algorithm on GPUs, comprising the following steps:

[0061] S1, according to SPHINCS + The parameter set, GPU architecture information and internal structure design parallelization scheme include a four-level parallel scheme, including first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism and fourth-level hash function parallelism.

[0062] S101. Use a GPU architecture information collection tool to collect information on the number of GPU cores, including the number of multiprocessors, the number of cores on each multiprocessor, and the total number of cores;

[0063] S102, via SPHINCS + The parameter set and the total number of GPU cores determined in step S101 determine the maximum parallelism;

[0064] SPHINCS + Parallelism at the parameter level is determined by multiple parameters. At the same time, the maximum parallelism of the parameter set needs to be determined for the three parts of key pair generation, signature generation and signature verification. Here, the maximum parallelism of these three parts is obtained by taking the maximum value of the number of GPU cores.

[0065] S103. Determine the number of parallel stages to be used based on the maximum parallelism and internal structure determined in step S102.

[0066] Parallelism levels are deployed from low to high. When the maximum parallelism is low, only the first level of parallelism can be deployed; when the maximum parallelism is high, the first and second levels of parallelism can be deployed, and so on. Furthermore, different internal structures determine the number of parallelism levels that can be used. In the Forest of Random Subsets (FORS) method, only the first, second, and fourth levels can be deployed, while in the Winternitzone-time signature (WOTS) method… + In this method, only the second, third, and fourth levels can be deployed.

[0067] S2. Based on the multi-level parallel scheme determined in step S1, deploy the first-level inter-tree parallel scheme to obtain the code for deploying the first-level parallel scheme, including the parallel schemes for FORS signature generation and FORS signature verification.

[0068] S201. Based on the number of parallel levels determined in step S103, deploy the first-level parallel scheme for generating key pairs into the FORS signature generation method to obtain the first-level parallel FORS parallel signature generation method.

[0069] Please see Figure 1Multiple threads construct multiple FORS trees independently and in parallel, and GPU synchronization technology is used at the end to ensure the correctness of subsequent operations;

[0070] S202. Based on the number of parallel levels determined in step S103, deploy the first-level parallel scheme for generating key pairs into the FORS signature verification method to obtain the first-level parallel FORS parallel signature verification method.

[0071] Please see Figure 1 Multiple threads independently and in parallel verify multiple FORS trees, and GPU synchronization technology is used at the end to ensure the correctness of subsequent operations.

[0072] S3. Based on the multi-level parallel scheme determined in step S1 and the code of the first-level parallel scheme obtained in step S2, deploy the second-level inter-node parallel scheme to obtain the code of two-level parallelism, including the parallel construction scheme of XMSS tree and FORS tree.

[0073] S301. Based on the number of parallel stages determined in step S103 and the first-level FORS parallel signature generation method obtained in step S201, deploy the second-level parallel scheme for FORS signature generation to obtain a two-level FORS parallel signature generation method with the first and second levels.

[0074] Please see Figure 1 The threads are first divided into several groups for building multiple trees. The threads are divided into several groups and the FORS tree is constructed independently and in parallel by group. Each thread processes the calculation of one node alone. After the construction of one layer of the tree is completed, GPU synchronization operation is performed to ensure that the next layer of calculation can obtain the correct data.

[0075] S302. Deploy the second-level parallel scheme for parallel construction of XMSS tree according to the parallel level determined in step S103, and obtain the second-level parallel construction scheme for XMSS tree.

[0076] Please see Figure 1 The XMSS tree is constructed in parallel by threads. Each thread processes the calculation of a subtree independently and performs a synchronization operation after the subtree is constructed. After that, each node at each level needs to perform a GPU synchronization operation to ensure that the next level of calculation can obtain the correct data.

[0077] S4. Based on the multi-level parallel scheme determined in step S1 and the two-level parallel code obtained in step S3, deploy the third-level intra-node parallel scheme to obtain the three-level parallel code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + A parallel scheme for three signature verification methods;

[0078] S401. Deploy WOTS based on the number of parallel stages determined in step S103 and the parallel construction scheme of the second-level XMSS tree obtained in step S302. + The third-level parallel scheme for key pair generation yields a two-level parallel construction method for the second and third levels of XMSS trees, such as... Figure 1 As shown in the third level of parallelism, the leaf nodes of the XMSS tree use WOTS. + Key pair generation, in which the computations can be performed independently and in parallel, each task is called an n-byte computation. The threads are first divided into multiple groups to process multiple leaf nodes. Each group of threads completes multiple n-byte computations independently and in parallel. After all computations are completed, GPU synchronization operations are performed to ensure that the threads can obtain the correct data.

[0079] S402. Deploy the third-level WOTS according to the parallel stages determined in S103. + The signature generation scheme yields a third-level WOTS. + Parallel signature schemes, such as Figure 1 As shown in the third level of parallelism, the threads are first divided into multiple groups to process multiple leaf nodes. Each group of threads completes multiple n-byte calculations independently and in parallel, and GPU synchronization is performed after all calculations are completed to ensure that the threads can obtain the correct data.

[0080] S403, Deploy the third-level WOTS according to the parallel stages determined in S103. + The signature verification scheme yields a third-level WOTS. + Parallel authentication schemes, such as Figure 1 As shown in the third level of parallelism, the threads are first divided into multiple groups, each processing multiple leaf nodes. Each group of threads completes multiple n-byte calculations independently and in parallel, and GPU synchronization is performed after all calculations are completed to ensure that the threads can obtain the correct data.

[0081] S5. Based on the multi-level parallel scheme determined in step S1 and the three-level parallel code obtained in step S4, deploy the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions that can be executed in parallel in the method.

[0082] S501, based on the parallel levels determined in S103 and the two-level XMSS tree parallel construction scheme obtained in S401, deploys the fourth-level parallel scheme of the hash function, such as... Figure 1 As shown in the fourth level of parallelism, in the official parameter set, only the SHA256 hash function can use the fourth level of parallelism, allowing threads to execute WOTS in parallel. + The hash function for the public key can also be executed in parallel when building branch nodes. Other hash functions cannot be executed in parallel because the hashed messages are too short.

[0083] S502, Based on the parallel stages determined in S103 and the two-stage FORS parallel signature generation method obtained in S301, the fourth-stage parallel scheme for deploying the hash function is as follows: Figure 1 As shown in the fourth level of parallelism, threads can execute hash functions in parallel when concatenating the root node and when obtaining the branch node. The remaining hash functions cannot be parallelized because the hashed messages are too short.

[0084] S503, based on the parallel stages determined in S103 and the two-stage FORS parallel signature verification method obtained in S202, deploys the fourth-stage parallel scheme of the hash function, such as... Figure 1 As shown in the fourth level of parallelism, threads can execute hash functions in parallel when concatenating the root node and when obtaining the branch node. The remaining hash functions cannot be parallelized because the hashed messages are too short.

[0085] In another embodiment of the present invention, a parallel implementation system for the GPU quantum-resistant SPHINCS+ signature algorithm is provided. This system can be used to implement the above-mentioned parallel implementation method for the GPU quantum-resistant SPHINCS+ signature algorithm. Specifically, the parallel implementation system for the GPU quantum-resistant SPHINCS+ signature algorithm includes a design module, a first-level module, a second-level module, a third-level module, and an output module.

[0086] The design module, based on SPHINCS + The parameter set, GPU architecture information and internal structure design parallelization scheme include first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism and fourth-level hash function parallelism.

[0087] The first-level module, based on the four-level parallel scheme obtained from the design module, deploys the first-level inter-tree parallel scheme, resulting in the code for deploying the first-level parallel scheme, including the parallel schemes for FORS signature generation and FORS signature verification.

[0088] The second-level module, based on the four-level parallel scheme determined by the design module and the code of the first-level parallel scheme obtained by the first-level module, deploys the second-level inter-node parallel scheme to obtain the code of two-level parallelism, including the parallel construction scheme of XMSS tree and FORS tree.

[0089] The third-level module, based on the four-level parallel scheme determined by the design module and the two-level parallel code obtained from the second-level module, deploys the intra-node parallel scheme of the third-level module, resulting in three-level parallel code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + Parallel schemes for signature verification;

[0090] The output module, based on the four-level parallel scheme determined by the design module and the three-level parallel code obtained from the third-level module, deploys the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions executed in parallel.

[0091] In another embodiment of the present invention, a terminal device is provided, comprising a processor and a memory. The memory stores a computer program, the computer program including program instructions, and the processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to implement a corresponding method flow or corresponding function. The processor described in this embodiment of the present invention can be used for the operation of a parallel implementation method of the quantum attack-resistant SPHINCS+ signature algorithm on a GPU, including:

[0092] According to SPHINCS + The parameter set, GPU architecture information, and internal structure design are used to create a parallelization scheme. This scheme includes first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism. Based on the four-level parallelism scheme, the first-level inter-tree parallelism scheme is deployed, resulting in code for deploying the first-level parallelism scheme, including parallel schemes for FORS signature generation and FORS signature verification. Based on the code of the four-level parallelism scheme and the first-level parallelism scheme, the second-level inter-node parallelism scheme is deployed, resulting in two-level parallelism code, including parallel construction schemes for XMSS trees and FORS trees. Based on the four-level parallelism scheme and the two-level parallelism code, the third-level intra-node parallelism scheme is deployed, resulting in three-level parallelism code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + Parallel scheme for signature verification; based on the four-level parallel scheme and the three-level parallel code, deploy the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions executed in parallel.

[0093] In another embodiment of the present invention, a storage medium is also provided, specifically a computer-readable storage medium (memory). This computer-readable storage medium is a memory device in a terminal device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and extended storage media supported by the terminal device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by a processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device.

[0094] One or more instructions stored in a computer-readable storage medium can be loaded and executed by a processor to implement the corresponding steps of the parallel implementation method of the GPU-based quantum-resistant SPHINCS+ signature algorithm in the above embodiments; one or more instructions in the computer-readable storage medium are loaded and executed by the processor in the following steps:

[0095] According to SPHINCS + The parameter set, GPU architecture information, and internal structure design are used to create a parallelization scheme. This scheme includes first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism. Based on the four-level parallelism scheme, the first-level inter-tree parallelism scheme is deployed, resulting in code for deploying the first-level parallelism scheme, including parallel schemes for FORS signature generation and FORS signature verification. Based on the code of the four-level parallelism scheme and the first-level parallelism scheme, the second-level inter-node parallelism scheme is deployed, resulting in two-level parallelism code, including parallel construction schemes for XMSS trees and FORS trees. Based on the four-level parallelism scheme and the two-level parallelism code, the third-level intra-node parallelism scheme is deployed, resulting in three-level parallelism code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + Parallel scheme for signature verification; based on the four-level parallel scheme and the three-level parallel code, deploy the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions executed in parallel.

[0096] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0097] SPHINCS using the SHA256 hash function + Taking the SHA256-128s-robust parameter as an example: When running the official code, the time for generating the key pair, generating the signature, and verifying the signature on the GPU (GTX 3090) were 4088.57ms, 30782.05ms, and 32.77ms, respectively. After deploying this invention, the time for generating the key pair, generating the signature, and verifying the signature on the GPU (GTX 3090) were 0.24ms, 3.14ms, and 0.97ms, respectively.

[0098] In summary, this invention provides a parallel implementation method and system for the quantum-resistant SPHINCS+ signature algorithm for GPUs. Through a four-layer parallel strategy—including first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism—and combining multi-level parallel scheme decisions, a quantum-resistant SPHINCS signature algorithm for GPUs is obtained. + A parallel implementation method for the signature method is presented. Through the design of parallelization, deployment, and implementation modules, a quantum-resistant SPHINCS implementation for GPUs is derived. + A parallel implementation system for signature methods.

[0099] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0101] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0102] In the embodiments provided by this invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0103] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0104] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0105] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0106] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0108] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0109] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A parallel implementation method for the quantum-resistant SPHINCS+ signature algorithm on a GPU, characterized in that, Includes the following steps: S1, according to SPHINCS + The parameter set, GPU architecture information, and internal structure design are used to create a parallelization scheme. This scheme includes first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism, specifically: S101. Use a GPU architecture information collection tool to collect information on the number of GPU cores, including the number of multiprocessors, the number of cores on each multiprocessor, and the total number of cores; S102, via SPHINCS + The parameter set and the total number of GPU cores determined in step S101 determine the maximum parallelism; S103. Determine the number of parallel stages to be used based on the maximum parallelism and internal structure determined in step S102; S2. Based on the four-level parallel scheme obtained in step S1, deploy the first-level inter-tree parallel scheme to obtain the code for deploying the first-level parallel scheme, including the parallel schemes for FORS signature generation and FORS signature verification, specifically as follows: S201. Based on the number of parallel levels determined in step S1, deploy the first-level parallel scheme for generating key pairs into the FORS signature generation method to obtain the first-level parallel FORS parallel signature generation method. Multiple FORS trees are constructed independently and in parallel using multiple threads, and GPU synchronization technology is used at the end. S202. Based on the number of parallel levels determined in step S1, deploy the first-level parallel scheme for generating key pairs into the FORS signature verification method to obtain the first-level parallel FORS parallel signature verification method. Multiple threads are used to independently and in parallel authenticate multiple FORS trees, and GPU synchronization technology is used at the end. S3. Based on the four-level parallel scheme determined in step S1 and the code of the first-level parallel scheme obtained in step S2, deploy the second-level inter-node parallel scheme to obtain the code for two-level parallelism, including the parallel construction schemes of XMSS tree and FORS tree, specifically as follows: S301. Based on the number of parallel levels determined in step S1 and the first-level FORS parallel signature generation method obtained in step S2, deploy the second-level parallel scheme for FORS signature generation to obtain the two-level FORS parallel signature generation method of the first and second levels. Divide the threads into several groups and construct the FORS tree independently and in parallel with each group. S302. Deploy the second-level parallel scheme for parallel construction of XMSS tree according to the parallel level determined in step S1, and obtain the second-level parallel construction scheme for XMSS tree, and construct the XMSS tree in parallel with threads. S4. Based on the four-level parallel scheme determined in step S1 and the two-level parallel code obtained in step S3, deploy the third-level intra-node parallel scheme to obtain the three-level parallel code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + The parallel scheme for signature verification is as follows: S401. Deploy WOTS based on the parallel level determined in step S1 and the second-level XMSS tree parallel construction scheme obtained in step S3. + The third-level parallel scheme for key pair generation yields a two-level parallel XMSS tree construction algorithm for the second and third levels. S402. Deploy the third-level WOTS according to the number of parallel stages determined in step S1. + The signature generation scheme yields a third-level WOTS. + The parallel signature scheme allows threads to independently and in parallel complete multiple n-byte calculations; S403. Deploy the third-level WOTS according to the number of parallel stages determined in step S1. + The signature verification scheme yields a third-level WOTS. + The parallel signature verification scheme enables threads to independently and in parallel complete multiple n-byte calculations; S5. Based on the four-level parallel scheme determined in step S1 and the three-level parallel code obtained in step S4, deploy the fourth-level hash function parallel scheme, including the parallel scheme of all hash functions executed in parallel, specifically as follows: S501. Based on the parallel level determined in step S1 and the two-level XMSS tree parallel construction scheme obtained in step S4, deploy the fourth-level parallel scheme of the hash function so that the threads execute the hash function in parallel. S502. Based on the parallel level determined in step S1 and the two-level FORS parallel signature generation algorithm obtained in step S3, deploy the fourth-level parallel scheme of the hash function, so that the threads execute the hash function in parallel. S503. Based on the parallel level determined in step S1 and the two-level FORS parallel signature verification algorithm obtained in step S2, deploy the fourth-level parallel scheme of the hash function, so that the threads execute the hash function in parallel.

2. The parallel implementation method of the quantum-resistant SPHINCS+ signature algorithm for GPUs according to claim 1, characterized in that, In step S103, the parallel stages are deployed in a manner from low to high level.

3. The parallel implementation method of the quantum-resistant SPHINCS+ signature algorithm for GPUs according to claim 1, characterized in that, During the construction of FORS and XMSS trees, each thread processes the computation of one node independently, and performs GPU synchronization operations after the construction of one layer of nodes in the tree is completed.

4. The parallel implementation method of the quantum-resistant SPHINCS+ signature algorithm for GPUs according to claim 1, characterized in that, In step S401, the leaf nodes of the XMSS tree use WOTS. + Key pair generation, independent and parallel computation, each task is an n-byte computation, and threads independently and in parallel complete multiple n-byte computations.

5. A parallel implementation system for the quantum attack-resistant SPHINCS+ signature algorithm using a GPU, characterized in that, include: Design modules, based on SPHINCS + The parameter set, GPU architecture information, and internal structure design are used to create a parallelization scheme. This scheme includes first-level inter-tree parallelism, second-level inter-node parallelism, third-level intra-node parallelism, and fourth-level hash function parallelism, specifically: Use GPU architecture information gathering tools to collect information on the number of GPU cores, including the number of multiprocessors, the number of cores per multiprocessor, and the total number of cores; through SPHINCS + The maximum parallelism is determined by the parameter set and the total number of GPU cores; the number of parallelism stages to be used is determined by the determined maximum parallelism and internal structure. The first-level module, based on the four-level parallel scheme obtained from the design module, deploys the first-level inter-tree parallel scheme, resulting in the code for deploying the first-level parallel scheme, including the parallel schemes for FORS signature generation and FORS signature verification, specifically as follows: Based on the determined number of parallel levels, the first-level parallel scheme for generating key pairs is deployed into the FORS signature generation method, resulting in a first-level parallel FORS signature generation method. This method uses multiple threads to independently and in parallel construct multiple FORS trees, and employs GPU synchronization technology at the end. Similarly, based on the determined number of parallel levels, the first-level parallel scheme for generating key pairs is deployed into the FORS signature verification method, resulting in a first-level parallel FORS signature verification method. This method uses multiple threads to independently and in parallel authenticate multiple FORS trees, and employs GPU synchronization technology at the end. The second-level module, based on the four-level parallel scheme determined by the design module and the code of the first-level parallel scheme obtained from the first-level module, deploys the second-level inter-node parallel scheme, resulting in two-level parallel code, including the parallel construction schemes for XMSS trees and FORS trees, specifically: Based on the determined number of parallel levels and the obtained first-level FORS parallel signature generation method, the second-level parallel scheme for FORS signature generation is deployed, resulting in a two-level FORS parallel signature generation method. The threads are divided into several groups, and the FORS tree is constructed independently and in parallel by group. Based on the determined number of parallel levels, the second-level parallel scheme for XMSS tree parallel construction is deployed, resulting in a second-level XMSS tree parallel construction scheme, where threads construct the XMSS tree in parallel. The third-level module, based on the four-level parallel scheme determined by the design module and the two-level parallel code obtained from the second-level module, deploys the intra-node parallel scheme of the third-level module, resulting in three-level parallel code, including WOTS. + Key pair generation, WOTS + Signature generation and WOTS + The parallel scheme for signature verification is as follows: WOTS is deployed based on the determined number of parallel stages and the obtained second-level XMSS tree parallel construction scheme. + The third-level parallel scheme for key pair generation yields a two-level parallel XMSS tree construction algorithm for the second and third levels; the third-level WOTS is deployed according to the determined number of parallel levels. + The signature generation scheme yields a third-level WOTS. + The parallel signature scheme allows threads to independently and concurrently complete multiple n-byte computations; a third-level WOTS is deployed based on a determined number of parallel stages. + The signature verification scheme yields a third-level WOTS. + The parallel signature verification scheme enables threads to independently and in parallel complete multiple n-byte calculations; The output module, based on the four-level parallel scheme determined by the design module and the three-level parallel code obtained from the third-level module, deploys the fourth-level hash function parallel scheme, including the parallel schemes for all hash functions executed in parallel, specifically as follows: Based on the determined parallelism level and the obtained two-level XMSS tree parallel construction scheme, a fourth-level parallel scheme for deploying the hash function is implemented, enabling threads to execute the hash function in parallel; based on the determined parallelism level and the obtained two-level FORS parallel signature generation algorithm, a fourth-level parallel scheme for deploying the hash function is implemented, enabling threads to execute the hash function in parallel; based on the determined parallelism level and the obtained two-level FORS parallel signature verification algorithm, a fourth-level parallel scheme for deploying the hash function is implemented, enabling threads to execute the hash function in parallel.

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