Control device and camera device

Abstract

This invention relates to a control device and a camera device. The control device includes: a generation unit for generating a first synchronization signal and a second synchronization signal; and a control unit for controlling the generation unit. The control unit controls the generation unit such that a first synchronization signal for repeatedly reading out a first image signal to be sequentially displayed on a display and a second synchronization signal for displaying the first image signal on the display are output at a predetermined time difference. When the second image signal is read out at a timing corresponding to a shooting command between the readout of the first image signal and the readout of the second image signal, the first synchronization signal and the second synchronization signal are output at a predetermined time difference before and after the readout of the second image signal.

Description

[0001] (This application is a divisional application of the application filed on December 18, 2020, with application number 2020115038168, entitled "Control Device, Control Method, Camera Device, Camera System and Storage Medium".) Technical Field

[0002] This invention relates to a control device, control method, camera device, camera system, and storage medium, and more specifically to a technique for controlling the timing of image capture and the timing of image display. Background Technology

[0003] Some digital cameras and electronic devices with camera functions (hereinafter collectively referred to as "video equipment") have a Live View (LV) function. The LV function is a feature that captures moving images and displays the captured image (hereinafter referred to as "LV image") on a monitor in parallel. By using the displayed LV image as a viewfinder, users can find the ideal composition for still or moving image shooting while reviewing the LV image. In the following text, the operation of adjusting shooting conditions (e.g., changing zoom ratio, panning, tilting, etc.) to find the ideal composition is referred to as "framing".

[0004] For users to capture images according to their own intentions, the operability of the viewfinder is quite important. For example, if the time lag between capturing an LV image and displaying it on the monitor is long (display lag), the subject may have moved to a different location by the time the image is displayed on the monitor. Therefore, display lag greatly affects the operability of the viewfinder.

[0005] In camera devices that use the Live View (LV) function to capture still images, framing is impossible unless the LV images are continuously displayed on the monitor, even during continuous still image capture. However, when the capture and display of LV images occur between still image frames during continuous still image capture, it becomes difficult to adjust the timing of capturing each frame of the LV image if the interval between continuous still image captures is short. Therefore, during continuous still image capture, the time interval between the timing of capturing each frame of the LV image and the timing of updating the LV image on the monitor becomes longer, resulting in increased display lag and making framing difficult.

[0006] To address this issue, Japanese Patent Application Publication No. 2007-243615 discloses a method for reducing display lag by synchronously controlling the image capture timing of an image sensor and the display start timing of a display with a predetermined time difference.

[0007] However, in the conventional technology disclosed in Japanese Patent Application Publication No. 2007-243615, LV images become unnatural when the image capture operation is not performed at regular intervals. For example, when a still image is captured between frames of LV images captured at a constant period, the display period cannot remain constant at the timing of capturing the still image. Therefore, the user may perceive that the motion of the subject in the LV image is different from the actual motion of the subject. Furthermore, if the captured image is processed through different processing paths and therefore the display lag before the corresponding image is displayed on the monitor fluctuates, the timing of the subject moving in the LV image differs from the timing of the actual movement of the subject. In these cases, it is difficult to frame an image by viewing the LV image. Summary of the Invention

[0008] The present invention was achieved considering the above circumstances, and even during continuous shooting of still images, the present invention still performs real-time framing display with a short display lag, thereby improving the operability of framing.

[0009] According to the present invention, a control device is provided, comprising: a generation unit that generates a first synchronization signal for controlling the timing of readout of an image signal from an image sensor and a second synchronization signal for controlling the timing of displaying the readout image signal on a display; and a control unit that controls the generation unit, wherein the control unit controls the generation unit such that: the first synchronization signal for repeatedly reading out a first image signal to be sequentially displayed on the display and the second synchronization signal for displaying the first image signal on the display are output at a predetermined time difference; and, in the case that a second image signal is read out between readouts of the first image signal at a timing corresponding to a shooting command, the first synchronization signal and the second synchronization signal are output at the predetermined time difference before and after the readout of the second image signal; and wherein each unit is implemented by one or more processors, circuits, or combinations thereof.

[0010] Furthermore, according to the present invention, a camera device is provided, comprising: an image sensor, and a control device, the control device comprising: a generation unit that generates a first synchronization signal for controlling the timing of readout of an image signal from the image sensor and a second synchronization signal for controlling the timing of displaying the readout image signal on a display; and a control unit that controls the generation unit, wherein the control unit controls the generation unit such that: the first synchronization signal for repeatedly reading out a first image signal to be sequentially displayed on the display and the second synchronization signal for displaying the first image signal on the display are output at a predetermined time difference; and, in the case that a second image signal is read out between readouts of the first image signal at a timing corresponding to a shooting command, the first synchronization signal and the second synchronization signal are output at the predetermined time difference before and after the readout of the second image signal, and wherein each unit is implemented by one or more processors, circuits, or a combination thereof.

[0011] Furthermore, according to the present invention, a camera system is provided, comprising: a camera device including an image sensor; and a control device including: a generation unit that generates a first synchronization signal for controlling the timing of readout of an image signal from the image sensor and a second synchronization signal for controlling the timing of displaying the readout image signal on a display; a control unit that controls the generation unit; and a processing device connected to the control device and including a processing unit that processes the image signal output from the image sensor by synchronizing with the control device, wherein the control unit controls the generation unit such that: the first synchronization signal for repeatedly reading out a first image signal to be sequentially displayed on the display and the second synchronization signal for displaying the first image signal on the display are output at a predetermined time difference; and, in the case that a second image signal is read out between readouts of the first image signal at a timing corresponding to a shooting command, the first synchronization signal and the second synchronization signal are output at the predetermined time difference before and after the readout of the second image signal; and wherein each unit is implemented by one or more processors, circuits, or combinations thereof.

[0012] Furthermore, according to the present invention, a camera system is provided, comprising: a camera device including an image sensor; and a control device including: a generation unit that generates a first synchronization signal for controlling the timing of readout of an image signal from the image sensor and a second synchronization signal for controlling the timing of displaying the readout image signal on a display; a control unit that controls the generation unit; and a processing device connected to the control device and including a processing unit that processes the image signal output from the image sensor without synchronization with the control device, wherein the control unit controls the generation unit such that: the first synchronization signal for repeatedly reading out a first image signal to be sequentially displayed on the display and the second synchronization signal for displaying the first image signal on the display are output at a predetermined time difference; and, in the case that a second image signal is read out between readouts of the first image signal at a timing corresponding to a shooting command, the first synchronization signal and the second synchronization signal are output at the predetermined time difference before and after the readout of the second image signal; and wherein each unit is implemented by one or more processors, circuits, or combinations thereof.

[0013] Furthermore, according to the present invention, a control method is provided, comprising: generating a first synchronization signal for repeatedly reading from an image sensor a first image signal to be sequentially displayed on a display and a second synchronization signal for displaying the first image signal on the display; outputting the first synchronization signal and the second synchronization signal at a predetermined time difference; and, in the case that a second image signal is read from the image sensor at a timing corresponding to a shooting command between the readouts of the first image signal and the readout of the second image signal, outputting the first synchronization signal and the second synchronization signal at the predetermined time difference after the readout of the second image signal.

[0014] Furthermore, according to the present invention, a non-transitory computer-readable storage medium is provided, the storage medium storing a program executable by the computer, wherein the program includes program code for enabling the computer to function as a control processing device, the control processing device comprising: a generation unit that generates a first synchronization signal for controlling the timing of readout of an image signal from an image sensor and a second synchronization signal for controlling the timing of displaying the readout image signal on a display; and a control unit that controls the generation unit, wherein the control unit controls the generation unit such that: the first synchronization signal for repeatedly reading out a first image signal to be sequentially displayed on the display and the second synchronization signal for displaying the first image signal on the display are output at a predetermined time difference; and, in the case that a second image signal is read out between readouts of the first image signal at a timing corresponding to a shooting command, the first synchronization signal and the second synchronization signal are output at the predetermined time difference before and after the readout of the second image signal.

[0015] Other features of the invention will become apparent from the following description of exemplary embodiments (with reference to the accompanying drawings). Attached Figure Description

[0016] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0017] Figure 1 This is a block diagram illustrating the configuration of a camera device according to an embodiment of the present invention;

[0018] Figure 2A This is a circuit diagram of the pixels according to an embodiment;

[0019] Figure 2B This is a block diagram of an image sensor according to an embodiment;

[0020] Figure 3 This is a block diagram of a timing pulse generation circuit according to an embodiment;

[0021] Figure 4 This is a timing diagram illustrating the operation during continuous still image capture according to the first embodiment;

[0022] Figure 5 It is a timing diagram showing the operation during continuous still image capture according to the first variation;

[0023] Figure 6 It is a timing diagram showing the operation during continuous still image capture according to the second variation;

[0024] Figure 7This is a timing diagram illustrating the operation during continuous still image capture according to the second embodiment;

[0025] Figure 8 This is a block diagram illustrating the configuration of a camera system according to a third embodiment; and

[0026] Figure 9 This is a block diagram illustrating the configuration of a camera system according to a fourth embodiment. Detailed Implementation

[0027] In the following description, various embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention, nor do they limit the invention to combinations of all features described in the embodiments. Two or more of the multiple features described in the embodiments may be suitably combined. Furthermore, identical or similar configurations are given the same reference numerals, and repeated descriptions thereof are omitted.

[0028] <First Embodiment>

[0029] Figure 1 This is a block diagram illustrating the configuration of a camera device 1 according to a first embodiment of the present invention. Figure 1 In the imaging optical system 104, the first lens 100 is positioned at the front end. The aperture 101 is adjusted to control the amount of light during shooting. The second lens 102 and the third lens 103 are driven by the focusing actuator 120 and move back and forth along the optical axis to adjust the focus of the imaging optical system 104.

[0030] The focal plane shutter 105 has the function of adjusting the exposure time period when capturing still images. However, when the electronic shutter is used to adjust the exposure time period in slit-rolling reading, the focal plane shutter 105 is not used to adjust the exposure time period. The optical low-pass filter 106 is used to reduce false color and moiré fringes in the captured image.

[0031] The image sensor 107 photoelectrically converts the optical image of the subject formed by the camera optical system 104 into an electrical signal (image signal). In addition, the image sensor 107 has an electronic shutter function and can acquire image signals by slit scrolling.

[0032] The digital signal processor (DSP) 108 receives image signals from the image sensor 107 and performs image processing on them. In addition to image processing, the DSP 108 also calculates information to be used to drive the focusing lenses (second lens 102, third lens 103) based on the information from the image sensor 107.

[0033] Random Access Memory (RAM) 109 serves both to store image data processed by DSP 108 and to function as working memory during operation of Central Processing Unit (CPU) 110. Although this embodiment is configured to use RAM 109 to implement these functions, other types of memory can also be used, provided the access speed is sufficiently high and operation is not problematic. Furthermore, in this embodiment, RAM 109 is located externally to DSP 108 and CPU 110; however, some or all of its functions can be integrated into DSP 108 or CPU 110.

[0034] The CPU 110 executes programs for controlling each part of the camera device 1 and controls the overall operation of the camera device 1. The CPU 110 can control the reading of image signals from the image sensor 107 by making various settings on the image sensor 107. In addition, the CPU 110 communicates with the timing pulse generation circuit 111 and controls the timing of the generation of various timing pulses in order to control the operation of each module, as described later.

[0035] The timing pulse generation circuit 111 generates multiple synchronization signals based on the clock signal CLK1 from the first clock 112 and the clock signal CLK2 from the second clock 113, and provides these synchronization signals to the image sensor 107 and the display 114. The image sensor 107 performs image capture operations in sync with the signals from the timing pulse generation circuit 111.

[0036] Furthermore, the display 114 operates synchronously with signals from the timing pulse generation circuit 111 to update the displayed image. Additionally, the CPU 110 also has the function of using calculation results output from the DSP 108 to control the focusing actuator 120 to adjust the focus of the camera optical system 104.

[0037] The display 114 displays still and moving images processed by the DSP 108, menus, etc. By sequentially displaying frames of moving images (LV images) on the display 114 and using the display 114 as a viewfinder, the user can confirm the composition while framing the shot during both still and moving image capture. The display 114 may include multiple display devices, such as a rear display and an electronic viewfinder (EVF).

[0038] The operation unit 115 is equipped with operating components such as buttons and joysticks, and includes a still image capture button for instructing still image capture. Note that the operation unit 115 may not have operating components and may be configured to allow input of various commands via a touch panel. The user can control the CPU 110 through the operation unit 115, thereby capturing images.

[0039] When the CPU 110 detects that the user has pressed the still image capture button, the CPU 110 controls the capture of a still image after a specific time period, including the still image capture preparation period, has elapsed. Furthermore, if the still image capture button is pressed continuously after the start of still image capture, continuous still image captures are performed. It should be noted that reference... Figure 4 A timeline diagram is used to describe the detailed operations related to still image capture.

[0040] Recording medium 116 is configured to be removable, and still image data and moving image data are recorded on recording medium 116. Read-only memory (ROM) 117 stores the program used by CPU 110 to control the operation of each unit.

[0041] The shutter drive circuit 118 drives and controls the focal plane shutter 105. The focus drive circuit 119 controls the focus actuator 120 based on the output of the CPU 110, thereby driving the focusing lenses (second lens 102, third lens 103) back and forth along the optical axis to adjust the focus. The aperture drive circuit 121 controls the aperture actuator 122 to control the aperture 101.

[0042] Next, we will refer to Figure 2A and Figure 2B The configuration of the image sensor 107 in this embodiment will be described below.

[0043] Figure 2A This diagram shows the detailed circuit configuration of the pixels 206 of the image sensor 107. A photodiode (PD) 200 performs photoelectric conversion on the incident light and accumulates the resulting charge. A transfer switch 201 transfers the charge accumulated in the PD 200 to the floating diffuser (FD) 202 when the control signal φtx is set high (hereinafter referred to as "H").

[0044] Reset switch 203 resets FD 202 and is controlled by signal φres. Pixel reset operation is achieved by simultaneously setting signals φtx and φres to H to set PD 200 and FD 202 to the power supply voltage (VDD). Pixel amplifier transistor 204 is connected to constant current source 209 via selection switch 205 and vertical output line 208, described later. When the control signal φsel of selection switch 205 changes to H, pixel amplifier transistor 204 is connected to vertical output line 208. The charge transferred from PD 200 to FD 202 is then converted into a voltage value corresponding to the charge amount and output as an image signal to vertical output line 208.

[0045] Next, we will refer to Figure 2B To describe the circuit configuration of image sensor 107.

[0046] In pixel array 207, multiple pixels 206, numbering (m+1) pixels horizontally and (n+1) pixels vertically, are arranged in a matrix. Note that m and n are natural numbers. Based on the synchronization signal from timing pulse generation circuit 111, drive pulse generation circuit 210 to generate pulse signals for reset and read operations of pixel 206.

[0047] The generated pulse signal is provided to the pixel driving circuit 212. The row selection circuit 211 selects the row to be provided with the pulse signal generated by the driving pulse generation circuit 210, and sets the selected row in the pixel driving circuit 212. The pixel driving circuit 212 provides the pulse signal generated by the driving pulse generation circuit 210 to the row set by the row selection circuit 211 as the aforementioned control signal.

[0048] Based on the control signal provided from the pixel driving circuit 212, the image signal is output from the pixels in the selected row to the vertical output line 208. The constant current source 209 and the pixel amplifier transistor 204 are combined to form a source follower circuit.

[0049] The analog-to-digital converter (ADC) 213 converts the analog image signal output to the vertical output line 208 into a digital value corresponding to the signal level of the analog image signal. The image signal converted into a digital value by the ADC 213 is sequentially selected by the horizontal scanning circuit 214 and transferred to the output terminal 215, which outputs the image signal to the outside of the image sensor 107.

[0050] By changing the drive of the pixel array 207 by the row selection circuit 211, the image signal can be read out in a variety of different ways. For example, in this embodiment, as a readout method for generating a still image, after reading out the image signal from the pixels of the top row, the image signal is read out from the pixels of the next row, and the reading out of the image signal from the pixels of the next row is repeated until the image signal is read out from the pixels of the bottom row.

[0051] Furthermore, as a readout method for generating moving images, for example, after reading the image signal from the pixels of the top row, the image signal is repeatedly read from the pixels of every multiple rows (e.g., two rows) until the image signal is read from the pixels of the bottom row. If the image signal is read out in this way when generating moving images, although the vertical resolution of the image will degrade, a frame of image signal can be read out in a shorter time with lower power consumption. Besides the above, various readout methods can be used to read out image signals.

[0052] Note that in this embodiment, an example of the pixel driving circuit 212 and ADC 213 being built into the image sensor 107 has been described; however, these circuits may be located in a different chip than the image sensor 107.

[0053] Next, we will refer to Figure 3 The internal configuration of the timing pulse generation circuit 111 is described. In this embodiment, the timing pulse generation circuit 111 includes a reference synchronization signal generation circuit 300 (hereinafter referred to as "reference SSG"), a second synchronization signal generation circuit 301 (hereinafter referred to as "second SSG"), and a third synchronization signal generation circuit 302 (hereinafter referred to as "third SSG").

[0054] Reference SSG 300 and second SSG 301 are connected to CPU 110 and can record the assertion timing of each synchronization signal. Based on this timing, the time difference between the assertion timing of reference SSG 300 and second SSG 301 can be calculated. Furthermore, by controlling each of these circuits from CPU 110, synchronization signals of various periods can be generated, and the generation timing of these synchronization signals can be changed.

[0055] Furthermore, in this configuration, the second SSG 301 operates based on a clock signal CLK1 from the first clock 112, while the reference SSG 300 and the third SSG 302 operate based on a clock signal CLK2 from the second clock 113. The second SSG 301 then generates a second synchronization signal and outputs it to the image sensor 107 essentially within a predetermined first cycle, while the third SSG 302 generates a third synchronization signal and outputs it to the display 114 within the same first cycle.

[0056] This embodiment describes a configuration in which multiple clock inputs are fed into the timing pulse generation circuit 111 to generate two types of synchronization signals; however, the invention is not limited thereto. All SSGs can operate based on a single clock signal or on different clock signals. Furthermore, all or some of the aforementioned SSGs can be formed as independent blocks.

[0057] Figure 4 This is a timing diagram illustrating the still image capture operation in the first embodiment; the case of continuous shooting will be described here. In this embodiment, the still image to be recorded and the LV image to be used for LV display are read out using different reading methods. Figure 4 In the section on "Reset Scan or Readout Scan of Image Sensor," a dashed line indicates image signal readout for LV image generation, while a double dashed line indicates image signal readout for still image generation. Each dashed line represents a reset scan corresponding to each readout, with the vertical direction corresponding to a row of the image sensor 107 in the scanning direction. Furthermore, in... Figure 4 In the “Image Update Scan of the Display”, the diagonal solid lines represent the scan of the display 114 updating the LV display, and the vertical direction corresponds to the row of the display 114 in the scanning direction.

[0058] When the second synchronization signal is asserted at time t400, image signal readout for LV image generation begins. Then, when the third synchronization signal is asserted at time t401, the LV image generated based on the image signal already read out at time t400 begins to be displayed on display 114. Here, it is assumed that the captured image can be stably displayed by providing a time delay Δt1 from capture to display (which is the time difference between time t400 and time t401).

[0059] Subsequently, whenever the second synchronization signal is asserted, the image signal is read out from the image sensor, and whenever the third synchronization signal is asserted, the LV display is updated. A reset scan is performed at a time predetermined before the timing of the second synchronization signal assertion, prior to the readout of the image signal used for LV image generation. The timing of the reset scan can be determined based on the period of the second synchronization signal and the exposure time period.

[0060] Additionally, the third SSG 302 resets the value of its internal counter at the timing when the reference synchronization signal is asserted (as time t402). Thus, the third SSG 302 is synchronized with the synchronization signal from the reference SSG 300. Furthermore, the reference synchronization signal is also input to the CPU 110, and when the CPU 110 detects that the reference synchronization signal has been asserted, the CPU 110 reads a value from a counter representing the system time of the CPU 110 and records that count value.

[0061] At time t403 (which is the timing immediately following the assertion of the second synchronization signal after the assertion of the reference synchronization signal at time t402), image signal readout for LV image generation begins, and simultaneously, the second synchronization signal is input to CPU 110. CPU 110 then records a count value representing the system time at the time the second synchronization signal is asserted.

[0062] The CPU 110 calculates the assertion timing of the second synchronization signal based on the count values ​​of the reference synchronization signal and the second synchronization signal using calculations described later. Then, based on the calculation result, the timing pulse generation circuit 111 is controlled such that the second synchronization signal is asserted at a timing point where a fixed time has elapsed since the reference synchronization signal was asserted. Under this control, both the second and third synchronization signals can be operated based on the reference synchronization signal, thereby maintaining the time interval Δt1 between the second and third synchronization signals at a constant value.

[0063] When the still image capture button is pressed at time t404, indicating the start of capture, the timer used to manage the release delay begins operation. Simultaneously, preparations for capturing the still image, such as focusing and exposure control, are performed. Then, after a release delay T1 longer than the required capture preparation time, the second synchronization signal is asserted at time t405, and a reset scan of the still image begins. Then, after a charge accumulation period T2 has elapsed, the second synchronization signal is asserted again at time t407, and a scan for reading out the image signal used to generate the still image begins. At this time, the phase of the second synchronization signal changes.

[0064] Subsequently, at time t409, a reset scan for the LV image begins, and at time t410, a scan for reading out the corresponding image signal used to generate the LV image begins. Here, time t410, which is the start timing for reading out the image signal used to generate the LV image, can be calculated based on the still image capture button press timing, release delay T1, still image charge accumulation time period T2, and the still image signal reading out time period.

[0065] Here, time period T3 corresponds to the image update cycle of display 114, i.e., the first cycle. In this embodiment, these time periods T1, T2, and T3 can be determined at the timing point when the shooting button is pressed at time t404. Under this condition, at time t404, the assertion timing t406 of the reference synchronization signal and the assertion timing t410 of the second synchronization signal used to generate the image for LV image are fixed.

[0066] Therefore, the assertion timing of the third synchronization signal is changed at time t408, so that the third synchronization signal will be asserted at time t411 when the time difference from time t410 becomes Δt1, and thereafter, the assertion timing is maintained. To achieve this, the third synchronization signal is shifted relative to the reference synchronization signal. Here, the shift amount is adjusted to be equal to or less than the period of the third synchronization signal.

[0067] The difference between the assertion time t406 and time t411 of the reference synchronization signal is equal to or greater than the period of the third synchronization signal. Therefore, at time t408, the assertion timing of the third synchronization signal is shifted relative to the reference synchronization signal, and the shift amount is defined as Δu1. At this time, at time t404, the CPU 110 calculates the time difference Δu1 and sets the timing pulse generation circuit 111 to shift the assertion timing of the third synchronization signal by Δu1.

[0068] Based on this setting, the third synchronization signal is asserted at time t408. Therefore, when Δu1 has elapsed since the third SSG 302 received the reference synchronization signal, the third SSG 302 is set to reset the counter value. Subsequently, at a timing point delayed by a time difference Δu1 from the reference synchronization signal, the third synchronization signal is asserted.

[0069] Furthermore, the time difference T3 between the assertion time t410 of the second synchronization signal for reading the image signal used to generate the LV image and the assertion time t407 of the second synchronization signal for reading the still image immediately preceding time t410 is the same as the image update cycle of the display 114. Therefore, after time t407, control is performed such that the time difference Δu2 between the assertion timing of the reference synchronization signal and the assertion timing of the second synchronization signal is maintained. This difference Δu2 is the time difference between the assertion time t406 of the reference synchronization signal and the assertion time t407 of the second synchronization signal for reading the image signal used to generate the still image.

[0070] More specifically, the difference Δu2 between the time t406 when the reference synchronization signal is asserted and the time t407 when the second synchronization signal, used for still image generation, is asserted, is recorded as a target time difference value. Subsequently, at the timing points following the assertions of the reference and second synchronization signals, the time difference between the assertion timings is calculated, and the target time difference value Δu2 is subtracted from the calculated time difference. Therefore, this difference is the value used to correct the assertion timing of the second synchronization signal, and thus the assertion timing of the second synchronization signal is shifted to correct for this difference.

[0071] By operating in this manner, after time t407, a second synchronization signal can be asserted at a fixed period based on a reference synchronization signal having a phase difference corresponding to the target time difference value Δu2. Thus, after time t407, the reference synchronization signal, the second synchronization signal, and the third synchronization signal operate with reference to each other. As a result, image capture can be performed while maintaining a constant time difference Δt1 between the start time t410 of the image signal readout for LV image generation and the start time t411 of the image update scan of the display 114.

[0072] Thus, by altering the assertion timing of the second and third synchronization signals, a frame time interval with a phase shift and a different period is inserted into each of the second and third synchronization signals. As a result, the phase shift of the LV image update timing in display 114 (which begins at time t411) relative to the reference synchronization signal changes from the phase shift of the update timing immediately preceding the LV image update timing in display 114, but thereafter, the display delay of the LV image can be maintained as a time difference Δt1.

[0073] Furthermore, when capturing the first still image, a reset scan is performed based on the second synchronization signal. However, when capturing the second still image and subsequent still images, the timing for reading out the image signal used to generate the still image is adjusted to the first cycle of the second synchronization signal, and the reset scan is controlled so that it begins at the timing of the charge accumulation period required before the timing for reading out the image signal used to generate the still image. As a result, there is no need to reset the assertion timing of the second and third synchronization signals.

[0074] In this embodiment, the readout image signal used for still image generation is not used for LV display on display 114 for the following reasons. Generally, the optimal time period for displaying a still image since it was captured (referred to as Δt2) is different from the optimal time period for displaying an LV image since it was captured (Δt1 in this embodiment). Therefore, when attempting to display a still image on display 114, the motion of the subject is considered unnatural because the display lag is different from the display lag used to display LV image frames. However, it can be configured to display a still image.

[0075] Furthermore, in this embodiment, at time t412, the image signal readout for LV image generation at the update timing of display 114 is not performed. This is because, during continuous shooting, the image signal readout for still image generation (e.g., the readout starting at time t413) cannot be performed. This is also to maintain a constant LV image update rate during continuous still image shooting. At this time, the second SSG 301 is controlled to periodically discard the second synchronization signal. However, if the readout speed of the image signal from image sensor 107 is high enough, the LV image update rate can be increased, and the LV image can be updated at that update rate.

[0076] Furthermore, in this embodiment, the frame rate of the display 114 is reduced during continuous still image capture, but the invention is not limited thereto. For example, if the image signal readout speed is sufficiently high as described above, it can be achieved by... Figure 4 The period of the second synchronization signal is halved to control the update rate of the display 114 to be the same during continuous shooting of still images and during continuous shooting without still images. In this way, if the reading method of the image signal used for still image generation is different from the reading method of the image signal used for LV image generation, the reduction in the update rate of the display 114 during continuous shooting can be prevented.

[0077] As described above, according to the first embodiment, even during continuous shooting of still images, the display lag of LV images can be prevented from changing, which achieves better live view display.

[0078] Although the LV image is only used for display in this embodiment, it can also be recorded as a moving image on the recording medium 116. Using this configuration, both still and moving images can be captured simultaneously.

[0079] <First Variation>

[0080] Figure 5 A timing diagram is shown where the charge accumulation period in the second frame of a series of still images is longer than the update rate displayed by LV. Examples of variations in the length of the charge accumulation period during a series of still images include variations in photometric values ​​measured for each still image and exposure bracketing.

[0081] like Figure 5 As shown, when the charge accumulation period of the still image is longer than the update rate of the display 114, regardless of the value of the charge accumulation period of the still image, the interval between the image signal used for generating the LV image and the readout timing of the image signal used for generating the still image is controlled to be an integer multiple of the first cycle. By controlling it in this way, it may be unnecessary to readjust the update timing of the LV image on the display 114. Here, reference will be made to... Figure 5 The timing diagrams in the document describe the specific control methods. Note that the details already referenced will not be repeated. Figure 4 The timing is described in the timing diagram.

[0082] After the first still image is captured, a reset scan of the still image begins at time t501, a predetermined time has elapsed since the second synchronization signal was asserted at time t500. Furthermore, as described above, the charge accumulation period of the second still image is longer than the time period from time t500 to time t502, i.e., the first cycle. It is assumed that the charge accumulation period is determined by the start time of the reset scan.

[0083] First, time t503 (i.e., the assertion timing of the second synchronization signal immediately following the charge accumulation period since the reading of the image signal used for generating the second still image began at time t500) is determined as the start timing for reading the image signal used for generating the second still image. Then, time t501 is determined by counting down the charge accumulation period from time t503. Figure 5 In the example timing diagram shown, the LV image is not read out at the timing asserted at time t502 of the second synchronization signal.

[0084] At time t503, the image signal for still image generation corresponding to the reset scan that begins at time t501 is read out. Then, at the timing asserted by the second synchronization signal at time t504, the image signal for LV image generation is read out. Thus, since the time difference Δt1 between the reading timing of the image signal for LV image generation at time t504 and the update timing of the display 114 at time t505 can be maintained, the display lag can be controlled to maintain... Figure 4 The time difference Δt1 is shown in the timing diagram.

[0085] As described above, according to the first variant, the charge accumulation period of a still image can be controlled without frequently adjusting the assertion timing of the reference synchronization signal and the third synchronization signal.

[0086] <Second Variation>

[0087] exist Figure 4 In the timing diagram, when the still image capture button is pressed at time t404, the release delay T1, the charge accumulation period of the still image T2, and the readout time T3 for the image signal used to generate the still image are determined. However, other situations may actually exist.

[0088] For example, in the release lag T1, the charge accumulation period during shooting preparation can be defined as part of exposure control. In this case, when in Figure 6 When the still image capture button is pressed at time t600, the charge accumulation time period T2 of the still image is not fixed, and it is not possible to perform actions such as... Figure 4 The timing adjustment is described in the timing diagram. Therefore, in the second variation, the case where the charge accumulation period T2 is determined at time t601 will be described.

[0089] The reference synchronization signal is asserted at time t602, and the second synchronization signal is asserted at time t603. At this time, with the aid of the reference... Figure 4 The timing diagram describes a method for controlling the assertion timing of the second synchronization signal. However, if it takes time to change the assertion timing of the third synchronization signal, then it cannot be achieved by using a reference. Figure 4 The timing diagram describes a method for controlling the assertion timing of the third synchronization signal.

[0090] In this scenario, the image update scan of display 114 is paused for a period of time and then resumes at a timing point where the assertion timing of the next synchronization signal can be controlled. For example, considering the timing before and after the next still image capture, a reference synchronization signal is asserted at time t604, and then a second synchronization signal is asserted at time t605. The assertion timing of the second synchronization signal is controlled to maintain a time difference Δu2 with the assertion timing t604 of the reference synchronization signal, as described above.

[0091] At this point, it should be configured such that the third synchronization signal is asserted at time t606, which is Δt1 after the second synchronization signal has been asserted at time t605. To achieve this, the time difference Δu1 between the assertion timings of the reference synchronization signal and the third synchronization signal at time t606 can be calculated and set to the timing pulse generation circuit 111. This time difference Δu1 can be calculated when the charge accumulation time T2 at time t601 is fixed.

[0092] Therefore, at time t601, CPU 110 calculates the time difference Δu1 and sets the timing pulse generation circuit 111 so that the assertion timing of the third synchronization signal is shifted according to the time difference Δu1. Based on this setting, the third synchronization signal is asserted at time t606. Therefore, when Δu1 has elapsed since the third SSG 302 received the reference synchronization signal, the third SSG 302 is set to the reset counter value.

[0093] <Second Embodiment>

[0094] The second embodiment of the present invention will now be described.

[0095] In the first embodiment, to reduce power consumption, different readout methods are used to perform the readout of image signals for still image generation and for LV image generation. However, this not only complicates the processing but also leads to a reduction in the display frame rate. Therefore, in the second embodiment, a method for suppressing the reduction in display frame rate will be described by using the readout image signals for still image generation for LV display during continuous still image capture.

[0096] Figure 7 This is a timing diagram illustrating the still image capture operation in the second embodiment. The method for reading out the LV image before pressing the still image capture button may or may not be the same as the method for reading out the still image; however, from the perspective of the time difference between readout and display and power saving, the method for reading out the LV image is different from the method for reading out the still image. It should be noted that... Figure 7 In Chinese, various types of line representations and references Figure 4The same content as described in the first embodiment will not be repeated here. Furthermore, the operation before pressing the still image capture button is the same as... Figure 4 The operations shown in the timing diagram are the same, so they will not be described again.

[0097] When the still image capture button is pressed at time t700, preparations for capturing a still image are made, such as focusing and exposure control. Then, at time t701, after the release delay T1 has elapsed, the second synchronization signal is asserted, and the reset scan for the still image begins. After the predetermined charge accumulation period T2 has elapsed, at time t702, the second synchronization signal is asserted again, and the readout scan for the image signal used to generate the still image begins. Thereafter, the second synchronization signal is asserted at the same first cycle as before the still image capture.

[0098] In this embodiment, the captured still image is displayed on the display 114. Here, the optimal time difference for displaying the read still image on the display 114 is set to Δt2. At this time, the time from the assertion timing t702 of the second synchronization signal to the assertion timing t704 of the immediately following third synchronization signal is controlled to Δt2.

[0099] More specifically, at the time t700 when the still image capture button is pressed, the release delay T1 and the charge accumulation period T2 are fixed, thereby determining the time t702 at which the image signal for still image generation begins to be read out. Therefore, it can be determined at this time that a time difference Δt2 has elapsed since t702, at time t704. To use this information to assert the third synchronization signal at that time, the assertion timing of the third synchronization signal can be changed from t703, when the reference synchronization signal is asserted, by a time difference Δu2.

[0100] The CPU 110 performs calculations to obtain the time difference Δu2 and changes the settings of the timing pulse generation circuit 111 at time t700. Then, the assertion timing of the third synchronization signal changes from time t703 to time t704, which is changed by the time difference Δu2.

[0101] Since the still image capture button is still pressed, when a period equal to the update rate of the display 114 has elapsed since the first still image was captured at time t702, the image signal for generating the second still image is read out at time t705. The read image is then used as the LV image on the display 114, and when a time difference Δt2 has elapsed since time t705, the LV image is updated at time t706.

[0102] By controlling the various timings described above, continuous shooting of still images can be performed even during continuous shooting without reducing the display rate of the display 114.

[0103] In this embodiment, the still image capture cycle and the display 114 update cycle are controlled to be the same. However, this control is not always necessary; the still image capture cycle can be 1 / an integer of the display 114 update cycle. By controlling it in this way, the continuous still image capture cycle can be set to exceed the display 114 update rate.

[0104] Conversely, it is not necessary to record all captured still images. To reduce power consumption and processing load, not all captured still images can be recorded; instead, captured still images can be selectively discarded and recorded at intervals.

[0105] Furthermore, even when using the readout image signal used to generate still images to perform various calculations for automatic exposure (AE) and automatic focus (AF), similar to recording, it is possible that not all captured still images are calculated, and that captured still images can be periodically culled and calculated.

[0106] <Third Embodiment>

[0107] The third embodiment of the present invention will now be described.

[0108] Figure 8 This is a block diagram illustrating the configuration of a camera system according to a third embodiment. Figure 1 The same components shown are indicated by the same reference numerals and will not be described again. In this embodiment, by connecting the external device 700 to a device having Figure 1 The camera device 1 and the external device 700 are configured as shown, and can operate as a single unit. In this embodiment, an example of such a configuration will be described, wherein a synchronization signal is input to the external device 700 to maintain synchronization between the external device 700 and the camera device 1.

[0109] The second CPU 701 is integrated into the external device 700 and is connected to the CPU 110, exchanging information via communication. The second CPU 701 configures the second timing pulse generation circuit 702, which operates based on a third clock signal CLK3 output from the third clock 703. The second timing pulse generation circuit 702 receives a reference synchronization signal output from the timing pulse generation circuit 111. The second timing pulse generation circuit 702 includes a fourth synchronization signal generation circuit 704 (hereinafter referred to as the "fourth SSG"). The reference synchronization signal output from the timing pulse generation circuit 111 and the third clock signal CLK3 output from the third clock 703 are then input to the fourth SSG 704.

[0110] Similar to the third SSG 302, the fourth SSG 704 has the following function: when a reference synchronization signal output from the timing pulse generation circuit 111 is received, the counter is reset after a predetermined time has elapsed since the reference synchronization signal was received. This predetermined time includes 0. Therefore, it can be configured according to the reference synchronization signal in the first embodiment. Figure 4 The timing diagram describes changing the assertion timing of the third synchronization signal in exactly the same way as changing the assertion timing of the fourth synchronization signal from the fourth SSG 704. By using this function, the external device 700 can operate in synchronization with the capture of LV images, even during continuous still image capture.

[0111] Functional unit 705 operates based on timing pulses from the second timing pulse generation circuit 702 and settings made by the second CPU 701. Here, the function of functional unit 705 is not limited to a specific function. For example, various devices are conceivable, such as a time recorder for recording operation time, a microphone for recording voice, an illumination device for adjusting light intensity, a recording device for recording video, and a display device for displaying captured images. Other devices different from these can be used. Furthermore, to implement various functions, functional unit 705 can be divided into several blocks.

[0112] As described above, according to the third embodiment, by controlling the fourth SSG 704 included in the external device 700 connected to the camera device 1, the operating timing of the external device 700 can be stably controlled relative to the timing of image capture. By operating the external device in this way, the operating timing of the external device can be changed so that the operating timing of the external device is optimal relative to the timing of image acquisition.

[0113] <Fourth Embodiment>

[0114] The fourth embodiment of the present invention will now be described.

[0115] Figure 9 This is a block diagram illustrating the configuration of a camera system according to a fourth embodiment. Figure 1 The same components shown are indicated by the same reference numerals and will not be described again. In this embodiment, by connecting the external display device 800 to a device having Figure 1 The camera device 1 and the external display device 800 in the illustrated configuration can operate as a single unit. In this embodiment, an example of a simpler configuration is shown where a synchronization signal is not input to the external display device 800, within such a single-unit operation configuration.

[0116] The third CPU 801 is integrated into the external display device 800, and is connected to the CPU 110 and exchanges information via communication. The third CPU 801 configures the third timing pulse generation circuit 802, which operates based on the fourth clock signal CLK4 output from the fourth clock 803. The third timing pulse generation circuit 802 includes a fifth synchronization signal generation circuit 804 (hereinafter referred to as the "fifth SSG"), and inputs the fourth clock signal CLK4 output from the fourth clock 803 to the fifth SSG 804. Since the fifth SSG 804 does not accept the synchronization signal asserted by the reference SSG 300, the timing of the synchronization signal asserted by the fifth SSG 804 cannot be synchronized with the timing of the synchronization signal asserted by the reference SSG 300.

[0117] The second display 805 displays the image read from the image sensor 107 based on the synchronization signal asserted by the fifth SSG 804 and the settings made by the third CPU 801. In this configuration, since the timing of the synchronization signal asserted by the fifth SSG 804 is independent of the timing of pressing the still image capture button, the timing of displaying the image is also independent of the timing of the still image capture start command being notified.

[0118] At this time, although the timing of displaying the image on the external display device 800 is independent of the still image capture start command, the display lag in the display 114 is reduced by performing the operation described in the first embodiment.

[0119] As described above, the method described in this embodiment can reduce the number of connection signal lines between the camera device 1 and the external display device 800. Therefore, display lag in the viewfinder directly viewed by the photographer can be reduced, while simultaneously displaying the image on another external monitor or similar device via a simplified system.

[0120] Other embodiments

[0121] This invention can be applied to systems comprising multiple devices or devices comprising a single device.

[0122] The embodiments of the present invention can also be implemented by providing software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads and executes the program.

[0123] Although the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A control device, comprising: The generation unit generates a first synchronization signal to be provided to the image sensor to control the readout timing of the image signal from the image sensor, and a second synchronization signal to be provided to the display to control the timing of the display of an image based on the readout image signal on the display. as well as The control unit controls the generating unit. The control unit controls the generating unit such that: The first synchronization signal is repeatedly generated to read out the first image signal of each frame from the image sensor, and the second synchronization signal is repeatedly generated to sequentially display images based on the first image signal on the display, wherein the first synchronization signal and the second synchronization signal are generated with a predetermined time difference. When a shooting command is given by the user and a second image signal is read from the image sensor at a timing corresponding to the shooting command between the readout of the first image signal of the frame, a predetermined time difference between the first synchronization signal and the second synchronization signal is maintained before and after the readout of the second image signal by changing the output timing of the first synchronization signal and the second synchronization signal based on the preparation time period for acquiring the second image signal and the charge accumulation time period of the second image signal.

2. The control device according to claim 1, wherein, The generation unit generates the first synchronization signal and the second synchronization signal based on a reference synchronization signal with a first period, and The control unit indicates to the generating unit the time difference of the output timing of the first synchronization signal relative to the reference synchronization signal, and the time difference of the output timing of the second synchronization signal relative to the reference synchronization signal.

3. The control device according to claim 1, wherein, Without the shooting command given, the generating unit repeatedly generates the first synchronization signal and the second synchronization signal in a second cycle, and When the second image signal is repeatedly read out, the control unit controls the generation unit to change the second readout timing and subsequent readout timing of the second image signal to an integer multiple of the second period starting from the first readout timing of the second image signal.

4. The control device according to claim 1, wherein, The generating unit generates the second synchronization signal in a second cycle, and If the second image signal can be read within the second cycle, the second image signal is displayed on the display.

5. The control device according to claim 4, wherein, The first image signal and the second image signal are read from the image sensor using the same readout method.

6. The control device according to claim 4, wherein, The second image signal is read from the image sensor using a readout method that takes longer than the readout method used to read out the first image signal. When a shooting command is given, the control unit controls the generating unit to shift the timing of the output of the second synchronization signal in a manner with a second time difference, the second time difference being longer than the time difference during which the second image signal is displayed on the display.

7. The control device according to claim 1, wherein, The first image signal is the image signal of a moving image.

8. A control device, comprising: The generation unit generates a first synchronization signal to be provided to the image sensor to control the readout timing of the image signal from the image sensor, and a second synchronization signal to be provided to the display to control the timing of the display of an image based on the readout image signal on the display. as well as The control unit controls the generating unit. The control unit controls the generating unit such that: The first synchronization signal is repeatedly generated to read out the first image signal of each frame from the image sensor, and the second synchronization signal is repeatedly generated to sequentially display images based on the first image signal on the display, wherein the first synchronization signal and the second synchronization signal are generated with a predetermined time difference. When a shooting command is given by the user and the charge of the second image signal of the frame to be read from the image sensor is accumulated at a time point after a predetermined time period has elapsed since the shooting command was given, the first synchronization signal and the second synchronization signal are generated with the predetermined time difference when the output timing of the first synchronization signal and the second synchronization signal is changed based on the timing of the shooting command to read the first image signal after the second image signal is read.

9. The control device according to claim 8, wherein, The generation unit generates the first synchronization signal and the second synchronization signal based on a reference synchronization signal with a first period, and The control unit indicates to the generating unit the time difference of the output timing of the first synchronization signal relative to the reference synchronization signal, and the time difference of the output timing of the second synchronization signal relative to the reference synchronization signal.

10. The control device according to claim 8, wherein, Without the shooting command given, the generating unit repeatedly generates the first synchronization signal and the second synchronization signal in a second cycle, and When the second image signal is repeatedly read out, the control unit controls the generation unit to change the second readout timing and subsequent readout timing of the second image signal to an integer multiple of the second period starting from the first readout timing of the second image signal.

11. The control device according to claim 8, wherein, The generating unit generates the second synchronization signal in a second cycle, and If the second image signal can be read within the second cycle, the second image signal is displayed on the display.

12. The control device according to claim 11, wherein, The first image signal and the second image signal are read from the image sensor using the same readout method.

13. The control device according to claim 11, wherein, The second image signal is read from the image sensor using a readout method that takes longer than the readout method used to read out the first image signal. When the shooting command is given, the control unit controls the generating unit to shift the timing of the output of the second synchronization signal in a manner with a second time difference, the second time difference being longer than the time difference during which the second image signal is displayed on the display.

14. The control device according to claim 8, wherein, The first image signal is the image signal of a moving image.

15. A camera device, comprising: Image sensor; as well as Control device, comprising: A generation unit generates a first synchronization signal to be provided to the image sensor to control the readout timing of an image signal from the image sensor, and a second synchronization signal to be provided to the display to control the timing of displaying an image based on the readout image signal on the display; and The control unit controls the generating unit. The control unit controls the generating unit such that: The first synchronization signal is repeatedly generated to read out the first image signal of each frame from the image sensor, and the second synchronization signal is repeatedly generated to sequentially display images based on the first image signal on the display, wherein the first synchronization signal and the second synchronization signal are generated with a predetermined time difference. When a shooting command is given by the user and a second image signal is read from the image sensor at a timing corresponding to the shooting command between the readout of the first image signal of the frame, a predetermined time difference between the first synchronization signal and the second synchronization signal is maintained before and after the readout of the second image signal by changing the output timing of the first synchronization signal and the second synchronization signal based on the preparation time period for acquiring the second image signal and the charge accumulation time period of the second image signal.

16. A camera device, comprising: Image sensor; as well as Control device, comprising: A generation unit generates a first synchronization signal to be provided to the image sensor to control the readout timing of an image signal from the image sensor, and a second synchronization signal to be provided to the display to control the timing of displaying an image based on the readout image signal on the display; and The control unit controls the generating unit. The control unit controls the generating unit such that: The first synchronization signal is repeatedly generated to read out the first image signal of each frame from the image sensor, and the second synchronization signal is repeatedly generated to sequentially display images based on the first image signal on the display, wherein the first synchronization signal and the second synchronization signal are generated with a predetermined time difference. When a shooting command is given by the user and the charge of the second image signal of the frame to be read from the image sensor is accumulated at a time point after a predetermined time period has elapsed since the shooting command was given, the first synchronization signal and the second synchronization signal are generated with the predetermined time difference when the output timing of the first synchronization signal and the second synchronization signal is changed based on the timing of the shooting command to read the first image signal after the second image signal is read.

Images