Select module, pixel row selection module and pixel readout circuit

Abstract

This invention provides a selection module, a pixel row selection module, and a pixel readout circuit, comprising: a set of multi-row selection units, each multi-row selection unit including multiple AND gates, the input of each AND gate being connected to a corresponding address signal, and the output of each AND gate outputting a row selection signal in the pixel array; the AND gates in the multi-row selection unit...<n:m+1> Each bit address receives its corresponding / rs_add<n:m+1> Each and every door <m:0>Each bit address receives its corresponding rs_addb <m:0>Furthermore, in the same group of multi-row selection cells, each AND gate sequentially converts rs_addb from least significant bit to most significant bit according to binary. <m:0>Replace with rs_add <m:0>The corresponding bits; where / rs_add<n:m+1> For rs_add<n:m+1> The inverted signal is used, where m and n are both natural numbers, and m is less than n. This invention enables simultaneous selection of multiple rows, greatly improving the readout speed of the pixel array and thus increasing the frame rate of the image sensor.< / m:0>

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a selection module, a pixel row selection module, and a pixel readout circuit. Background Technology

[0002] In image sensors, pixel array signals are typically read out row by row. The row driving circuit selects a specific row of the pixel array using a row selection signal, then controls the reset and readout of the pixel signals in that row using reset and transmission signals. Finally, the voltage signal of that row is converted into a digital signal by a column-level ADC for further processing. The readout speed of the pixel array signals directly affects the frame rate of the image sensor. Due to the millions or tens of millions of pixels and the row-by-row readout characteristic, improving the frame rate has always been a challenge.

[0003] Therefore, how to improve the frame rate of image sensors has become one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a selection module, a pixel row selection module, and a pixel readout circuit to solve the problem of low frame rate of image sensors in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a selection module based on a single-row readout architecture for pixel array signals, wherein the selection module includes at least:

[0006] A set of multi-row selection row selection units, wherein the multi-row selection row selection unit includes multiple AND gates, the input of each AND gate is connected to the corresponding address signal, and the output of each AND gate outputs the row selection signal in the pixel array respectively;

[0007] Each AND gate in the multi-row selection row selection unit<n:m+1> Each bit address receives its corresponding first address signal / rs_add<n:m+1> Each and every door <m:0>Each bit address receives its corresponding second address signal rs_addb <m:0>Furthermore, in the same group of multi-row selection cells, each AND gate sequentially converts the second address signal rs_addb from the least significant bit to the most significant bit in binary order. <m:0>Replace with the third address signal rs_add <m:0>The corresponding bit;

[0008] Among them, the first address signal / rs_add<n:m+1> For the third address signal rs_add<n:m+1> The inverted signal of , where m and n are both natural numbers, and m is less than n.

[0009] Optionally, the multi-row selection row selection unit includes 2*2 m In the multi-row selection row selection unit, the second address signal rs_addb is an AND gate. <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0>=11……11, to achieve 2*2 m Select all rows at the same time.

[0010] Optionally, the multi-row selection row selection unit includes 2*2 m In the AND gate, the second address signal rs_addb in the multi-row selection row selection unit... <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0>=11……101, used to select every two even-numbered rows.

[0011] Optionally, the multi-row selection row selection unit includes 2*2 m In the AND gate, the second address signal rs_addb in the multi-row selection row selection unit... <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0>=11……10, used to select even-numbered rows.

[0012] Optionally, the multi-row selection row selection unit includes 2*2 m In the AND gate, the second address signal rs_addb in the multi-row selection row selection unit... <m:0>=11……101, rs_add in the third address signal<n:m+1> =00……00、rs_add <m:0>=11……11 is used to select every two odd-numbered rows.

[0013] Optionally, the multi-row selection row selection unit includes 2*2 m In the AND gate, the second address signal rs_addb in the multi-row selection row selection unit... <m:0>=11……10, rs_add in the third address signal<n:m+1> =00……00、rs_add <m:0>=11……11, used to select odd-numbered rows.

[0014] Optionally, the multi-row selection row selection unit includes 3*2 m Each AND gate, after removing the last two bits, is connected to rs_add. <1> and rs_add <0> The address combination; and set the second address signal rs_addb <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0>=11……11, to achieve 3*2 m Select all rows at the same time.

[0015] Alternatively, the selection module includes nm groups of multi-row selection units, each of which includes the same number of AND gates, and the input of each AND gate is connected to the corresponding address signal, and the output of each AND gate outputs the row selection signal in the pixel array respectively.

[0016] Among them, the first address signal of the m+N-1th bit of the row selection unit in the Nth group of multi-row selection is / rs_add<m+N-1> Replace with the third address signal rs_add<m+N-1> And N is a positive integer ≤ nm.

[0017] More optionally, the selected module includes 2*2 n-m -1 group of multi-row selection row selection units, each of the multi-row selection row selection units includes the same number of AND gates, and the input of each AND gate is connected to the corresponding address signal, and the output of each row selection signal in the pixel array is output respectively;

[0018] In this process, the row selection units in each group of multi-row selections sequentially convert the second address signal / rs_add from the least significant bit to the most significant bit in binary order.<n:m+1> Replace with the third address signal rs_add<n:m+1> The corresponding bit.

[0019] To achieve the above and other related objectives, the present invention also provides a pixel row selection module, the pixel row selection module comprising at least:

[0020] The first selection module, consisting of the first AND logic unit, the second AND logic unit, the OR gate, the selection module formed by simultaneously selecting the above even-numbered rows, and the above 3*2 m A second selection module is formed by selecting the selected modules simultaneously in the same row;

[0021] The first logic unit receives an address signal and a first enable signal at its input terminal, and its output terminal is connected to the input terminal of the first selected module. When the first enable signal is valid, it provides an address signal to the first selected module.

[0022] The input terminals of the second logic unit receive an address signal and a second enable signal, respectively, and the output terminal is connected to the input terminal of the second selected module. When the second enable signal is valid, it provides an address signal to the second selected module.

[0023] The first input of the OR gate is connected to the output of the first selected module, and the second input is connected to the output of the second selected module, outputting the row selection signal of the pixel array.

[0024] To achieve the above and other related objectives, the present invention also provides a pixel readout circuit, the pixel readout circuit comprising at least:

[0025] The system comprises a pixel array, a readout module, and the aforementioned selection module; the selection module provides row selection signals for the pixel array; and the readout module receives column readout signals from the pixel array.

[0026] To achieve the above and other related objectives, the present invention also provides a pixel readout circuit, the pixel readout circuit comprising at least:

[0027] The pixel array, the readout module, and the aforementioned pixel row selection module; the pixel row selection module provides row selection signals for the pixel array; the readout module receives column readout signals from the pixel array.

[0028] As described above, the selection module, pixel row selection module, and pixel readout circuit of the present invention have the following beneficial effects:

[0029] 1. The selection module, pixel row selection module and pixel readout circuit of the present invention can realize the simultaneous selection of multiple rows, which greatly improves the readout speed of the pixel array and thus improves the frame rate of the image sensor.

[0030] 2. The selection module, pixel row selection module, and pixel readout circuit of this invention can achieve 2*2 M row or 3*2 m It can select rows simultaneously, and achieve the purpose of selecting different numbers of rows at the same time by setting different address signals, which is highly flexible and universal. Attached Figure Description

[0031] Figure 1 The diagram shown is a circuit structure diagram of a selected module of the present invention.

[0032] Figure 2 This is a schematic diagram of another circuit structure for the selected module of the present invention.

[0033] Figure 3 This is a schematic diagram of another circuit structure for the selected module of the present invention.

[0034] Figure 4 The diagram shown is a schematic diagram of the circuit structure of the pixel row selection module of the present invention.

[0035] Figure 5 This is shown as an example of the pixel row selection module of the present invention.

[0036] Figure 6 The diagram shown is a schematic representation of one possible structure of the pixel readout circuit of the present invention.

[0037] Figure 7 The diagram shown illustrates another structural design of the pixel readout circuit of the present invention.

[0038] Component designation explanation

[0039] 1-Pixel row selection module; 11-First AND logic unit; 12-Second AND logic unit; 13-OR gate; 14-First selection module; 15-Second selection module; 2-Pixel array; 3-Readout module; 4-Selection module; 5-Pixel row selection module. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figures 1-7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. Example 1

[0042] like Figure 1 As shown, this embodiment provides a selection module based on a single-row readout architecture for pixel array signals. The selection module includes:

[0043] A set of multi-row selection row selection units, wherein the multi-row selection row selection unit includes multiple AND gates, the input of each AND gate is connected to the corresponding address signal, and the output of each AND gate outputs the row selection signal in the pixel array respectively;

[0044] Each AND gate in the multi-row selection row selection unit<n:m+1> Each bit address receives its corresponding first address signal / rs_add<n:m+1> Each and every door <m:0>Each bit address receives its corresponding second address signal rs_addb <m:0>Furthermore, in the same group of multi-row selection cells, each AND gate sequentially converts the second address signal rs_addb from the least significant bit to the most significant bit in binary order. <m:0>Replace with the third address signal rs_add <m:0>The corresponding bit;

[0045] Among them, the first address signal / rs_add<n:m+1> For the third address signal rs_add<n:m+1> The inverted signal of , where m and n are both natural numbers, and m is less than n.

[0046] Specifically, the multi-row selection row selection unit includes 2*2 m Each AND gate outputs a 2x2 pixel array. m Each row selection signal is denoted as rowsel. <0> rowsel <1> ...rowsel<2*2 m -2>、rowsel<2*2 m -1>. Each AND gate's input terminals include... <n:0>Bit address. Each AND gate's<n:m+1> Each bit address receives the corresponding first address signal / rs_add<n:m+1> Each and every door <m:0>The bit address is sequentially processed from least significant bit to most significant bit in binary format, with the second address signal rs_addb... <m:0>Replace with the third address signal rs_add <m:0>The corresponding bits; where the first AND gate corresponds to binary 000...000, does not change the input address signal, therefore, the first AND gate's <m:0>The bit address receives the corresponding second address signal rs_addb <m:0>The second AND gate corresponds to binary 000...001, changing the 0th bit of the address signal. Therefore, the second AND gate... <m:1>The bit address receives the corresponding second address signal rs_addb <m:1>The second AND gate <0> The bit address receives the corresponding third address signal rs_add <0> Correspondingly, the third AND gate corresponds to binary 000...010, changing the first address bit signal. Therefore, the third AND gate... <m:2>and <0> The bit address receives the corresponding second address signal rs_addb <m:2>and rs_addb <0> The third AND gate <1> The bit address receives the corresponding third address signal rs_add <1> The fourth AND gate corresponds to binary 000...011, changing the 1st and 0th address bits. Therefore, the fourth AND gate... <m:2>The bit address receives the corresponding second address signal rs_addb <m:2>The <1:0> bit address of the fourth AND gate receives the corresponding third address signal rs_add<1:0>; and so on, the 2nd*2nd bit address... m With the door <m:0>The bit address receives the corresponding third address signal rs_add <m:0>.

[0047] As a first example, let the second address signal rs_addb <m:0>=11……11, the third address signal rs_add<n:m+1> =00……00, the third address signal rs_add <m:0>=11……11, then, the first address signal / rs_add<n:m+1> =11……11. At this time, the input signal of the first AND gate is / rs_add <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_addb <0> All are 1, and the row selection signal rowsel is generated after AND logic. <0> A high level signal is used to control the selection of row 0 of the pixel array; the input signal of the second AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_add <0> All are 1, row selection signal rowsel <1> A high level is used to control the selection of the first row of the pixel array; similarly, rowsel <2> rowsel <3> ...rowsel<2*2 m -1> are all high levels, used to control the selection of pixel arrays 2 to 2*2. m -1 line; implements 2*2 m Select all rows at the same time.

[0048] As a second example, let the second address signal rs_addb <m:0>=11……11, the third address signal rs_add<n:m+1> =00……00, the third address signal rs_add <m:0>=11……101, then, the first address signal / rs_add<n:m+1> =11……11. At this time, the input signal of the first AND gate is / rs_add <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_addb <0> All are 1, row selection signal rowsel <0> A high level selects row 0 of the pixel array; the input signal of the second AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_add <0> All are 1, row selection signal rowsel <1> A high level selects the first row of the pixel array; the input signal of the third AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> rs_addb <0> Both are 1, rs_add <1> The row selection signal is 0. <2> When the signal is low, the second row of the pixel array is not selected; the input signal of the fourth AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> Both are 1, rs_add <1> rs_add is 0 <0> The row selection signal is 1. <3> When the signal is low, the 3rd row of the pixel array is not selected; and so on, the row selection signal rowsel... <4> rowsel <5> When the signal is high, the row select signal (rowsel) is active. <6> rowsel <7> The level is low..., and each pair of rows is selected at intervals to achieve simultaneous selection of every two even-numbered rows (row 2i and row 2i+1, where i is an even number greater than or equal to 0).

[0049] As a third example, let the second address signal rs_addb <m:0>=11……11, the third address signal rs_add<n:m+1> =00……00, the third address signal rs_add <m:0>=11……10, then, the first address signal / rs_add<n:m+1> =11……11. At this time, the input signal of the first AND gate is / rs_add <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_addb <0> All are 1, row selection signal rowsel <0> A high level selects row 0 of the pixel array; the input signal of the second AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> All are 1, rs_add <0> The row selection signal is 0. <1> When the signal is low, the first row of the pixel array is not selected; the input signal of the third AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> rs_addb <0> Both are 1, rs_add <1> The row selection signal is 1. <2> A high level selects the second row of the pixel array; the input signal of the fourth AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> Both are 1, rs_add <1> rs_add is 1. <0> The row selection signal is 0. <3> When the signal is low, the 3rd row of the pixel array is not selected; and so on, the row selection signal rowsel... <4> When the signal is high, the row select signal (rowsel) is active. <5> The level is low... Each row is a group, and the rows are selected at intervals to achieve simultaneous selection of even-numbered rows (row 2j, where j is a natural number).

[0050] As a fourth example, let the second address signal rs_addb <m:0>=11……101, the third address signal rs_add<n:m+1> =00……00, the third address signal rs_add <m:0>=11……11, then, the first address signal / rs_add<n:m+1> =11……11. At this time, the input signal of the first AND gate is / rs_add <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> rs_addb <0> Both are 1, rs_addb <1> The row selection signal is 0. <0> When the signal is low, row 0 of the pixel array is not selected; the input signal of the second AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> rs_add <0> Both are 1, rs_addb <1> The row selection signal is 0. <1> When the signal is low, the first row of the pixel array is not selected; the input signal of the third AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> rs_addb <0> Both are 1, rs_add <1> The row selection signal is 1. <2> A high level selects the second row of the pixel array; the input signal of the fourth AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> All are 1, rs_add<1:0> is 0, and the row selection signal rowsel is 0. <3> When the signal is high, the 3rd row of the pixel array is selected; and so on, the row selection signal rowsel... <4> rowsel <5> When the level is low, the row select signal rowsel <6> rowsel <7> The value is high..., and each pair of rows is selected at intervals to achieve simultaneous selection of every two odd-numbered rows (row 2k and row 2k+1, where k is an odd number greater than 0).

[0051] As a fifth example, let the second address signal rs_addb <m:0>=11……10, the third address signal rs_add<n:m+1> =00……00, the third address signal rs_add <m:0>=11……11, then, the first address signal / rs_add<n:m+1> =11……11. At this time, the input signal of the first AND gate is / rs_add <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> Both are 1, rs_addb <0> The row selection signal is 0. <0> When the signal is low, row 0 of the pixel array is not selected; the input signal of the second AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> Both are 1, rs_add <0> The row selection signal is 1. <1> A high level selects the first row of the pixel array; the input signal of the third AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> Both are 1, rs_add <1> rs_addb is 1. <0> The row selection signal is 0. <2> When the signal is low, the second row of the pixel array is not selected; the input signal of the fourth AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <2> All are 1, rs_add<1:0> is 1, row selection signal rowsel <3> When the signal is high, the 3rd row of the pixel array is selected; and so on, the row selection signal rowsel... <4> When the level is low, the row select signal rowsel <5> The value is high level... Each row is a group, and the rows are selected at intervals to achieve simultaneous selection of odd-numbered rows (the 2l+1th row, where l is a natural number).

[0052] It should be noted that the second address signal rs_addb can be adjusted as needed. <m:0>and the third address signal rs_add <n:0>Assign values ​​to achieve different quantities (2*2) M Simultaneous selection of rows (M is a natural number); including but not limited to simultaneous selection of every 4 odd / even rows, every 8 odd / even rows, etc., which will not be elaborated here.

[0053] It should be noted that if the second address signal rs_addb <m:0>For the third address signal rs_add <m:0>Inverting the value transforms the process into a regular read operation where only one row is selected for each address. Example 2

[0054] like Figure 2 As shown, this embodiment provides a selection module, which includes nm groups of multi-row selection units. Each multi-row selection unit includes the same number of AND gates, and the input of each AND gate is connected to the corresponding address signal, and the output of each AND gate outputs the row selection signal in the pixel array.

[0055] Among them, the first address signal of the m+N-1th bit of the row selection unit in the Nth group of multi-row selection is / rs_add<m+N-1> Replace with the third address signal rs_add<m+N-1> And N is a positive integer ≤ nm.

[0056] Specifically, such as Figure 1 As shown, the first multi-row selection row selection unit has the same structure as the multi-row selection row selection unit 1 in Embodiment 1, and will not be described in detail here. Figure 2 As shown, the second multi-row selection row selection cell also includes 2*2 m Each and every door<n:m+2> and <m:0>The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate.<m+1> Each bit is replaced with the third address signal rs_add<m+1> The third multi-row selection also includes 2x2 cell selection. m Each and every door<n:m+3> and<m+1:0> The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate.<m+2> Each bit is replaced with the third address signal rs_add<m+2> Similarly, the row selection unit in the nmth group of multi-row selection also includes 2*2. m Each and every door <n-1:0>The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate. <n>Each bit is replaced with the third address signal rs_add <n>The third multi-row selection row selection unit...the nm group of multi-row selection row selection units are not illustrated, but those skilled in the art can learn about them based on the description of this invention, and will not be described in detail here. Example 3

[0057] This embodiment provides a selection module, which differs from Embodiment 2 in that the selection module includes 2*2 n-m -1 group of multi-row selection row selection units, each of the multi-row selection row selection units includes the same number of AND gates, and the input of each AND gate is connected to the corresponding address signal, and the output of each row selection signal in the pixel array is output respectively;

[0058] In this process, the row selection units in each group of multi-row selections sequentially convert the second address signal / rs_add from the least significant bit to the most significant bit in binary order.<n:m+1> Replace with the third address signal rs_add<n:m+1> The corresponding bit.

[0059] Specifically, the first multi-line selection row selection unit corresponds to binary 00...00, therefore, it does not replace the input address signal, and its structure is the same as that of the multi-line selection row selection unit 1 in Embodiment 1, which will not be described in detail here. The second multi-line selection row selection unit also includes 2*2 m Each AND gate corresponds to binary 00...01.<n:m+2> and <m:0>The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate.<m+1> Each bit is replaced with the third address signal rs_add<m+1> The third multi-row selection also includes 2x2 cell selection. m Each AND gate corresponds to binary 00...10.<n:m+3> and<m+1:0> The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate.<m+2> Each bit is replaced with the third address signal rs_add<m+2> The fourth multi-row selection also includes 2x2 cell selection. m Each AND gate corresponds to binary 00...11.<n:m+3> and <m:0>The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate.<m+2:m+1> Each bit is replaced with the third address signal rs_add<m+2:m+1> Similarly, the row selection unit in the nmth group of multi-row selection also includes 2*2. m Each and every door <m:0>The position of the AND gate in the first multi-row selected row selection cell is consistent with the corresponding AND gate, and the first position of each AND gate is consistent with the corresponding AND gate.<n:m+1> Each bit is replaced with the third address signal rs_add<n:m+1> . Example 4

[0060] like Figure 3 As shown, this embodiment provides a selection module, which differs from the selection module in Embodiment 1 in that the selection module in this embodiment is used to implement 3*2 m Select all rows at the same time.

[0061] Specifically, the selection module includes a set of multi-row selection units, and the multi-row selection units include 3*2 m Each AND gate outputs a 3x2 pixel array. m Each row selection signal is denoted as rowsel. <0> rowsel <1> ...rowsel<2*2 m -2>、rowsel<3*2 m -1>. Each AND gate's input terminals include... <n:0>Bit address. Each AND gate's<n:m+1> Each bit address receives the corresponding first address signal / rs_add<n:m+1> Each and every door <m:0>The bit address is sequentially processed from least significant bit to most significant bit in binary format, with the second address signal rs_addb... <m:0>Replace with the third address signal rs_add <m:0>The corresponding bits, and the last two bits are removed and concatenated to rs_add. <1> and rs_add <0> The address combination; where the first AND gate corresponds to binary 000...000, does not change the input address signal, therefore, the first AND gate's <m:0>The bit address receives the corresponding second address signal rs_addb <m:0>The second AND gate corresponds to binary 000...001, changing the 0th bit of the address signal. Therefore, the second AND gate... <m:1>The bit address receives the corresponding second address signal rs_addb <m:1>The second AND gate <0> The bit address receives the corresponding third address signal rs_add <0> The third AND gate corresponds to binary 000...010, changing the first address bit. Therefore, the third AND gate... <m:2>and <0> The bit address receives the corresponding second address signal rs_addb <m:2>and rs_addb <0> The third AND gate <1> The bit address receives the corresponding third address signal rs_add <1> The last two bits of the binary representation should be replaced with rs_add. <1> and rs_add <0> The address combination is skipped; therefore, the fourth AND gate corresponds to binary 000...100, changing the second address bit signal. The fourth AND gate... <m:3>The <1:0> bit address receives the corresponding second address signal rs_addb <m:3>and rs_addb<1:0>, the fourth AND gate <2> The bit address receives the corresponding third address signal rs_add <2> The fifth AND gate corresponds to binary 000...101. Changing the 2nd and 0th address bits of the fifth AND gate... <m:3>and <1> The bit address receives the corresponding second address signal rs_addb <m:3>and rs_addb <1> The fifth AND gate <2> and <0> The bit address receives the corresponding third address signal rs_add <2> and rs_add <0> The sixth AND gate corresponds to binary 000...110. By changing the 2nd and 1st address bits, the sixth AND gate... <m:3>and <0> The bit address receives the corresponding second address signal rs_addb <m:3>and rs_addb <0> The <2:1> bit address of the sixth AND gate receives the corresponding third address signal rs_add<2:1>; and so on, the 3*2 m -2 and the door <m:2>The bit address receives the corresponding third address signal rs_add <m:2>, No. 3*2 m -2 AND gate <1:0> bit address receives the corresponding second address signal rs_addb<1:0>; 3*2 m -1 and the door <m:2>and <0> The bit address receives the corresponding third address signal rs_add <m:2>and rs_add <0> , No. 3*2 m -1 and the door <1> The bit address receives the corresponding second address signal rs_addb <1> ;No. 3*2 m With the door <m:1>The bit address receives the corresponding third address signal rs_add <m:1>, No. 3*2 m With the door <0> The bit address receives the corresponding second address signal rs_addb <0> .

[0062] It should be noted that the last two digits of the address should be replaced with rs_add. <1> and rs_add <0> The address combinations are skipped, which is equivalent to deleting the addresses in rows 3, 7, 11... sequentially based on Example 1 (i.e., skipping bits 1 and 0 in rs_add). <1> rs_add <0> The "deletion" described in this invention does not physically delete rows 3, 7, 11, etc., but rather assigns the address of the original row 4 in Embodiment 1 to row 3 and controls whether row 3 is selected in the pixel array. The corresponding row selection addresses are sequentially forward: the address of the original row 5 is assigned to row 4 and controls whether row 4 is selected in the pixel array; the address of the original row 6 is assigned to row 5 and controls whether row 5 is selected in the pixel array; the address of the original row 8 is assigned to row 6 and controls whether row 6 is selected in the pixel array; and so on. These will not be elaborated upon here.

[0063] Alternatively, let the second address signal rs_addb <m:0>=11……11, the third address signal rs_add<n:m+1> =00……00, the third address signal rs_add <m:0>=11……11, then, the first address signal / rs_add<n:m+1> =11……11. At this time, the input signal of the first AND gate is / rs_add <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_addb <0> All are 1, row selection signal rowsel <0> A high level selects row 0 of the pixel array; the input signal of the second AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_add <0> All are 1, row selection signal rowsel <1> A high level selects the first row of the pixel array; the input signal of the third AND gate is / rs_add. <n>、 / rs_add <n-1>、 / rs_add <n-2>…… / rs_add<m+1>、rs_addb <m>,rs_addb <m-1>……rs_addb <1> rs_add <0> All are 1, row selection signal rowsel <1> A high level selects the first row of the pixel array; similarly, rowsel... <3> rowsel <4> ...rowsel<3*2 m -1> All are high level, select pixel array 3 to 3*2 m -1 line; implements 3*2 m Select all rows at the same time. Example 5

[0064] This embodiment provides a selection module, which differs from Embodiment 2 in that the multi-row selection unit can also be implemented using the structure of Embodiment 4.

[0065] Specifically, similarly, each AND gate in each row selection cell of a multi-row selection... <m:0>The bit is consistent with the corresponding AND gate in the multi-row selection row selection unit of Embodiment 2, and the first address signal / rs_add of the m+N-1th bit of the Nth group of multi-row selection row selection units in each multi-row selection row selection unit is consistent with the first address signal of the m+N-1th bit of the multi-row selection row selection unit.<m+N-1> Replace with the third address signal rs_add<m+N-1> I will not go into detail here. Example 6

[0066] This embodiment provides a selection module, which differs from Embodiment 3 in that the multi-row selection unit can also be implemented using the structure of Embodiment 4.

[0067] Specifically, similarly, each AND gate in each row selection cell of a multi-row selection... <m:0>The bits are consistent with the corresponding AND gates in the multi-row selection row selection unit of Embodiment 2. Each multi-row selection row selection unit sequentially processes the second address signal / rs_add in binary from the least significant bit to the most significant bit.<n:m+1> Replace with the third address signal rs_add<n:m+1> The corresponding bits are not detailed here. Example 7

[0068] like Figure 4 As shown, this embodiment provides a pixel row selection module 1, which includes:

[0069] First AND logic unit 11, second AND logic unit 12, OR gate 13, first selected module 14 and second selected module 15.

[0070] like Figure 4 As shown, the input terminals of the first logic unit 11 receive the address signal and the first enable signal en0, respectively, and the output terminal is connected to the input terminal of the first selected module 14. When the first enable signal en0 is valid, it provides the address signal to the first selected module 14.

[0071] Specifically, in this embodiment, the first AND logic unit 11 includes two AND gates, and one input of each of the two AND gates is respectively connected to the second address signal rs_addb. <m:0>and the third address signal rs_add <n:0>The other end is connected to the first enable signal en0, and the output end is connected to the first selected module 14. In actual use, the structure of the first logic unit 11 can be set as needed to achieve the above functions, and is not limited to this embodiment.

[0072] like Figure 4 As shown, the input terminals of the second AND logic unit 12 receive the address signal and the second enable signal en1, respectively, and the output terminal is connected to the input terminal of the second selected module 15. When the second enable signal en1 is valid, it provides the address signal to the second selected module 15.

[0073] Specifically, in this embodiment, the second AND logic unit 12 has the same structure as the first AND logic unit 11, except that the received enable signal is different, which will not be described in detail here. In actual use, the structure of the second AND logic unit 12 can be set as needed to achieve the above functions, and is not limited to this embodiment.

[0074] like Figure 4 As shown, the first selected module 14 is used to implement 2*2 a All rows are selected simultaneously, where 'a' is an integer greater than or equal to 0.

[0075] Specifically, the first selection module 14 may be the selection module of Embodiment 1, Embodiment 2 or Embodiment 3, which will not be described in detail here.

[0076] like Figure 4 As shown, the second selected module 15 is used to implement 3*2 a All rows are selected simultaneously, where 'a' is an integer greater than or equal to 0.

[0077] Specifically, the second selection module 15 may be the selection module of Embodiment 4, Embodiment 5 or Embodiment 6, which will not be described in detail here.

[0078] like Figure 4 As shown, the first input terminal of the OR gate 13 is connected to the output terminal of the first selection module 14, and the second input terminal is connected to the output terminal of the second selection module 15, outputting the row selection signal (rowsel) of the pixel array. <n:0>.

[0079] like Figure 4 As shown, by switching between the first enable signal en0 and the second enable signal en1, two different addressing modes can be switched.

[0080] like Figure 5 As shown, as an example, a scheme to simultaneously select 4 or 3 rows includes the second address signal rs_addb<1:0> and the third address signal rs_add<3:0>. When the second address signal rs_addb<1:0>=11 and the third address signal rs_add<3:0>=0011, rows 0, 1, 2, and 3 can be selected based on the first selection module 34, or rows 0, 1, and 2 can be selected based on the second selection module 35. When the second address signal rs_addb<1:0>=11 and the third address signal rs_add<3:0>=0111, rows 4, 5, 6, and 7 can be selected based on the first selection module 34, or rows 3, 4, and 5 can be selected based on the second selection module 35. For ease of explanation, Figure 5 Both the first selection module 14 and the second selection module 15 display only two groups of multi-line selection units. In actual use, the number of multi-line selection units can be set as needed. Example 8

[0081] like Figure 6 As shown, this embodiment provides a pixel readout circuit, which includes:

[0082] Pixel array 2, readout module 3, and selection module 4.

[0083] like Figure 6 As shown, the selection module 4 provides row selection signals (rowsel) to the pixel array 2. <n:0>The selected module 4 can be any one of Embodiments 1 to 6. As an example, the selected module 4 also provides a reset signal rst. <n:0>and transmission signal tx <n:0>.

[0084] like Figure 6 As shown, the readout module 3 receives the column readout signal from the pixel array 2; in this embodiment, the readout module 3 is a column-level ADC that outputs digital signals; in actual use, the readout module can be configured as needed to achieve the readout function, and is not limited to this embodiment. Example 9

[0085] like Figure 7 As shown, this embodiment provides a pixel readout circuit, which differs from Embodiment 8 in that a pixel row selection module 5 is used to replace the selection module 4; the pixel row selection module 5 is the pixel row selection module of Embodiment 7, which will not be described in detail here.

[0086] This invention implements a multi-row simultaneous selection addressing method based on single-row pixel selection, so that multiple rows of pixel signals can be read out simultaneously under certain conditions, thereby improving the frame rate of the image sensor and increasing the readout speed of the pixel array signal.

[0087] In summary, this invention provides a selection module, a pixel row selection module, and a pixel readout circuit, comprising: a set of multi-row selection units, each multi-row selection unit including multiple AND gates, the input of each AND gate being connected to a corresponding address signal, and the output of each AND gate outputting a row selection signal in the pixel array; the AND gates in the multi-row selection unit...<n:m+1> Each bit address receives its corresponding first address signal / rs_add<n:m+1> Each and every door <m:0>Each bit address receives its corresponding second address signal rs_addb <m:0>Furthermore, in the same group of multi-row selection cells, each AND gate sequentially converts the second address signal rs_addb from the least significant bit to the most significant bit in binary order. <m:0>Replace with the third address signal rs_add <m:0>The corresponding bits; where the first address signal / rs_add<n:m+1> For the third address signal rs_add<n:m+1> The inverted signal, where m and n are both natural numbers, and m is less than n. The selection module, pixel row selection module, and pixel readout circuit of this invention can achieve simultaneous selection of multiple rows, greatly improving the readout speed of the pixel array and thus increasing the frame rate of the image sensor; it can achieve 2*2 M row or 3*2 m This invention allows for the simultaneous selection of rows, and different numbers of rows can be selected simultaneously by setting different address signals. It offers high flexibility and versatility. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention. < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n>

Claims

1. A selection module, based on a single-row readout architecture of pixel array signals, characterized in that, The selected modules include at least: A set of multi-row selection row selection units, wherein the multi-row selection row selection unit includes multiple AND gates, the input of each AND gate is connected to the corresponding address signal, and the output of each AND gate outputs the row selection signal in the pixel array respectively; Each AND gate in the multi-row selection row selection unit<n:m+1> Each bit address receives its corresponding first address signal / rs_add<n:m+1> Each and every door <m:0>Each bit address receives its corresponding second address signal rs_addb <m:0>Furthermore, within the same group of multi-row selection cells, each AND gate sequentially processes the second address signal rs_addb from least significant bit to most significant bit according to the binary representation of the AND gate. <m:0>Replace with the third address signal rs_add <m:0> The corresponding bits, wherein the first AND gate does not change the address signal;< / m:0> Among them, the first address signal / rs_add<n:m+1> For the third address signal rs_add<n:m+1> The inverted signal of , where m and n are both natural numbers, and m is less than n.

2. The selected module according to claim 1, characterized in that: The multi-row selection row selection unit includes 2*2 m In the multi-row selection row selection unit, the second address signal rs_addb is an AND gate. <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0>=11……11, to achieve 2*2 m Select all rows at the same time.

3. The selected module according to claim 1, characterized in that: The multi-row selection row selection unit includes 2*2 m In the AND gate, within the multi-row selection row selection unit, the second address signal rs_addb <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0> =11……101, used to select every two even-numbered rows.< / m:0> 4. The selected module according to claim 1, characterized in that: The multi-row selection row selection unit includes 2*2 m In the AND gate, within the multi-row selection row selection unit, the second address signal rs_addb <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0> =11……10, used to select even-numbered rows.< / m:0> 5. The selected module according to claim 1, characterized in that: The multi-row selection row selection unit includes 2*2 m In the AND gate, within the multi-row selection row selection unit, the second address signal rs_addb <m:0>=11……101, rs_add in the third address signal<n:m+1> =00……00、rs_add <m:0> =11……11 is used to select every two odd-numbered rows.< / m:0> 6. The selected module according to claim 1, characterized in that: The multi-row selection row selection unit includes 2*2 m In the AND gate, within the multi-row selection row selection unit, the second address signal rs_addb <m:0>=11……10, rs_add in the third address signal<n:m+1> =00……00、rs_add <m:0> =11……11, used to select odd-numbered rows.< / m:0> 7. The selection module according to claim 1, characterized in that, The multi-row selection row selection unit includes 3*2 m Each AND gate, after removing the last two bits, is connected to rs_add. <1> and rs_add <0> The address combination; and set the second address signal rs_addb <m:0>=11……11, in the third address signal rs_add<n:m+1> =00……00、rs_add <m:0>=11……11, to achieve 3*2 m Select all rows at the same time.

8. The selected module according to any one of claims 1-7, characterized in that: The selection module includes nm groups of multi-row selection units, each of which includes the same number of AND gates. The input of each AND gate is connected to the corresponding address signal, and the output of each AND gate outputs the row selection signal in the pixel array. In this context, the first address signal / rs_add<m+N-1> of the m+N-1th bit of the row selection unit in the Nth group of multi-row selection is replaced by the third address signal rs_add<m+N-1>, and N is a positive integer ≤ nm.

9. The selected module according to any one of claims 1-7, characterized in that: The selected module includes 2*2 n-m -1 group of multi-row selection row selection units, each of the multi-row selection row selection units includes the same number of AND gates, and the input of each AND gate is connected to the corresponding address signal, and the output of each row selection signal in the pixel array is output respectively; In this process, the row selection units in each group of multi-row selections sequentially convert the second address signal / rs_add from the least significant bit to the most significant bit in binary order.<n:m+1> Replace with the third address signal rs_add<n:m+1> The corresponding bit.

10. A pixel row selection module, characterized in that, The pixel row selection module includes at least: The system comprises a first AND logic unit, a second AND logic unit, an OR gate, a first selection module, and a second selection module; the first selection module is a selection module that simultaneously selects an even number of rows, and is composed of the selection modules described in any one of claims 2-6, 8, and 9; the second selection module is a 3*2... m The selection module for simultaneous selection of rows is composed of the selection module as described in any one of claims 7-9; The first logic unit receives an address signal and a first enable signal at its input terminal, and its output terminal is connected to the input terminal of the first selected module. When the first enable signal is valid, it provides an address signal to the first selected module. The input terminals of the second logic unit receive an address signal and a second enable signal, respectively, and the output terminal is connected to the input terminal of the second selected module. When the second enable signal is valid, it provides an address signal to the second selected module. The first input of the OR gate is connected to the output of the first selected module, and the second input is connected to the output of the second selected module, outputting the row selection signal of the pixel array.

11. A pixel readout circuit, characterized in that, The pixel readout circuit includes at least: The pixel array, the readout module, and the selection module as described in any one of claims 1-9; the selection module provides row selection signals for the pixel array; and the readout module receives column readout signals from the pixel array.

12. A pixel readout circuit, characterized in that, The pixel readout circuit includes at least: The pixel array, the readout module, and the pixel row selection module as described in claim 10; the pixel row selection module provides row selection signals for the pixel array; the readout module receives column readout signals from the pixel array.

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