Preparation and application method of planar thermoelectric thin film device

Abstract

The application discloses a preparation and application method of a planar thermoelectric thin film device, the preparation method adopts a standard integrated circuit manufacturing process, metal electrode material, P-type or N-type thermoelectric material of the device is deposited on the same substrate plane, and is prepared through mask photolithography, so that the complex MEMS process is avoided, the process is simple, low in cost and capable of realizing batch preparation, and the like, meanwhile, the material interface contact area in the planar direction is increased, the influence of parasitic parameters such as contact thermal resistance and contact resistance can be overcome to a certain extent, efficient hot spot cooling or micro-area refrigeration is realized, and the peak temperature of a chip is rapidly reduced; the application method can cool the chip hot spot in real time, energy is captured in a time period without power supply, and the energy can be used for power supply of active devices after storage, thereby providing a new idea for realizing true electronic equipment self-power intelligent heat management and advanced intelligent control of a more complex and harsh scene.

Description

Technical Field

[0001] This invention belongs to the field of thermal management technology for electronic devices, and particularly relates to a method for the preparation and application of a planar thermoelectric thin film device. Background Technology

[0002] As electronic devices gradually move towards miniaturization and high packaging density, the power consumption of chips continues to increase and usually reaches its peak in a short period of time, generating local hot spots with rapidly changing heat flux density over time. These local hot spots will directly cause local thermal failure problems such as overheating and burn-out, and will also cause various failures such as thermal stress failure, mechanical embrittlement / weakness, parasitic chemical reactions and impurity diffusion of interface materials, which will seriously affect the performance, reliability and lifespan of electronic devices, posing a great challenge to chip thermal management.

[0003] Traditional chip thermal management technologies suffer from limitations such as uneven cooling, high cost, low reliability, and large size. They struggle to provide transient cooling to localized hot spots on chip surfaces with timescales much smaller than the thermal time constant, failing to meet the dynamic thermal management requirements of increasingly demanding operating and environmental conditions. For example, liquid cooling presents sealing challenges and relatively high costs when the liquid flows through the chip, and often leads to overcooling. Similarly, both liquid and air cooling technologies are heavily constrained by ambient and fluid temperatures, unable to reduce the temperature of the object being cooled below ambient or fluid temperatures, and struggle to precisely and precisely adjust the chip junction temperature. While heat pipe cooling technology can achieve a cooling heat flux density of 200 W / cm², it is not feasible. 2 However, this technology has a certain heat dissipation limit. When the heat at the evaporation end exceeds a certain limit, the working medium will completely vaporize, causing the cycle to be interrupted. Therefore, traditional thermal management technology is gradually being challenged with the development of chips. Chip cooling needs to move towards microscale integration. Chip thermal management technology developed on a dynamic basis will significantly improve the size, weight, power, and cost of next-generation high-performance electronic devices.

[0004] Thermoelectric thin-film devices (TDPs) are a highly integrated, lightweight, all-solid-state micro-thermal management technology that utilizes the Peltier effect for localized active thermal management. Due to their flexible placement, convenient integration, fast response time, precise temperature control, and high reliability, TDPs offer significant advantages in hotspot cooling applications for chips. When the chip's hotspot temperature reaches a threshold, TDPs can implement dynamic thermal management mechanisms similar to throttling, current (voltage) frequency regulation, or task migration, providing on-demand cooling, reducing the chip's peak temperature, and maintaining high-power / high-frequency operation for a longer period, significantly improving chip performance. However, the manufacturing process of TDPs is complex and costly, currently limited to laboratory development. Furthermore, the complex three-dimensional integration environment and harsh service conditions pose severe challenges to the functionality and reliability of TDPs. The topology design, parasitic contact electrical (thermal) resistance, and hot-end heat dissipation of TDPs are key factors limiting their performance. Therefore, how to further improve the heat pumping capability of thermoelectric thin film devices is the core content of expanding the application of micro thermoelectric refrigeration technology. The miniaturization and high performance of thermoelectric thin film devices face complex and severe scientific and technological problems that urgently need to be solved. Summary of the Invention

[0005] In view of this, this application proposes a method for fabricating and applying planar thermoelectric thin film devices. The fabrication method uses standard integrated circuit manufacturing processes to complete the fabrication of planar thermoelectric thin film devices, avoiding complex MEMS processes. It has advantages such as simple process, low cost and the ability to achieve mass production. The application method uses current / voltage to control the cooling mode or energy capture mode of the planar radial thermoelectric thin film device, realizing true self-powered intelligent thermal management of electronic devices.

[0006] To achieve this objective, the first aspect of this application protects an application method for a planar thermoelectric thin film device, the method comprising: adjusting the input current or voltage according to the chip cooling requirements, so that the cold end and hot end of the planar thermoelectric thin film device appear at different positions on the thermoelectric arm, so that the planar thermoelectric thin film device operates in cooling mode or energy capture mode respectively.

[0007] The planar thermoelectric thin film device includes: an insulating substrate at the bottom layer, a metal bottom electrode on the insulating substrate, and P-type thermoelectric arms and N-type thermoelectric arms radially distributed on the metal bottom electrode, wherein the P-type thermoelectric arms and N-type thermoelectric arms are arranged at intervals around the center of the thermoelectric thin film device, and the positions of the P-type thermoelectric arms and N-type thermoelectric arms can be interchanged; the metal bottom electrode is also provided with a current or voltage input electrode and a ground electrode.

[0008] Preferably, the application method includes:

[0009] During the phase when chip power consumption and chip temperature rise rapidly, current or voltage is applied to the thermoelectric thin film device to activate the active cooling mode of the thermoelectric thin film device, so that the end of the thermoelectric arm of the thermoelectric thin film device closer to the center of the device is the cold end and the end farther away from the center of the device is the hot end, so that the chip can be cooled quickly.

[0010] When the chip power consumption is low or when chip thermal management is not required, no current or voltage is input to the thermoelectric thin film device. At this time, the end of the thermoelectric arm of the thermoelectric thin film device that is closer to the central heating area of ​​the device is the hot end, and the end that is farther away from the central heating area of ​​the device is the cold end. The thermoelectric thin film device operates in energy capture mode to capture energy and store the energy through an energy storage device, so as to provide power when the thermoelectric thin film device is cooled or to provide power to other active devices.

[0011] A second aspect of this application protects a method for fabricating a planar thermoelectric thin-film device. The method is used to fabricate a planar thermoelectric thin-film device for use in the aforementioned application method. The method is performed using a standard integrated circuit manufacturing process and includes:

[0012] S1: After organic cleaning of the insulating substrate material, photoresist is spin-coated onto it and photolithography is performed through a mask.

[0013] S2: Deposit a metal thin film on an insulating substrate material and pattern the metal bottom electrode using a lift-off process or an etching process;

[0014] S3: Heat the insulating substrate material to deposit P-type or N-type thermoelectric material, spin-coat photoresist, perform photolithography through a mask, and then use an etching process to complete the patterning of the P-type or N-type thermoelectric arm.

[0015] S4: Heat the insulating substrate material to deposit N-type or P-type thermoelectric material, spin-coat photoresist, perform photolithography through a mask, and then use an etching process to pattern the N-type or P-type thermoelectric arm to obtain a planar thermoelectric thin film device structure.

[0016] S5: Spin-coat photoresist onto the surface of a planar thermoelectric thin film device, perform photolithography through a mask, and bake to cure to form a protective layer.

[0017] Preferably, the insulating substrate material is obtained by coating one or more of the following: polyimide substrate, quartz substrate, mica substrate, glass substrate, silicone rubber substrate, silicone resin substrate, polyethylene terephthalate substrate, polyethylene naphthalate substrate, silicon-based substrate, silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, diamond substrate, sapphire substrate, alumina substrate, aluminum nitride substrate, beryllium oxide substrate, and silicon nitride substrate with an insulating medium.

[0018] Preferably, the method for depositing the metal thin film, N-type or P-type thermoelectric material is any one of molecular beam epitaxy, pulsed laser deposition, metal-organic chemical vapor deposition, magnetron sputtering deposition, vacuum evaporation deposition, and electrochemical deposition.

[0019] Preferably, the metal bottom electrode is made of any one or more of the following materials: copper, aluminum, gold, silver, chromium, nickel, titanium, cobalt, tin, zinc, bismuth, molybdenum, tungsten, iron, indium, niobium, antimony, manganese, lead, tantalum, yttrium, hafnium, vanadium, platinum, rhenium, palladium, iridium, rhodium, ruthenium, and their alloys.

[0020] Preferably, the etching process is either a wet etching process or a dry etching process.

[0021] Preferably, the deposition thickness of the P-type thermoelectric material or the N-type thermoelectric material is 1 nm to 100 μm.

[0022] Preferably, the P-type thermoelectric material and the N-type thermoelectric material are any one or more of the following: Bi2Te3-based binary or ternary materials, Sb2Te3-based binary or ternary materials, Pb2Te3-based binary or ternary materials, SnSe-based binary or ternary materials, Mg-based binary or ternary materials, Te-based binary or ternary materials, Sn-based binary or ternary materials, SiGe alloy materials, semi-Halles alloys, graphene, squartzite, or filled squartzite materials.

[0023] The beneficial effects of this invention are as follows: The method for fabricating planar thermoelectric thin-film devices proposed in this invention is used to fabricate planar thermoelectric thin-film devices comprising an insulating substrate, a metal bottom electrode, and thermoelectric arms arranged around the center. This fabrication method employs standard integrated circuit manufacturing deposition processes and photolithography processes to fabricate planar thermoelectric thin-film devices, avoiding the use of complex MEMS processes. The fabrication process is simple and easily achieves low-cost and mass production of thermoelectric thin-film devices. Simultaneously, this fabrication method increases the contact area of ​​the material interface in the planar direction, which to some extent overcomes the influence of parasitic parameters such as contact thermal resistance and contact resistance on device performance, significantly improving the performance of planar thermoelectric thin-film devices, achieving larger temperature differences, and higher cooling power density or power generation power density.

[0024] The application method proposed in this application utilizes input current / voltage to control the hot and cold ends of a planar radial thermoelectric thin film device, thereby switching the planar radial thermoelectric thin film device into a cooling mode or an energy trapping mode. In the cooling mode, the device can efficiently cool the chip hotspot through the Peltier effect. In the energy trapping mode, the device achieves energy trapping through the Seebeck effect and stores the energy through an energy storage device to provide power for the device during cooling or to power other active devices in the system. This achieves true self-powered intelligent thermal management of electronic devices and provides a new approach for advanced intelligent control in higher-level, complex, and demanding scenarios. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the planar thermoelectric thin film device in an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the fabrication process of the planar thermoelectric thin film device in the embodiments of this application;

[0027] Figure 3 This is a schematic diagram illustrating the application method of the planar thermoelectric thin film device in the embodiments of this application;

[0028] Figure 4 This is a flowchart illustrating the application method of the planar thermoelectric thin film device in the embodiments of this application;

[0029] In the figure: 101. Insulating substrate 102. Metal bottom electrode 103. P-type thermoelectric arm 104. Device center 105. N-type thermoelectric arm 106. Current or voltage input terminal 107. Ground terminal 201. Insulating substrate material 202. Photoresist 203. Metal thin film 204. N-type thermoelectric material 205. P-type thermoelectric material. Detailed Implementation

[0030] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

[0031] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0032] This application proposes a method for fabricating and applying a planar thermoelectric thin-film device. As an example, the structure of the planar thermoelectric thin-film device to be fabricated and applied in this application is as follows: Figure 1As shown, the planar thermoelectric thin-film device includes: an insulating substrate 101 at the bottom, a metal bottom electrode 102 on the insulating substrate 101, and P-type thermoelectric arms 103 and N-type thermoelectric arms 105 radially distributed on the metal bottom electrode 102, which are arranged at intervals around the device center 104. The metal bottom electrode 103 also has a current or voltage input terminal 106 and a ground terminal 107. After current or voltage is input to the current or voltage input terminal 106, a cold end is formed in the central region 104 of the device for localized cooling, while a hot end is formed on the outer side of the device for heat dissipation. Since the area of ​​the hot end is significantly larger than that of the cold end, the lower thermal resistance of the hot end facilitates heat dissipation, while the higher thermal resistance of the cold end facilitates the accumulation of cold energy, thus enhancing the cooling performance of the device. This structural design helps to increase the effective cooling area (hot end area / cold end area), forming a good heat transfer path and achieving high integration of the thermoelectric thin-film device.

[0033] The application method and preparation method of this application will be described using a planar thermoelectric thin film device with the above structure as an example.

[0034] As an example, such as Figure 2 The method for fabricating the planar thermoelectric thin-film device shown includes metal bottom electrode deposition and patterning, P-type thermoelectric arm deposition and patterning, and N-type thermoelectric arm deposition and patterning. The specific process is as follows:

[0035] S1: The insulating substrate material 201 was ultrasonically cleaned for 5 minutes using acetone, ethanol and deionized water respectively, and then dried with N2. After that, photoresist 202 was spin-coated on the insulating substrate material 201 and photolithography was performed through a mask.

[0036] S2: Deposit a metal thin film 203 on the insulating substrate material 201 as a metal bottom electrode. As an example, the metal thin film 203 is a Ti / Cu thin film.

[0037] S3: The metal film 203 is patterned using a lift-off process, then washed sequentially with acetone, ethanol and deionized water, and dried with N2.

[0038] S4: Heat the insulating substrate material 201 to 300°C to deposit the N-type Bi2Te3 thermoelectric material 204;

[0039] S5: Spin-coat photoresist 202 onto N-type Bi2Te3 thermoelectric material 204 and perform photolithography through a mask;

[0040] S6: The N-type thermoelectric arm is patterned using a wet etching process;

[0041] S7: Heat the insulating substrate material 201 to 300°C to deposit the P-type Sb2Te3 thermoelectric material 205;

[0042] S8: Photoresist 202 is spin-coated onto P-type Sb2Te3 thermoelectric material 205 and photolithography is performed using a mask;

[0043] S9: The P-type thermoelectric arm pattern is completed using a wet etching process 205, which yields the planar thermoelectric thin film device structure;

[0044] S10: Finally, spin-coat photoresist onto the surface of the planar thermoelectric thin film device, perform photolithography through a mask, and bake to cure to form a protective layer.

[0045] In this embodiment, the insulating substrate material is selected as a polyimide substrate. In addition, the insulating substrate material can also be any one or more of the following: quartz substrate, mica substrate, glass substrate, silicone rubber substrate, silicone resin substrate, polyethylene terephthalate substrate, polyethylene naphthalate substrate, silicon-based substrate, silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, diamond substrate, sapphire substrate, aluminum oxide substrate, aluminum nitride substrate, beryllium oxide substrate, and silicon nitride substrate, after coating with an insulating medium.

[0046] The above preparation methods for depositing metal thin films, N-type or P-type thermoelectric materials can be any one of molecular beam epitaxy, pulsed laser deposition, metal-organic chemical vapor deposition, magnetron sputtering deposition, vacuum evaporation deposition, and electrochemical deposition.

[0047] The metal bottom electrode material in the above preparation method is composed of any one or more of the following: copper, aluminum, gold, silver, chromium, nickel, titanium, cobalt, tin, zinc, bismuth, molybdenum, tungsten, iron, indium, niobium, antimony, manganese, lead, tantalum, yttrium, hafnium, vanadium, platinum, rhenium, palladium, iridium, rhodium, ruthenium, and their alloys.

[0048] The etching process described above can be either wet etching or dry etching.

[0049] The aforementioned P-type and N-type thermoelectric materials are any one or more of the following: Bi2Te3-based binary or ternary materials, Sb2Te3-based binary or ternary materials, Pb2Te3-based binary or ternary materials, SnSe-based binary or ternary materials, Mg-based binary or ternary materials, Te-based binary or ternary materials, Sn-based binary or ternary materials, SiGe alloy materials, semi-Halles alloys, graphene, squartzite, or filled squartzite materials.

[0050] In the above preparation process, when depositing P-type or N-type thermoelectric materials, the thickness of the deposited thermoelectric materials ranges from 1 nm to 100 μm, which can ensure the superior cooling performance and energy capture performance of the planar thermoelectric thin film device in application, and at the same time help to obtain a faster response time.

[0051] The above-described fabrication method deposits metal electrode materials, P-type thermoelectric materials, and N-type thermoelectric materials on the same substrate plane and fabricates them together using photolithography, avoiding the use of complex MEMS processes. This gives planar thermoelectric thin film devices advantages such as miniaturization, low cost, and mass production. At the same time, it increases the material interface contact area in the planar direction, which can overcome the influence of parasitic parameters such as contact thermal resistance and contact resistance to a certain extent, achieving efficient cooling of hot spot micro-regions and rapidly reducing the peak temperature of the chip.

[0052] As an example, the application method of this planar thermoelectric thin film device is as follows: Based on the chip cooling requirements, the input current or voltage is adjusted so that the cold end and hot end of the planar thermoelectric thin film device are located at different positions on the thermoelectric arm, thereby enabling the planar thermoelectric thin film device to operate in either cooling mode or energy harvesting mode. The specific process is as follows: Figure 4 As shown, it specifically includes:

[0053] 401: When the chip is in a low-power stage, the planar thermoelectric thin film device does not need to be supplied with current or voltage and is connected to an energy storage device to put it in an energy capture working mode.

[0054] 402: Planar thermoelectric thin film devices collect energy (thermal energy) through the Seebeck effect and store the energy through an energy storage device to provide power when the device is cooled or to power other active devices;

[0055] 403: When the chip power consumption increases, apply an appropriate current or voltage to the planar thermoelectric thin film device to switch it to active cooling mode;

[0056] 404: Planar thermoelectric thin film devices utilize the Peltier effect to form a cold end in the central region of the device for localized cooling of the chip, effectively reducing the chip temperature and thermal slope.

[0057] 405: When the chip temperature decreases and thermal management is no longer needed (long-term operation of the device may cause temperature overshoot), the planar thermoelectric thin film device is switched to energy harvesting mode and the system energy is continued to be harvested through the Seebeck effect.

[0058] Figure 3 A schematic diagram illustrating the application methods of planar thermoelectric thin-film devices is shown in the figure. The maximum allowable junction temperature T is shown in the figure. d 301 is a pre-configured or predefined temperature, which is also the upper limit of the chip's temperature. To allow for a certain margin, this maximum allowable junction temperature T is set.d 301 is selected below the thermal burn-out temperature of the chip or component. Curve 302 is the power consumption curve generated when the chip is working; curve 303 is the chip temperature curve without the integrated planar thermoelectric thin film device; curve 304 is the chip temperature curve with the integrated planar thermoelectric thin film device proposed in the embodiments of this application and active cooling. The chip temperature curve 304 after integrating the planar thermoelectric thin film device is lower than the chip temperature curve 303 without the integrated planar thermoelectric thin film device, and the temperature difference between the two curves is ΔTpassive. This is because integrating the device into the chip TIM increases the effective thermal conductivity of the chip TIM layer.

[0059] As shown in the curves, during the rapid rise of the chip power consumption curve 302 and the chip temperature curve 303, the active cooling mode 305 of the planar thermoelectric thin film device will be activated. Based on the Peltier effect, the planar thermoelectric thin film device transfers heat radially from the central cold end to the surrounding environment. Since the area of ​​the hot end is significantly larger than that of the cold end at this time, the thermal resistance of the hot end is smaller, which is conducive to heat dissipation. The thermal resistance of the cold end is larger, which is conducive to the accumulation of cold energy. This enhances the cooling performance of the device, thereby enabling the chip to be cooled rapidly. The chip temperature and thermal slope are effectively reduced, and the temperature drop is ΔTactive.

[0060] During periods of low chip power consumption and when chip thermal management is not required (prolonged device operation may cause temperature overshoot), the planar thermoelectric thin film device activates energy harvesting mode 306. The hot end, located at the center, has a higher thermal resistance, making it easier to accumulate heat, while the cold end has a lower thermal resistance, making it easier to dissipate heat. This enhances the temperature difference between the hot and cold ends, significantly improving the device's power generation performance based on the Seebeck effect. The energy is then stored through an energy storage device to power the device when it is cooled or to power other devices.

[0061] The aforementioned planar thermoelectric thin-film device can be integrated with the heat source chip of the semiconductor device under test, enabling real-time cooling of the chip's hot spots. Simultaneously, it can capture and store energy during periods when power is not required, and then use the energy to power active devices. This provides a new approach for achieving truly self-powered intelligent thermal management of electronic devices and advanced intelligent control in more complex and demanding scenarios.

Claims

1. A method for applying a planar thermoelectric thin-film device, characterized in that, The method includes: adjusting the input current or voltage according to the chip cooling requirements, so that the cold end and hot end of the planar thermoelectric thin film device appear at different positions on the thermoelectric arm, so that the planar thermoelectric thin film device can operate in cooling mode or energy capture mode respectively. The planar thermoelectric thin film device includes: an insulating substrate at the bottom layer, a metal bottom electrode on the insulating substrate, and P-type thermoelectric arms and N-type thermoelectric arms radially distributed on the metal bottom electrode, wherein the P-type thermoelectric arms and N-type thermoelectric arms are arranged at intervals around the center of the thermoelectric thin film device; the metal bottom electrode is also provided with a current or voltage input electrode and a ground electrode. The method includes: During the phase when chip power consumption and chip temperature rise rapidly, current or voltage is applied to the thermoelectric thin film device to activate the active cooling mode of the thermoelectric thin film device, so that the end of the thermoelectric arm of the thermoelectric thin film device closer to the center of the device is the cold end and the end farther away from the center of the device is the hot end, so that the chip can be cooled quickly. When the chip power consumption is low or when chip thermal management is not required, no current or voltage is input to the thermoelectric thin film device. At this time, the end of the thermoelectric arm of the thermoelectric thin film device that is closer to the central heating area of ​​the device is the hot end, and the end that is farther away from the central heating area of ​​the device is the cold end. This allows the thermoelectric thin film device to work in energy capture mode to capture energy and store the energy through an energy storage device, so as to provide power when the thermoelectric thin film device is cooled or to provide power to other active devices.

2. A method for fabricating a planar thermoelectric thin-film device, characterized in that, The method is implemented using standard integrated circuit manufacturing processes, including: S1: After organic cleaning of the insulating substrate material, photoresist is spin-coated onto it and photolithography is performed through a mask. S2: Deposit a metal thin film on an insulating substrate material and pattern the metal bottom electrode using a lift-off process or an etching process; S3: Heat the insulating substrate material to deposit P-type or N-type thermoelectric material, spin-coat photoresist, perform photolithography through a mask, and then use an etching process to complete the patterning of the P-type or N-type thermoelectric arm. S4: Heat the insulating substrate material to deposit N-type or P-type thermoelectric material, spin-coat photoresist, perform photolithography through a mask, and then use an etching process to pattern the N-type or P-type thermoelectric arm to obtain a planar thermoelectric thin film device structure. S5: Spin-coat photoresist onto the surface of a planar thermoelectric thin film device, perform photolithography through a mask, and bake to cure to form a protective layer; The planar thermoelectric thin film device includes: an insulating substrate located at the bottom layer, a metal bottom electrode located on the insulating substrate, and P-type thermoelectric arms and N-type thermoelectric arms located on the metal bottom electrode in a radially partitioned manner, wherein the P-type thermoelectric arms and N-type thermoelectric arms are arranged at intervals around the center of the thermoelectric thin film device; the metal bottom electrode is also provided with a current or voltage input electrode and a ground electrode.

3. The method for fabricating a planar thermoelectric thin-film device according to claim 2, characterized in that, The insulating substrate material is obtained by coating any one or more of the following: polyimide substrate, quartz substrate, mica substrate, glass substrate, silicone rubber substrate, silicone resin substrate, polyethylene terephthalate substrate, polyethylene naphthalate substrate, silicon-based substrate, silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, diamond substrate, sapphire substrate, aluminum oxide substrate, aluminum nitride substrate, beryllium oxide substrate, and silicon nitride substrate with an insulating medium.

4. The method for fabricating a planar thermoelectric thin-film device according to claim 2, characterized in that, The method for depositing metal thin films, N-type or P-type thermoelectric materials is any one of molecular beam epitaxy, pulsed laser deposition, metal-organic chemical vapor deposition, magnetron sputtering deposition, vacuum evaporation deposition, and electrochemical deposition.

5. The method for fabricating a planar thermoelectric thin-film device according to claim 2, characterized in that, The metal bottom electrode is made of any one or more of the following materials: copper, aluminum, gold, silver, chromium, nickel, titanium, cobalt, tin, zinc, bismuth, molybdenum, tungsten, iron, indium, niobium, antimony, manganese, lead, tantalum, yttrium, hafnium, vanadium, platinum, rhenium, palladium, iridium, rhodium, ruthenium, and their alloys.

6. The method for fabricating a planar thermoelectric thin-film device according to claim 2, characterized in that, The etching process can be either wet etching or dry etching.

7. The method for fabricating a planar thermoelectric thin-film device according to claim 2, characterized in that, The deposition thickness of the P-type or N-type thermoelectric material is 1 nm to 100 μm.

8. The method for fabricating a planar thermoelectric thin-film device according to claim 2, characterized in that, The P-type thermoelectric material and the N-type thermoelectric material are any one or more of the following: Bi2Te3-based binary or ternary materials, Sb2Te3-based binary or ternary materials, Pb2Te3-based binary or ternary materials, SnSe-based binary or ternary materials, Mg-based binary or ternary materials, Te-based binary or ternary materials, Sn-based binary or ternary materials, SiGe alloy materials, semi-Halles alloys, graphene, squartzite, or filled squartzite materials.

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