Magnetic random access memory and data writing and data reading method thereof, electronic device

Abstract

The application relates to a magnetic random memory (200) and a data writing and data reading method and electronic equipment thereof, relates to the technical field of storage, and can solve the problem of a large number of signal lines electrically connected with a peripheral control circuit in a 3D MRAM, which leads to wiring difficulty. The magnetic random memory (200) comprises a plurality of storage strings (101) arranged in a first direction and a second direction, each of the storage strings (101) comprises a plurality of first storage units (101A) stacked in sequence; the magnetic random memory (200) further comprises a first word line, a second word line, a source line, a first bit line and a plurality of first transistors (102); the plurality of first storage units (101A) located on the same layer are electrically connected with the same first word line; in the plurality of storage strings (101) arranged in the first direction, the plurality of first storage units (101A) of each of the storage strings (101) are electrically connected with the same source line through the first transistors (102), and the first storage units (101A) of the plurality of storage strings (101) arranged in the first direction are further electrically connected with the same first bit line; the gates of the plurality of first transistors (102) arranged in the second direction are electrically connected with the same second word line.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a magnetic random access memory and its data writing and reading methods, as well as electronic devices. Background Technology

[0002] The development of information technology has led to higher requirements for storage media. Compared with traditional semiconductor storage technology, magnetic random access memory (MRAM) is considered a high-density memory with great potential for large-scale application in the future due to its many excellent characteristics, such as non-volatility of stored data, fast read and write speed, unlimited erase and write life, and low read and write power consumption.

[0003] The core storage cell of MRAM is the magnetic tunnel junction (MTJ), which mainly consists of a free layer, a tunnel layer, and a reference layer. When writing data into the MTJ, the spin-transfer torque (STT) effect can be used to change the direction of the magnetic moment of the free layer, making the magnetic moments of the free layer parallel or antiparallel to those of the reference layer, thus writing first logic information such as "0" and second logic information such as "1". When reading data stored in the MTJ, the resistance of the MTJ can be used to determine whether the MTJ stores first or second logic information.

[0004] To improve the storage density of MRAM, expanding 2D (two-dimensional) storage to 3D (three-dimensional) storage has become the mainstream trend. Figure 1 This is a type of 3D MRAM consisting of stacked memory arrays with a cross-point structure. (Reference) Figure 1 Each memory cell in each layer of the memory array includes an MTJ and a selector connected in series with the MTJ. The upper and lower ends of the memory cell are electrically connected to a word line (WL) and a bit line (BL) that are perpendicular to each other, respectively. The conduction and disconnection of the selector are controlled by applying a voltage between the WL and BL that are electrically connected to the memory cell, thereby realizing read and write operations on the corresponding MTJ.

[0005] Figure 2a and Figure 2b These are side and top views of a 3D MRAM, respectively. Figure 2a and Figure 2bThe selection device in the circuit is an NPN transistor. The gate (P-terminal) of the NPN transistor is electrically connected to the ground line (WL), and the source (N-terminal) and drain (GND) are electrically connected to the MTJ and GND, respectively. Along the X-direction, a row of transistors is electrically connected to the same WL and ground line (GND). The MTJ is also electrically connected to the bottom line (BL). Along the Y-direction, a row of MTJs is electrically connected to the same bottom line (BL). When a read / write operation is required on a specific MTJ, a gate bias voltage is applied to the corresponding WL, causing the NPN transistor connected in series with the specific MTJ to conduct. A read / write voltage is then applied to the corresponding BL and GND to perform the read / write operation.

[0006] However, taking an N×N×M storage array as an example, for Figure 1 The 3D MRAM shown requires N BLs and N WLs for addressing and access control per layer. Adding a new layer requires at least N more BLs or WLs. If M layers of memory arrays are stacked in the Z direction, a total of N × (M+1) WLs and BLs are needed. Figure 2a and Figure 2b The 3D MRAM shown requires N BLs, N WLs, and N GNDs for addressing and access control per memory array layer. Adding another memory array layer requires an additional N WLs and N BLs or GNDs. If M memory array layers are stacked in the Z direction, a total of N×M WLs and N×(M+1) BLs and GNDs are needed. These BLs, WLs, and GNDs all need to be electrically connected to external control circuitry, which increases wiring complexity and wastes a significant amount of space, thus limiting the practicality of 3D MRAM. Summary of the Invention

[0007] The embodiments of this application provide a magnetic random access memory and a data writing and reading method thereof, as well as an electronic device, which can solve the problem that the large number of signal lines, such as word lines and bit lines, electrically connected to the peripheral control circuit in 3D MRAM leads to wiring difficulties.

[0008] To solve the above-mentioned technical problems, this application adopts the following technical solution.

[0009] In a first aspect, this application provides a magnetic random access memory (MRM) comprising multiple memory strings arrayed along a first direction and a second direction, wherein the first and second directions are not parallel, but may be perpendicular to each other, for example. Each memory string comprises multiple first memory cells stacked sequentially along a third direction; the third direction is perpendicular to the plane formed by the first and second directions. The MRM further comprises multiple first word lines, multiple second word lines, multiple source lines, multiple first bit lines, and multiple first transistors corresponding one-to-one with each memory string, such that the multiple first transistors are also arrayed along the first and second directions. Multiple first memory cells located on the same layer are electrically connected to the same first word line; in the multiple memory strings arranged along the first direction, the multiple first memory cells of each memory string are electrically connected to the same source line through the first transistors corresponding to that memory string, and the multiple first memory cells of the multiple memory strings arranged along the first direction are also electrically connected to the same first bit line; the gates of the multiple first transistors arranged along the second direction are electrically connected to the same second word line.

[0010] Since multiple first memory cells located on the same layer are electrically connected to the same first word line, that is, multiple first memory cells located on the same layer share a first word line, and the first word line can be used for addressing, a first word line can control multiple first memory cells located on the same layer to be in a conducting state when the magnetic random access memory is performing read and write operations. If each memory string includes M first memory cells stacked in sequence, that is, the magnetic random access memory includes M memory layers, then M first word lines are needed to control the M memory layers respectively. It can be understood that these M first word lines can be led from the outside of the memory array to the plane where the peripheral control circuit is located through metal wires, thereby realizing selective operation of the first memory cells in different memory layers, such as controlling the conduction or disconnection of the first memory cells in different memory layers.

[0011] Based on this, multiple memory strings arranged along the first direction share a source line and a first bit line, and multiple memory strings arranged along the second direction share a second word line. In the case where the magnetic random access memory includes P columns of memory strings arranged along the first direction and Q columns of memory strings arranged along the second direction, the magnetic random access memory includes P second word lines, Q source lines, and Q first bit lines.

[0012] Compared to existing technologies, taking an N×N×M memory array as an example, each memory layer requires N BLs and N WLs. If the magnetic random access memory includes M memory layers, it requires (M+1)×N BLs and WLs (i.e., (M+1)×N signal lines), or N×M WLs, and N×(M+1) BLs and GNDs (i.e., (2M+1)×N signal lines). In this application, multiple first memory cells located in the same layer share a first word line, multiple memory strings arranged along the first direction share a source line and a first bit line, and multiple memory strings arranged along the second direction share a second word line. Therefore, if the magnetic random access memory includes M memory layers, and the magnetic random access memory has P columns of memory strings arranged along the first direction and Q columns of memory strings arranged along the second direction, it requires M first word lines, P second word lines, Q source lines, and Q first bit lines, i.e., M+P+2Q signal lines. Based on this, it can be seen that the number of signal lines (including the first word line, source line, first bit line, and second word line) in the magnetic random access memory provided in this application is significantly reduced. This significantly reduces the number of signal lines that are electrically connected to the peripheral control circuit, thereby reducing the wiring difficulty and saving the area occupied by the wiring.

[0013] In one possible implementation, each memory string further includes a plurality of second memory cells corresponding one-to-one with each first memory cell; the corresponding first and second memory cells are located on the same layer; the plurality of first and second memory cells located on the same layer are electrically connected to the same first word line. The magnetic random access memory (RAM) further includes a plurality of second bit lines, and the plurality of second memory cells in the plurality of memory strings arranged along a first direction are respectively electrically connected to the same first bit line and the same second bit line. The RAM also includes a plurality of second transistors corresponding one-to-one with each memory string; each first bit line is electrically connected to a plurality of first and second memory cells in the memory string corresponding to the second transistor via the second transistor; the gates of the plurality of first transistors and the plurality of second transistors arranged along a second direction are electrically connected to the same second word line; and / or, the RAM further includes a plurality of third transistors corresponding one-to-one with each memory string; each second bit line is electrically connected to a plurality of second memory cells in the memory string corresponding to the third transistor via the third transistor; the gates of the plurality of first transistors and the plurality of third transistors arranged along the second direction are electrically connected to the same second word line. Since multiple first memory cells and multiple second memory cells of multiple memory strings arranged along the first direction share a single bit line, the number of bit lines, i.e. the number of signal lines, is further reduced. This further reduces the number of signal lines electrically connected to the peripheral control circuit, thereby further reducing the wiring difficulty and saving the area occupied by wiring.

[0014] In one possible implementation, each memory string further includes a plurality of second memory cells corresponding one-to-one with each first memory cell; the corresponding first memory cells and second memory cells are located on the same layer; the plurality of first memory cells and the plurality of second memory cells located on the same layer are electrically connected to the same first word line. The magnetic random access memory (RAM) further includes multiple second bit lines, and multiple second memory cells of multiple memory strings arranged along a first direction are electrically connected to the same source line and the same second bit line, respectively; wherein, each source line is electrically connected to multiple first memory cells and multiple second memory cells in the memory string corresponding to the first transistor through a first transistor; the RAM also includes multiple second transistors corresponding to each memory string, each first bit line is electrically connected to multiple first memory cells of the memory string corresponding to the second transistor through a second transistor, and the gates of the multiple first transistors and multiple second transistors arranged along a second direction are electrically connected to the same second word line; and / or, the RAM also includes multiple third transistors corresponding to each memory string, each second bit line is electrically connected to multiple second memory cells of the memory string corresponding to the third transistor through a third transistor; the gates of the multiple first transistors and multiple third transistors arranged along the second direction are electrically connected to the same second word line. Since multiple first memory cells and multiple second memory cells of multiple memory strings arranged along the first direction share a single source line, the number of source lines, i.e. the number of signal lines, is further reduced. This further reduces the number of signal lines electrically connected to the peripheral control circuit, thereby further reducing the wiring difficulty and saving the area occupied by wiring.

[0015] In one possible implementation, each first memory cell includes a fourth transistor and a first magnetic tunnel junction (MTJ) connected in series with the fourth transistor; the gate of the fourth transistor is electrically connected to a first word line; the fourth transistor is also electrically connected to a source line through the first transistor, and the first MTJ is electrically connected to a first bit line; alternatively, the fourth transistor is also electrically connected to the first bit line, and the first MTJ is electrically connected to the source line through the first transistor. When the fourth transistor is turned on, current can flow through the first MTJ, thereby allowing data to be written to or read from the first MTJ.

[0016] In one possible implementation, each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; the gate of the fifth transistor is electrically connected to a first word line; the fifth transistor is electrically connected to a first bit line, and the second MTJ is electrically connected to a second bit line; or, the fifth transistor and the second bit line are electrically connected, and the second MTJ is electrically connected to the first bit line. When the fifth transistor is turned on, current can flow through the second MTJ, thereby allowing data to be written to or read from the second MTJ.

[0017] In one possible implementation, each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; the gate of the fifth transistor is electrically connected to a first word line; the fifth transistor is electrically connected to a source line, and the second MTJ is electrically connected to a second bit line; or, the fifth transistor and the second bit line are electrically connected, and the second MTJ is electrically connected to a source line. When the fifth transistor is turned on, current can flow through the second MTJ, thereby allowing data to be written to or read from the second MTJ.

[0018] In one possible implementation, the first transistor is a back-end-of-line (BEOL) transistor, such as a thin-film transistor, polycrystalline silicon transistor, amorphous silicon transistor, or carbon nanotube transistor. Since the electrical properties (e.g., resistance, switching current, turn-on voltage, durability) and fabrication process (e.g., fabrication temperature, typically <400°C) of BEOL transistors are compatible with the electrical properties and fabrication process of MTJs, using BEOL transistors as the gating device in this application is beneficial for improving the performance of the magnetic random access memory (MRMemory) and reducing the fabrication difficulty of the MRMemory. Furthermore, BEOL transistors can significantly increase the storage density of the MRMemory and reduce leakage current. Additionally, when the first transistor is a BEOL transistor, the peripheral control circuitry, such as the processor (e.g., CPU), can be placed below the memory string, i.e., the peripheral control circuitry and the processor (e.g., CPU) are closer to the substrate relative to the memory string, thereby reducing the chip area.

[0019] In one possible implementation, at least one of the second, third, fourth, and fifth transistors is a back-end transistor, such as a thin-film transistor, polycrystalline silicon transistor, amorphous silicon transistor, or carbon nanotube transistor. The technical effects of having the first transistor as a back-end transistor can be referred to above, and will not be repeated here.

[0020] In one possible implementation, the source and drain of the first transistor are arranged along the direction in which multiple first memory cells are stacked in the memory string, i.e., the first transistor is a vertical transistor. Since the first transistor is a vertical transistor, the area occupied by the first transistor can be reduced, thereby further increasing the storage density of the magnetic random access memory.

[0021] In one possible implementation, the source and drain of at least one of the second, third, fourth, and fifth transistors are arranged along the direction in which the plurality of first memory cells are stacked in the memory string; that is, at least one of the second, third, fourth, and fifth transistors is a vertical transistor. The technical effects of having a vertical transistor as described above can be referenced and will not be repeated here.

[0022] In one possible implementation, the first transistor is a planar transistor, and the source and drain of the first transistor are arranged in a direction perpendicular to the stacking of multiple first memory cells in the memory string.

[0023] In one possible implementation, at least one of the second, third, fourth, and fifth transistors is a planar transistor, and the source and drain of the planar transistor are arranged in a direction perpendicular to the stacking of the plurality of first memory cells in the memory string.

[0024] In one possible implementation, the magnetic random access memory further includes a substrate; the first transistor, the second word line, the source line, and the first bit line are positioned close to the substrate relative to the memory string, i.e., the first transistor, the second word line, the source line, and the first bit line are disposed below the memory string; alternatively, the memory string is positioned close to the substrate relative to the first transistor, the second word line, the source line, and the first bit line, i.e., the first transistor, the second word line, the source line, and the first bit line are disposed above the memory string. The positions of the first transistor, the second word line, the source line, and the first bit line can be flexibly configured according to wiring requirements, etc.

[0025] In one possible implementation, the magnetic random access memory further includes a substrate; the second transistor, the third transistor, and the second bit line are positioned close to the substrate relative to the memory string, i.e., the second transistor, the third transistor, and the second bit line are located below the memory string; alternatively, the memory string is positioned close to the substrate relative to the second transistor, the third transistor, and the second bit line, i.e., the second transistor and the third transistor are located above the memory string. The positions of the second transistor, the third transistor, and the second bit line can be flexibly configured according to wiring requirements, etc.

[0026] Secondly, an electronic device is provided, comprising a printed circuit board and the magnetic random access memory (RAM) provided in the first aspect; the printed circuit board and the RAM are electrically connected. Since this electronic device has the same technical effects as the RAM provided in the first aspect, reference can be made to the relevant description in the first aspect, which will not be repeated here.

[0027] Thirdly, a data writing method for a magnetic random access memory (MRM) is provided. The MRM can be the MRM provided in the first aspect above. Each first memory cell in the MRM includes a fourth transistor and a first MTJ connected in series with the fourth transistor. The data writing method includes: First, a first word line electrically connected to the first memory cell to be written receives a first gate bias voltage. The first gate bias voltage controls multiple first memory cells located on the same layer as the first memory cell to be written to be in a conducting state, thus selecting a certain layer of first memory cells. Next, a second word line corresponding to the first memory cell to be written receives a second gate bias voltage. The second gate bias voltage controls multiple first transistors located in the same column as the first transistor to be written along a second direction, thus selecting a column of first memory cells arranged along the second direction. Next, one of the source line and the first bit line electrically connected to the first memory cell to be written receives a write voltage, and the other receives a ground voltage, thus selecting a specific first memory cell for data writing. Since current flows through the first memory cell to be written, data writing to the first MTJ in the first memory cell to be written can be achieved. Since the data writing method of the magnetic random access memory has the same technical effect as the magnetic random access memory provided in the first aspect above, the relevant description in the first aspect above can be referred to, and will not be repeated here.

[0028] In one possible implementation, each memory string further includes a plurality of second memory cells, each second memory cell being electrically connected to a first bit line and a second bit line; in this case, the plurality of first memory cells and the plurality of second memory cells in the plurality of memory strings arranged along the second direction share the first bit line. The above data writing method further includes: First, a first word line electrically connected to the second memory cell to be written receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in a plurality of first memory cells and the fifth transistor in a plurality of second memory cells located in the same layer as the second memory cell to be written to be in a conducting state, thus selecting a certain layer of first memory cells and second memory cells; Next, a second word line corresponding to the second memory cell to be written receives a second gate bias voltage. The second gate bias voltage is used to control the plurality of first transistors, plurality of second transistors and plurality of third transistors located in the same column along the second direction and electrically connected to the second memory cell to be written to be in a conducting state, thus selecting a column of first memory cells and second memory cells arranged along the second direction; Next, one of the first bit line and the second bit line electrically connected to the second memory cell to be written receives a write voltage and the other receives a ground voltage. The source line electrically connected to the first memory cell corresponding to the second memory cell to be written to is in a floating state, thus selecting a specific second memory cell for data writing. Since there is current flowing through the second memory cell to be written, data writing to the second MTJ in the second memory cell to be written can be realized.

[0029] In one possible implementation, each memory string further includes a plurality of second memory cells, each second memory cell being electrically connected to a source line and a second bit line; in this case, the plurality of first memory cells and the plurality of second memory cells in the plurality of memory strings arranged along the second direction share the source line. The above data writing method further includes: First, the first word line electrically connected to the second memory cell to be written receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in the multiple first memory cells and the fifth transistor in the multiple second memory cells located in the same layer as the second memory cell to be written to be in the on state, so that a certain layer of first memory cells and second memory cells can be selected; Next, the second word line corresponding to the second memory cell to be written receives a second gate bias voltage. The second gate bias voltage is used to control the multiple first transistors, multiple second transistors and multiple third transistors located in the same column along the second direction and electrically connected to the second memory cell to be written to be turned on, so that a column of first memory cells and second memory cells arranged along the second direction can be selected; Next, one of the source line and the second bit line electrically connected to the second memory cell to be written receives a write voltage and the other receives a ground voltage. The first bit line electrically connected to the first memory cell corresponding to the second memory cell to be written to is in a floating state, so that a specific second memory cell can be selected for data writing. Since there is current flowing through the second memory cell to be written, the data writing of the second MTJ in the second memory cell to be written can be realized.

[0030] Fourthly, a data reading method for a magnetic random access memory (MRMemory) is provided. The MRMemory can be the MRMemory provided in the first aspect above. Each first memory cell in the MRMemory includes a fourth transistor and a first MTJ connected in series with the fourth transistor. The data reading method includes: firstly, a first word line electrically connected to the first memory cell to be read receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in a plurality of first memory cells located in the same layer as the first memory cell to be read to be in a conducting state, thus selecting a certain layer of first memory cells; nextly, a second word line corresponding to the first memory cell to be read receives a second gate bias voltage. The voltage setting is used to control the conduction of multiple first transistors located in the same column as the first transistors electrically connected to the first memory cell to be read along the second direction, thus selecting a column of first memory cells arranged along the second direction. Next, one of the source line and the first bit line electrically connected to the first memory cell to be read receives the read voltage, and the other receives the ground voltage, thus selecting a specific first memory cell for data reading. Since current flows only through the first MTJ of the first memory cell to be read, the resistance of the first MTJ in the first memory cell to be read can be determined based on the magnitude of the current, and thus it can be determined whether the first MTJ of the first memory cell to be read stores the first logic information "0" or the second logic information "1". Since the data reading method of the magnetic random access memory has the same technical effect as the magnetic random access memory provided in the first aspect above, the relevant description in the first aspect above can be referred to, and will not be repeated here.

[0031] In one possible implementation, each memory string further includes multiple second memory cells, each second memory cell being electrically connected to a first bit line and a second bit line; each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; in this case, multiple first memory cells and multiple second memory cells in multiple memory strings arranged along the second direction share a first bit line. The above data reading method further includes: firstly, a first word line electrically connected to the second memory cell to be read receives a first gate bias voltage, the first gate bias voltage being used to control the fourth transistor in multiple first memory cells and the fifth transistor in multiple second memory cells located in the same layer as the second memory cell to be read to be in a conducting state, thus selecting a certain layer of first memory cells and second memory cells; nextly, a second word line corresponding to the second memory cell to be read receives a second gate bias voltage, the second gate bias voltage being used to control multiple first transistors, multiple second transistors and multiple third transistors located in the same column along the second direction and electrically connected to the second memory cell to be read. When the body tube is turned on, a column of first and second storage cells arranged along the second direction can be selected. Next, one of the first and second bit lines electrically connected to the second storage cell to be read receives the read voltage, and the other receives the ground voltage. The source line electrically connected to the first storage cell corresponding to the second storage cell to be read is in a floating state. This allows a specific second storage cell to be selected for data reading. Since current flows only through the second storage cell to be read, the resistance of the second MTJ in the second storage cell to be read can be determined based on the magnitude of the current. Thus, it can be determined whether the second MTJ of the second storage cell to be read stores the first logic information "0" or the second logic information "1".

[0032] In one possible implementation, each memory string further includes multiple second memory cells, each second memory cell being electrically connected to a source line and a second bit line; each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; in this case, multiple first memory cells and multiple second memory cells in multiple memory strings arranged along the second direction share a single source line. The data reading method further includes: firstly, a first word line electrically connected to the second memory cell to be read receives a first gate bias voltage, the first gate bias voltage being used to control the fourth transistor in multiple first memory cells located in the same layer as the second memory cell to be read and the fifth transistor in multiple second memory cells to be in a conducting state, thus selecting a certain layer of first memory cells and second memory cells; nextly, a second word line corresponding to the second memory cell to be read receives a second gate bias voltage, the second gate bias voltage being used to control multiple first transistors, multiple second transistors, and multiple third transistors located in the same column as the second transistor to be read along the second direction. When the transistor is turned on, a column of first and second memory cells arranged along the second direction can be selected. Next, one of the source line and the second bit line electrically connected to the second memory cell to be read receives the read voltage, and the other receives the ground voltage. The first bit line electrically connected to the first memory cell corresponding to the second memory cell to be read is in a floating state. This allows a specific second memory cell to be selected for data reading. Since current flows only through the second memory cell to be read, the resistance of the second MTJ in the second memory cell to be read can be determined based on the magnitude of the current. Thus, it can be determined whether the second MTJ of the second memory cell to be read stores the first logic information "0" or the second logic information "1". Attached Figure Description

[0033] Figure 1 A schematic diagram of a 3D MRAM structure provided for the prior art; Figure 2a A side view diagram of a 3D MRAM structure provided for the prior art; Figure 2b A top view diagram of a 3D MRAM structure provided for the prior art; Figure 3 A schematic diagram of the structure of an electronic device provided for an embodiment of this application; Figure 4 A schematic diagram of the structure of a magnetic random access memory provided for an embodiment of this application; Figure 5 A schematic diagram of the structure of a magnetic random access memory is provided for another embodiment of this application; Figure 6 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 7 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 8 A schematic diagram of the structure of the first MTJ provided for an embodiment of this application; Figure 9 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 10 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 11 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 12 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 13 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 14 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 15 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 16 A schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application; Figure 17 This is a schematic diagram of the structure of a magnetic random access memory provided in another embodiment of this application.

[0034] Reference numerals: 100-Electronic device; 11-Storage device; 12-Processor; 13-Input device; 14-Output device; 10-Storage array; 20-Decoder; 30-Driver; 40-Timing controller; 50-Buffer; 60-Input / output driver; 101-Storage string; 101A-First storage unit; 101B-Second storage unit; 102-First transistor; 103-Second transistor; 104-Third transistor; 111-External memory; 112-Internal memory; 121-Arithmetic unit; 122-Controller; 200-Magnetic random access memory; 1011-Fourth transistor; 1012-First MTJ; 1013-Fifth transistor; 1014-Second MTJ. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0036] In the following description, the terms "first," "second," etc., are used for ease of description only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0037] In the embodiments of this application, unless otherwise expressly specified and limited, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0038] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0039] In the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0040] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, and vehicle-mounted equipment, etc.; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0041] Figure 3 This is a schematic diagram of the architecture of an electronic device provided as an example of an embodiment of this application. Figure 3 As shown, the electronic device 100 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will understand that... Figure 3The structure of the electronic device shown does not constitute a limitation on the electronic device, and the electronic device 100 may include more than Figure 3 The components shown may have more or fewer components, or may be combined as follows: Figure 3 Some of the components shown, or those that can be used with, for example Figure 3 The component arrangements shown are different.

[0042] The storage device 11, processor 12, input device 13 and output device 14 are described below.

[0043] Storage device 11 is used to store software programs and modules. Storage device 11 mainly includes a program storage area and a data storage area. The program storage area can store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area can store data created based on the use of the electronic device (such as audio data, image data, phone book, etc.). Furthermore, storage device 11 includes external storage 111 and internal storage 112. Data stored in external storage 111 and internal storage 112 can be transferred between each other. External storage 111 includes, for example, a hard disk, USB flash drive, floppy disk, etc. Internal storage 112 includes, for example, random access memory (RAM), read-only memory (ROM), etc. RAM can include, for example, phase-change RAM, magnetic random access memory (MRM), or ferroelectric RAM, etc.

[0044] The processor 12 is the control center of the electronic device 100. It connects various parts of the electronic device 100 via various interfaces and lines. By running or executing software programs and / or modules stored in the storage device 11, and by calling data stored in the storage device 11, it performs various functions and processes data of the electronic device 100, thereby providing overall monitoring of the electronic device 100. The processor 12 may include, for example, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a flight controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU), etc. The aforementioned application processor may be, for example, a central processing unit (CPU). Different types of processors can be set up independently or integrated together. For example, the application processor and the modem processor can be integrated together; the application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the aforementioned modem processor and application processor can also be set up independently. Figure 3 Taking the processor 12, which includes an arithmetic logic unit (ALU) 121 and a control unit 122, as an example, the ALU 121 retrieves data stored in the internal memory 112, processes the data stored in the internal memory 112, and typically sends the processed result back to the internal memory 112. The control unit 122 can control the ALU 121 to process the data, and the control unit 122 can also control the external memory 111 and the internal memory 112 to write or read data.

[0045] Input device 13 is used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. For example, input device 13 may include a touchscreen and other input devices. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control buttons, power switch buttons, etc.), trackball, mouse, joystick, etc. The controller 122 in the processor 12 described above can also be used to control input device 13 to receive input signals. Furthermore, the input numeric or character information received by input device 13, and the key signal inputs generated related to user settings and function control of the electronic device, can be stored in internal memory 112.

[0046] Output device 14 is used to output signals corresponding to the data input by input device 13 and stored in internal memory 112. For example, output device 14 outputs audio signals or video signals. The controller 122 in the processor 12 can also be used to control the output signals of output device 14.

[0047] It should be noted that, Figure 3 The thick arrows in the diagram are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a single arrow between input device 13 and internal memory 112 indicates that data received by input device 13 is transmitted to internal memory 112. As another example, a double arrow between arithmetic unit 121 and internal memory 112 indicates that data stored in internal memory 112 can be transmitted to arithmetic unit 121, and data processed by arithmetic unit 121 can be transmitted to internal memory 112. Figure 3 The thin arrows in the diagram indicate components that the controller 122 can control. For example, the controller 122 can control external memory 111, internal memory 112, arithmetic unit 121, input device 13, and output device 14.

[0048] Based on the above, the electronic device 100 provided in this application embodiment also includes printed circuit boards (PCBs). Some electronic devices in the electronic device 100, such as internal memory 112 or processor 12, can be disposed on the PCB, and the internal memory 112, processor 12, etc. are electrically connected to the PCB.

[0049] This application embodiment also provides a magnetic random access memory, which can be applied to the above-described electronic device 100, for example, it can be used as the internal memory 112 in the above-described electronic device 100.

[0050] like Figure 4 As shown, the magnetic random access memory 200 includes a storage array 10, which includes multiple storage cells, word lines, source lines, bit lines, etc. Each storage cell can be used to store 1 bit or more bits of data. In some examples, such as Figure 4 As shown, the magnetic random access memory 200 also includes a decoder 20, a driver 30, a timing controller 40, a register 50, and an input / output driver 60.

[0051] exist Figure 4In the magnetic random access memory 200 shown, decoder 20 decodes the received address to determine the memory cell to be accessed. Driver 30 controls the levels of source lines, bit lines, and word lines based on the decoding result generated by decoder 20, thereby enabling access to the specified memory cell. Buffer 50 buffers the read data, for example, using a first-in-first-out (FIFO) buffering method. Timing controller 40 controls the timing of buffer 50 and controls driver 30 to drive the source lines, bit lines, and word lines in the memory array. Input / output driver 60 drives transmission signals, such as driven received data signals and driven data signals to be transmitted, enabling long-distance transmission of data signals.

[0052] The aforementioned memory array 10, decoder 20, driver 30, timing controller 40, buffer 50, and input / output driver 60 can be integrated into one chip or into multiple chips respectively.

[0053] The following provides two specific embodiments to illustrate the structure of the above-described storage array 10.

[0054] Example 1 like Figure 5 As shown, the storage array 10 includes multiple storage strings 101 distributed in an array. Specifically, the multiple storage strings 101 are periodically repeated along a first direction X and a second direction Y, wherein the first direction X and the second direction Y are not parallel. The non-parallelism of the first direction X and the second direction Y can be that the first direction X and the second direction Y are perpendicular, or that the angle between the first direction X and the second direction Y is an acute angle. Figure 5 The following is an illustration of a storage array 10 comprising four storage strings 101.

[0055] Here, the number of storage strings 101 arranged along the first direction X and the number of storage strings 101 arranged along the second direction Y are not limited and can be adjusted as needed.

[0056] It is understood that the magnetic random access memory 200 also includes a substrate, and the memory array 10, etc., can be disposed on the substrate. The substrate is not shown in the accompanying drawings of this application. Here, the first direction X and the second direction Y are directions parallel to the substrate.

[0057] Each of the aforementioned storage strings 101 includes a plurality of first storage cells 101A stacked sequentially, as referenced. Figure 5 In each storage string 101, multiple first storage cells 101A are stacked sequentially along the third direction Z, wherein the third direction Z can be perpendicular to the plane formed by the first direction X and the second direction Y, that is, the third direction Z is perpendicular to the substrate. Figure 5The illustration takes as an example that each storage string 101 includes two first storage units 101A stacked in sequence.

[0058] Here, the number of first storage cells 101A stacked along the third direction Z of each storage string 101 can be adjusted as needed.

[0059] It should be noted that in the multiple storage strings 101, each first storage cell 101A of each storage string 101 is located on the same layer as a first storage cell 101A in any other storage string 101. That is, the storage array 10 includes multiple storage layers stacked along the third direction Z, and each storage layer includes multiple first storage cells 100A distributed in the array. Based on this, it can be seen that in this application, the multiple first storage cells 101A in the storage array 10 are 3D stacked, that is, the first storage cells 101A are stacked along the first direction X, the second direction Y, and the third direction Z respectively. Therefore, the magnetic random access memory 200 provided in this application embodiment can also be called a 3D magnetic random access memory. Compared with 2D magnetic random access memory, 3D magnetic random access memory can significantly improve the storage density of magnetic random access memory 200.

[0060] Please continue to refer to this. Figure 5 In some examples, each of the first memory cells 101A described above includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011.

[0061] It should be noted that in each first memory cell 101A, the positional relationship between the fourth transistor 1011 and the first MTJ 1012 can be one of the following two: First, as shown... Figure 5 As shown, the first MTJ1012 is disposed on the fourth transistor 1011, that is, the fourth transistor 1011 is closer to the substrate than the first MTJ1012. The second type, as... Figure 6 As shown, the fourth transistor 1011 is disposed on the first MTJ 1012, that is, the first MTJ 1012 is closer to the substrate than the fourth transistor 1011.

[0062] The aforementioned fourth transistor 1011 includes a gate (G), a source (S), and a drain (D). Furthermore, the fourth transistor 1011 can be either an N-type transistor or a P-type transistor.

[0063] Building upon this, the fourth transistor 1011 can be, for example, a back-end-of-line (BEOL) transistor. A BEOL transistor is a transistor compatible with semiconductor back-end processes, and its fabrication temperature is generally no higher than 400°C. BEOL transistors can be, for example, thin-film transistors, polycrystalline silicon transistors, amorphous silicon transistors, or carbon nanotube transistors. It is understandable that the aforementioned fourth transistor 1011 can also be a front-end-of-line (FEOL) transistor, i.e., a transistor fabricated using front-end processes. For example, it can be a metal-oxide-semiconductor field-effect transistor (MOSFET), which can be integrated with the MTJ via wafer bonding or other methods.

[0064] Because the electrical properties (e.g., resistance, switching current, turn-on voltage, durability) and fabrication process (e.g., fabrication temperature, typically <400°C) of BEOL transistors are compatible with those of MTJs, the use of BEOL transistors as the gating device in this application is beneficial for improving the performance of the magnetic random access memory 200 and reducing its fabrication difficulty. Furthermore, BEOL transistors can significantly increase the storage density of the magnetic random access memory 200 and reduce leakage current.

[0065] Based on this, such as Figure 5 and Figure 6 As shown, the fourth transistor 1011 can be a planar transistor, meaning that the source and drain of the fourth transistor 1011 are arranged along a direction perpendicular to the stacking of multiple first memory cells 101A in the memory string 101. In other words, the source and drain of the fourth transistor 1011 are arranged along a direction parallel to the plane formed by the first direction X and the second direction Y. Figure 7 As shown, the fourth transistor 1011 can also be a vertical transistor, that is, the source and drain of the fourth transistor 1011 are arranged along the direction of the stacking of multiple first memory cells 101A in the memory string 101, that is, the source and drain of the fourth transistor 1011 are arranged along the third direction Z.

[0066] When the fourth transistor 1011 is a vertical transistor, the area occupied by the fourth transistor 1011 can be reduced, thereby further increasing the storage density of the magnetic random access memory 200.

[0067] like Figure 8As shown, each first MTJ1012 includes a reference layer, a tunneling layer, and a free layer stacked sequentially. The materials of the reference layer and the free layer can be, for example, at least one of a cobalt-iron-boron (CoFeB) alloy, a cobalt-iron (CoFe) alloy, or a nickel-iron-cobalt (NiFeCo) alloy. The material of the tunneling layer can be, for example, a magnesium oxide (MgO) alloy.

[0068] To ensure that the magnetization direction of the reference layer remains unchanged, therefore in some examples, such as Figure 8 As shown, each first MTJ1012 may further include a pinning layer disposed on the side of the reference layer away from the tunneling layer, the pinning layer being able to pin the magnetization direction of the reference layer in a certain direction and keep it unchanged.

[0069] The material of the aforementioned pinning layer may include, for example, a rare earth transition metal alloy. Alternatively, the pinning layer may employ a SAF (synthetic antiferromagnetic, also known as artificial antiferromagnetic) structure. The SAF structure comprises a first composite layer, a non-magnetic layer, and a second composite layer stacked sequentially. Both the first and second composite layers are composed of alternating layers of ferromagnetic and metallic layers. For example, the first and second composite layers may consist of alternating layers of cobalt (Co) and platinum (Pt) stacked along the stacking direction of the layers in the first MTJ1012. The material of the non-magnetic layer includes at least one of platinum, tantalum, copper, iridium, ruthenium, and tungsten.

[0070] It is understandable that the structure of the first MTJ1012 includes, but is not limited to, Figure 8 The structure shown.

[0071] The following section uses a first storage unit 101A as an example to introduce the data writing and data reading principles of the magnetic random access memory 200.

[0072] In this application, the data writing of the first MTJ1012 utilizes the STT effect. Specifically, when the current passes through the reference layer of the first MTJ1012, it is spin-polarized. The resulting spin-polarized current interacts with the local magnetic moment of the free layer when it passes through the free layer, thereby changing the magnetization direction of the free layer. This changes the magnetization direction of the free layer to be parallel or antiparallel to the magnetization direction of the reference layer, i.e., data is written. When the magnetization direction of the free layer is parallel to the magnetization direction of the reference layer, it indicates that the first MTJ1012 has written first logic information; when the magnetization direction of the free layer is antiparallel to the magnetization direction of the reference layer, it indicates that the first MTJ1012 has written second logic information. One of the first logic information and the second logic information can be represented by "0" and the other by "1". The following explanation uses "0" for the first logic information and "1" for the second logic information as an example.

[0073] It should be noted that the direction of current flowing through the first MTJ1012 includes current flowing from the reference layer to the free layer and current flowing from the free layer to the reference layer. When the current flows from the free layer to the reference layer, the magnetization direction of the free layer is parallel to the magnetization direction of the reference layer; when the current flows from the reference layer to the free layer, the magnetization direction of the free layer is antiparallel to the magnetization direction of the reference layer.

[0074] The data reading of the first MTJ1012 utilizes the TMR (tunneling magneto resistance) effect. Specifically, when the magnetization direction of the free layer is parallel to the magnetization direction of the reference layer, the first MTJ1012 is in a low-resistance state; when the magnetization direction of the free layer is antiparallel to the magnetization direction of the reference layer, the first MTJ1012 is in a high-resistance state. Therefore, by detecting the resistance of the first MTJ1012, it can be determined whether the first MTJ1012 stores the first logic information "0" or the second logic information "1".

[0075] It should be understood that the source or drain of the fourth transistor 1011 is electrically connected to the first MTJ 1012. Furthermore, the free layer in the first MTJ 1012 may be closer to the fourth transistor 1011 relative to the reference layer, or the reference layer in the first MTJ 1012 may be closer to the fourth transistor 1011 relative to the free layer.

[0076] To enable read and write operations on the first storage cell 101A in storage string 101, please refer to [the relevant documentation / reference]. Figure 5 The storage array 10 also includes: multiple first word lines wl (e.g., wl1, wl2, etc.), multiple second word lines WL (e.g., WL1, WL2, etc.), multiple source lines SL (e.g., SL1, SL2, etc.), multiple first bit lines BL (e.g., BL1, BL2, etc.), and multiple first transistors 102 corresponding one-to-one with each storage string 101.

[0077] Understandably, word lines are typically used to control the on / off state of transistors. When a transistor is on, it is used for addressing, such as selecting a specific memory cell layer or column. For example, when a word line is used to select a memory cell layer, all transistors in that layer of memory electrically connected to the word line are in the on state. Source lines and bit lines are typically used to provide data voltage for read / write operations.

[0078] Here, the second letter line WL can extend along the second direction Y, and the first letter line BL and the source line SL can extend along the first direction X.

[0079] Since multiple storage strings 101 are distributed along the first direction X and the second direction Y, and multiple storage strings 101 correspond one-to-one with multiple first transistors 102, multiple first transistors 102 are also distributed along the first direction X and the second direction Y.

[0080] It should be noted that the structures and types of other transistors in this application, such as the first transistor 102, the second transistor, the third transistor, and the fifth transistor, can refer to the aforementioned fourth transistor 1011, and will not be repeated below.

[0081] Here, the first transistor 102 and the transistors in the memory string 101, such as the fourth transistor 1011, can be fabricated using the same process or different processes.

[0082] Multiple first memory cells 101A located on the same layer are electrically connected to the same first word line wl. Specifically, the gate of the fourth transistor 1011 in the multiple first memory cells 101A located on the same layer is electrically connected to the same first word line wl. In this way, each first word line wl can control the fourth transistor 1011 in the multiple first memory cells 101A located on the same layer to be turned on or off simultaneously.

[0083] In a plurality of memory strings 101 arranged along the first direction X, a plurality of first memory cells 101A in each memory string 101 are electrically connected to the same source line SL via a first transistor 102 corresponding to that memory string 101. All first memory cells 101A in the plurality of memory strings 101 arranged along the first direction X are also electrically connected to the same first bit line BL. Here, all first memory cells 101A in the plurality of memory strings 101 arranged along the first direction X can be directly electrically connected to the same first bit line BL, or they can be electrically connected to the same first bit line BL via other electronic components such as transistors. Furthermore, the gates of the plurality of first transistors 102 arranged along the second direction Y are electrically connected to the same second word line WL. In this way, each second word line WL can be controlled to be electrically connected to it, and the plurality of first transistors 102 arranged along the second direction Y can be simultaneously turned on or off.

[0084] When the first memory cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, the connection relationship between the fourth transistor 1011, the first MTJ 1012 and the first bit line BL and the source line SL can include the following two optional implementation methods. The first optional implementation method is as follows: Figure 5As shown, in the plurality of memory strings 101 arranged along the first direction X, the plurality of first MTJs 1012 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to that memory string 101, and the fourth transistor 1011 of the plurality of memory strings 101 arranged along the first direction X is electrically connected to the same first bit line BL. It can be understood that one of the source and drain of the first transistor 102 is electrically connected to the first MTJ 1012 and the other is electrically connected to the source line SL, and one of the source and drain of the fourth transistor 1011 is electrically connected to the first MTJ 1012 and the other is electrically connected to the first bit line BL.

[0085] The second optional implementation method: such as Figure 9 As shown, in the plurality of memory strings 101 arranged along the first direction X, the plurality of fourth transistors 1011 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to that memory string 101, and the first MTJ 1012 of the plurality of memory strings 101 arranged along the first direction X is electrically connected to the same first bit line BL. It can be understood that one of the source and drain of the fourth transistor 1011 is electrically connected to the first MTJ 1012, and the other is electrically connected to the source or drain of the first transistor 102, and the source or drain of the first transistor 102 is electrically connected to the source line SL.

[0086] Based on this, in some examples, such as Figure 10 As shown, the magnetic random access memory 200 may further include a plurality of second transistors 103 corresponding one-to-one with each memory string 101. In the plurality of memory strings 101 arranged along the first direction X, a plurality of first memory cells 101A of each memory string 101 are electrically connected to the same first bit line BL through the second transistor 103 corresponding to the memory string 101; the gates of the plurality of first transistors 102 and the gates of the plurality of second transistors 103 arranged along the second direction Y are electrically connected to the same second word line WL.

[0087] In the case where the first memory cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, in the plurality of memory strings 101 arranged along the first direction X, the fourth transistor 1011 of each memory string 101 is electrically connected to the same first line BL through a second transistor 103. In this case, one of the source and drain of the second transistor 103 is electrically connected to the source or drain of the fourth transistor 1011, and the other is electrically connected to the first line BL. Alternatively, in the plurality of memory strings 101 arranged along the first direction X, the first MTJ 1012 of each memory string 101 is electrically connected to the same first line BL through a second transistor 103. In this case, one of the source and drain of the second transistor 103 is electrically connected to the first MTJ 1012, and the other is electrically connected to the first line BL.

[0088] It should be noted that the aforementioned second word line WL, source line SL, first bit line BL, and multiple first transistors 102 can be as follows: Figure 5 The diagram shows the arrangement below multiple memory strings 101, specifically the second word line WL, source line SL, first bit line BL, and multiple first transistors 102 positioned close to the substrate relative to the memory strings 101. Alternatively, as shown... Figure 11 As shown, the second word line WL, the source line SL, the first bit line BL, and a plurality of first transistors 102 are positioned above the plurality of memory strings 101, that is, the memory strings 101 are closer to the substrate than the second word line WL, the source line SL, the first bit line BL, and the plurality of first transistors 102. Here, the positions of the first transistors 102, the second word line WL, the source line SL, and the first bit line BL can be flexibly set according to wiring requirements, etc.

[0089] In addition, when the first transistor 102 is a BEOL transistor, the peripheral control circuit, processor, such as CPU, can be placed below the memory string 101, that is, the peripheral control circuit, processor, such as CPU, is closer to the substrate relative to the memory string 101, thereby reducing the chip area.

[0090] Based on the structure of the magnetic random access memory 200 described above, this application embodiment also provides a method for writing and reading data from the magnetic random access memory 200. The methods for writing and reading data from the magnetic random access memory 200 are described below.

[0091] The data writing method for the magnetic random access memory 200 specifically includes the following steps: S10. The first word line wl, electrically connected to the first memory cell 101A to be written, receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor 1011 in the plurality of first memory cells 101A located on the same layer as the first memory cell 101A to be written to be in a conducting state. Other first word lines wl, besides the first word line wl electrically connected to the first memory cell 101A to be written, receive another gate bias voltage to control the first memory cells 101A in other layers to be in a de-energized state.

[0092] It is understandable that since multiple first memory cells 101A located on the same layer are electrically connected to the same first word line wl, when the first word line wl electrically connected to the first memory cell 101A to be written receives the first gate bias voltage, multiple first memory cells 101A located on the same layer as the first memory cell 101A to be written will be in the on state; when other first word lines wl, except for the first word line wl electrically connected to the first memory cell 101A to be written, receive another gate bias voltage, the first memory cells 101A in other layers will be in the off state.

[0093] When the first memory cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, the gate of the fourth transistor 1011 is electrically connected to the first word line wl, so the first memory cell 101A is turned on, that is, the fourth transistor 1011 in the first memory cell 101A is turned on; the first memory cell 101A is turned off, that is, the fourth transistor 1011 in the first memory cell 101A is turned off.

[0094] Example, Figure 5 The provided magnetic random access memory 200 includes a first storage layer and a second storage layer. The first storage layer is electrically connected to a first word line wl1, and the second storage layer is electrically connected to a first word line wl2. Taking the first storage cell 101A to be written as the first storage cell T in the first storage layer as an example, when the first word line wl1 receives a first gate bias voltage and the first word line wl2 receives another gate bias voltage, that is, the first storage layer is selected, the fourth transistor 1011 of the first storage cell 101A in the first storage layer is turned on, and the fourth transistor 1011 of the first storage cell 101A in the second storage layer is turned off.

[0095] S11. The second word line WL corresponding to the first memory cell 101A to be written receives a second gate bias voltage. The second gate bias voltage is used to control the conduction of a plurality of first transistors 102 located in the same column as the first transistor 102 electrically connected to the first memory cell 101A to be written along the second direction Y. Other second word lines WL receive another gate bias voltage to control the disengagement of a plurality of first transistors 102 in other columns except for the first transistors 102 located in the same column as the first transistor 102 electrically connected to the first memory cell 101A to be written along the second direction Y.

[0096] Since the gates of the plurality of first transistors 102 arranged along the second direction Y are electrically connected to the same second word line WL, when any second word line WL receives a second gate bias voltage, a column of first transistors 102 electrically connected to that second word line WL is turned on; when other second word lines WL receive another gate bias voltage, a column of first transistors 102 electrically connected to the other second word lines WL is turned off.

[0097] For example, such as Figure 5 As shown, the second word line WL2 receives a second gate bias voltage, and along the second direction Y, a plurality of first transistors 102 located in the same column as the first memory cell T are turned on. The second word line WL1 receives another bias voltage, and all the first transistors 102 in a column electrically connected to the second word line WL1 are turned off.

[0098] S12, receiving write voltage V from one of the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be written. write One of the source lines receives the ground voltage. The other source lines SL and the first source line BL also receive the ground voltage.

[0099] When one of the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be written, receives a write voltage V. write When a ground voltage is received, current flows through the first storage cell 101A to be written, thereby enabling the writing of data from the first MTJ1012 in the first storage cell 101A.

[0100] Among them, one of the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be written, receives the write voltage V. write Another receiver ground voltage includes: a source line SL electrically connected to the first memory cell 101A to be written to, which receives the write voltage V. write The first bit line BL, which is electrically connected to the first memory cell 101A to be written, receives the ground voltage; or, the source line SL, which is electrically connected to the first memory cell 101A to be written, receives the ground voltage, and the first bit line BL, which is electrically connected to the first memory cell 101A to be written, receives the write voltage V. write In these two cases, the direction of the current flowing through the first MTJ1012 in the first memory cell 101A to be written is different, so that opposite information can be written into the first MTJ1012 in the first memory cell 101A to be written. Specifically, the first logic information "0" or the second logic information "1" can be written.

[0101] For example, such as Figure 5 As shown, a receive write voltage V in source line SL1 and first bit line BL1 write Another line receives a ground voltage, allowing data to be written to the first storage cell T. Source line SL2 and first bit line BL2 each receive a ground voltage.

[0102] Based on the above, it can be seen that step S10 selects a certain layer of first storage cell 101A through the first word line wl; step S11 selects a column of first storage cells 101A in the XY plane through the second word line WL; step S12 can write data to a specific first storage cell 101A in the column of first storage cells 101A selected in step S11 through the source line SL and the first bit line BL.

[0103] The data reading method of the magnetic random access memory 200 specifically includes the following steps: S20. The first word line wl, which is electrically connected to the first memory cell 101A to be read, receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor 1011 in the plurality of first memory cells 101A located on the same layer as the first memory cell 101A to be read to be in a conducting state. Other first word lines wl, besides the first word line wl electrically connected to the first memory cell 101A to be read, receive another gate bias voltage to control the first memory cells 101A in other layers to be in a disconnected state.

[0104] S21. The second word line WL corresponding to the first memory cell 101A to be read receives a second gate bias voltage. The second gate bias voltage is used to control the conduction of a plurality of first transistors 102 located in the same column as the first transistor 102 electrically connected to the first memory cell 101A to be read along the second direction Y. Other second word lines WL receive another gate bias voltage to control the disengagement of a plurality of first transistors 102 in other columns except for the first transistors 102 located in the same column as the first transistor 102 electrically connected to the first memory cell 101A to be written along the second direction Y.

[0105] It should be noted that steps S20 and S21 can refer to steps S10 and S11 above, and will not be repeated here.

[0106] S22, A receive read voltage V from the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be read. read One receives the ground voltage. The other source line SL and the first source line BL receive the ground voltage.

[0107] When the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be read, receive a read voltage V read When one source line SL and the first bit line BL receive the ground voltage, only the first storage cell 101A to be read has current flowing through it. Therefore, the magnitude of the current can be used to determine the resistance of the first MTJ1012 in the first storage cell 101A to be read, and thus determine whether the first MTJ1012 stores the first logic information "0" or the second logic information "1".

[0108] Among them, one of the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be read, receives the read voltage V. read A receive ground voltage includes: a source line SL electrically connected to the first memory cell 101A to be read, and a receive read voltage V. readThe first line BL, electrically connected to the first memory cell 101A to be read, receives the ground voltage; or, the source line SL, electrically connected to the first memory cell 101A to be read, receives the ground voltage, and the first line BL, electrically connected to the first memory cell 101A to be read, receives the read voltage V. read .

[0109] In this first embodiment, since multiple first storage cells 101A located on the same layer are electrically connected to the same first word line wl, that is, multiple first storage cells 101A located on the same layer share a first word line wl, and the first word line wl can be used for addressing, a first word line wl can control multiple first storage cells 101A located on the same layer to be in a conducting state when the magnetic random access memory 200 is performing read and write operations. If each storage string 101 includes M first storage cells 101A stacked in sequence, that is, the magnetic random access memory 200 includes M storage layers, then M first word lines wl are needed to control the M storage layers respectively. It can be understood that these M first word lines wl can be led from the outside of the storage array 10 to the plane where the peripheral control circuit is located through metal wires, thereby realizing selective operation of the first storage cells 101A in different storage layers, such as controlling the conduction or disconnection of the first storage cells 101A in different storage layers.

[0110] Based on this, multiple storage strings 101 arranged along the first direction X share a source line SL and a first bit line BL, and multiple storage strings 101 arranged along the second direction Y share a second word line WL. When the magnetic random access memory 200 includes P columns of storage strings 101 arranged along the first direction X and Q columns of storage strings 101 arranged along the second direction Y, the magnetic random access memory 200 includes P second word lines WL, Q source lines SL, and Q first bit lines BL.

[0111] Compared to existing technologies, taking an N×N×M memory array as an example, each memory layer requires N BLs and N WLs. If the magnetic random access memory 200 includes M memory layers, it requires (M+1)×N BLs and WLs (i.e., (M+1)×N signal lines), or N×M WLs, and N×(M+1) BLs and GNDs (i.e., (2M+1)×N signal lines). In the embodiment of this application, multiple first memory cells 101A located on the same layer share a first word line wl, along the first... Multiple memory strings 101 arranged in one direction X share a source line SL and a first word line BL. Multiple memory strings 101 arranged in the second direction Y share a second word line WL. Therefore, if the magnetic random access memory 200 includes M memory layers, and the magnetic random access memory 200 has P columns of memory strings 101 arranged in the first direction X and Q columns of memory strings 101 arranged in the second direction Y, then M first word lines wl, P second word lines WL, Q source lines SL, and Q first word lines BL are required, that is, M+P+2Q signal lines are required. Based on this, it can be seen that the number of signal lines (including first word lines wl, source lines SL, first word lines BL, and second word lines WL) in the magnetic random access memory 200 provided in this application embodiment is significantly reduced. This significantly reduces the number of signal lines electrically connected to the peripheral control circuit, thereby reducing the wiring difficulty and saving the area occupied by wiring.

[0112] Example 2 The difference between Embodiment 2 and Embodiment 1 is as follows: In Embodiment 1, each storage string 101 in the magnetic random access memory 200 includes a plurality of first storage cells 101A stacked sequentially. In Embodiment 2, each storage string 101 in the magnetic random access memory 200, in addition to including a plurality of first storage cells 101A stacked sequentially, also includes a second storage cell corresponding to each first storage cell. Furthermore, to control the second storage cell, the magnetic random access memory 200 also includes a second transistor and / or a third transistor, as well as a second bit line, etc.

[0113] In other words, the magnetic random access memory 200 provided in Embodiment 2, based on the magnetic random access memory 200 provided in Embodiment 1, adds a second memory cell, a second bit line, and a second transistor and / or a third transistor, etc. The following describes the parts of the magnetic random access memory 200 provided in Embodiment 2 that differ from those in Embodiment 1; the parts that are the same can be referred to in Embodiment 1 above, and will not be repeated here.

[0114] like Figure 12As shown, each storage string 101 also includes a plurality of second storage units 101B corresponding one-to-one with each first storage unit 101A; the corresponding first storage units 101A and second storage units 101B are located on the same layer. The plurality of first storage units 101A and the plurality of second storage units 101B located on the same layer are electrically connected to the same first word line wl, and each first word line wl can control the on / off state of the plurality of first storage units 101A and the plurality of second storage units 101B located on the same layer.

[0115] Please continue to refer to this. Figure 12 In some examples, each second memory cell 101B includes a fifth transistor 1013 and a second MTJ 1014 connected in series with the fifth transistor 1013. Based on this, multiple first memory cells 101A and multiple second memory cells 101B located on the same layer are electrically connected to the same first word line wl, that is, the gate of the fourth transistor 1011 in the multiple first memory cells 101A and the gate of the fifth transistor 1013 in the multiple second memory cells 101B located on the same layer are electrically connected to the same first word line wl.

[0116] It should be noted that it can be as follows: Figure 12 As shown, the fourth transistor 1011 is disposed on the first MTJ 1012, and the fifth transistor 1013 is disposed on the second MTJ 1014, that is, the first MTJ 1012 and the second MTJ 1014 are closer to the substrate than the fourth transistor 1011 and the fifth transistor 1013. Alternatively, it can be as follows: Figure 13 As shown, the first MTJ1012 is disposed on the fourth transistor 1011, and the second MTJ1014 is disposed on the fifth transistor 1013, that is, the fourth transistor 1011 and the fifth transistor 1013 are closer to the substrate than the first MTJ1012 and the second MTJ1014. Alternatively, the fourth transistor 1011 can be disposed on the first MTJ1012, and the second MTJ1014 can be disposed on the fifth transistor 1013, that is, the first MTJ1012 and the fifth transistor 1013 are closer to the substrate than the fourth transistor 1011 and the second MTJ1014; or, the first MTJ1012 can be disposed on the fourth transistor 1011, and the fifth transistor 1013 can be disposed on the second MTJ1014, that is, the fourth transistor 1011 and the second MTJ1014 are closer to the substrate than the first MTJ1012 and the fifth transistor 1013.

[0117] Furthermore, the structure of the second MTJ1014, as well as the principles of data writing and data reading, can be referred to the first MTJ1012 mentioned above, and will not be repeated here.

[0118] The gate of the fifth transistor 1013 is electrically connected to the first word line wl, and the source or drain of the fifth transistor 1013 is electrically connected to the second MTJ 1014.

[0119] To enable read and write operations on the second storage unit 101B, the magnetic random access memory 200 provided in this embodiment can be implemented using the following two structures. The difference between these two structures is that, in the first structure, the multiple first storage units 101A and multiple second storage units 101B of the multiple storage strings 101 arranged along the first direction X share a single first bit line BL. In the second structure, the multiple first storage units 101A and multiple second storage units 101B of the multiple storage strings 101 arranged along the first direction X share a single source line SL. These two structures will be described in detail below.

[0120] The first type: such as Figure 12 and Figure 13 As shown, the magnetic random access memory 200 further includes multiple second bit lines BL', and multiple second memory cells 101B of the multiple memory strings 101 arranged along the first direction X are electrically connected to the same first bit line BL and the same second bit line BL', respectively. The second bit line BL' can extend along the first direction X. It is understood that the multiple first memory cells 101A and multiple second memory cells 101B of the multiple memory strings 101 arranged along the first direction X share the first bit line BL.

[0121] Based on this, the magnetic random access memory 200 also includes a plurality of second transistors and / or third transistors corresponding one-to-one with each memory string 101.

[0122] Here, the magnetic random access memory 200 may include a plurality of second transistors corresponding one-to-one with each storage string 101, but may not include a third transistor; or the magnetic random access memory 200 may include a plurality of third transistors corresponding one-to-one with each storage string 101, but may not include a second transistor; or the magnetic random access memory 200 may include a plurality of second transistors corresponding one-to-one with each storage string 101, and may also include a plurality of third transistors corresponding one-to-one with each storage string 101.

[0123] In the case where the magnetic random access memory 200 includes a second transistor, such as Figure 14 As shown, each first word line BL is electrically connected to a second transistor 103 and a plurality of first memory cells 101A and a plurality of second memory cells 101B in the memory string 101 corresponding to the second transistor 103; the gates of a plurality of first transistors 102 and a plurality of second transistors 103 arranged along the second direction Y are electrically connected to the same second word line WL.

[0124] In the case where the first memory cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, and the second memory cell 101B includes a fifth transistor 1013 and a second MTJ 1014 connected in series with the fifth transistor 1013, the connection relationship between the fourth transistor 1011, the first MTJ 1012, the fifth transistor 1013, the second MTJ 1014 and the source line SL, the first bit line BL, and the second bit line BL' can include the following four optional implementations: In the first optional implementation, such as Figure 14 As shown, in the plurality of memory strings 101 arranged along the first direction X, the plurality of first MTJs 1012 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to the memory string 101; in the plurality of memory strings 101 arranged along the first direction X, the source or drain of the plurality of fourth transistors 1011 and fifth transistors 1013 of each memory string 101 are electrically connected to the same first bit line BL through the second transistor 103 corresponding to the memory string 101; in the plurality of memory strings 101 arranged along the first direction X, the plurality of second MTJs 1014 of each memory string 101 are electrically connected to the same second bit line BL'.

[0125] In a second optional embodiment, among the plurality of memory strings 101 arranged along the first direction X, the plurality of first MTJs 1012 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to the memory string 101; among the plurality of memory strings 101 arranged along the first direction X, the plurality of fourth transistors 1011 and second MTJs 1014 of each memory string 101 are electrically connected to the same first bit line BL through the second transistor 103 corresponding to the memory string 101; among the plurality of memory strings 101 arranged along the first direction X, the plurality of fifth transistors 1013 of each memory string 101 are electrically connected to the same second bit line BL'.

[0126] In a third optional embodiment, among the plurality of memory strings 101 arranged along the first direction X, the plurality of fourth transistors 1011 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to the memory string 101; among the plurality of memory strings 101 arranged along the first direction X, the plurality of first MTJs 1012 and fifth transistors 1013 of each memory string 101 are electrically connected to the same first bit line BL through the second transistor 103 corresponding to the memory string 101; and among the plurality of memory strings 101 arranged along the first direction X, the plurality of second MTJs 1014 of each memory string 101 are electrically connected to the same second bit line BL'.

[0127] In a fourth alternative implementation, such as Figure 15As shown, in the plurality of memory strings 101 arranged along the first direction X, the plurality of fourth transistors 1011 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to the memory string 101; in the plurality of memory strings 101 arranged along the first direction X, the plurality of first MTJs 1012 and second MTJs 1014 of each memory string 101 are electrically connected to the same first bit line BL through the second transistor 103 corresponding to the memory string 101; in the plurality of memory strings 101 arranged along the first direction X, the plurality of fifth transistors 1013 of each memory string 101 are electrically connected to the same second bit line BL'.

[0128] In the case where the magnetic random access memory 200 includes a third transistor 104, such as Figure 12 and Figure 13 As shown, each second bit line BL' is electrically connected to a third transistor 104 and a plurality of second memory cells 101B in the memory string 101 corresponding to the third transistor 104; the gates of a plurality of first transistors 102 arranged along the second direction Y and the gates of a plurality of third transistors 104 are electrically connected to the same second word line WL.

[0129] In the case where the second memory cell 101B includes a fifth transistor 1013 and a second MTJ 1014 connected in series with the fifth transistor 1013, multiple second MTJs 1014 in a plurality of memory strings 101 arranged along the first direction X can be electrically connected to the same first bit line BL; in the plurality of memory strings 101 arranged along the first direction X, the source or drain of multiple fifth transistors 1013 in each memory string 101 can be electrically connected to the same second bit line BL' through a third transistor 104 corresponding to that memory string 101. Alternatively, multiple fifth transistors 1013 in a plurality of memory strings 101 arranged along the first direction X can be electrically connected to the same first bit line BL; in the plurality of memory strings 101 arranged along the first direction X, multiple second MTJs 1014 in each memory string 101 can be electrically connected to the second bit line BL' through a third transistor 104 corresponding to that memory string 101.

[0130] In the case where the first memory cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, the connection relationship between the fourth transistor 1011, the first MTJ 1012 and the source line SL and the first bit line BL can be referred to the above embodiment 1, and will not be repeated here.

[0131] It is understood that the second transistor 103, the third transistor 104 and the second bit line BL' mentioned above can be located above or below the storage string 101. For details, please refer to the above embodiment 1, which will not be repeated here.

[0132] Based on the structure of the magnetic random access memory 200 provided in Embodiment 2 above, Embodiment 2 of this application also provides a data writing and data reading method for the magnetic random access memory 200. The data writing and data reading methods for the magnetic random access memory 200 are described below.

[0133] The data writing method for the magnetic random access memory 200 specifically includes the following steps: S30. The first word line wl, electrically connected to the second memory cell 101B to be written, receives a first gate bias voltage. The first gate bias voltage is used to control multiple first memory cells 101A and multiple second memory cells 101B located on the same layer as the second memory cell 101B to be written to be in a conducting state. Other first word lines wl, except for the first word line wl electrically connected to the second memory cell 101B to be written, receive another gate bias voltage to control the first memory cells 101A and second memory cells 101B in other layers to be in a disconnected state.

[0134] When the first storage cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, and the second storage cell 101B includes a fifth transistor 1013 and a second MTJ 1014 connected in series with the fifth transistor 1013, the first storage cell 101A and the second storage cell 101B are in a conducting state, that is, the fourth transistor 1011 in the first storage cell 101A and the fifth transistor 1013 in the second storage cell 101B are in a conducting state.

[0135] It is understandable that step S30 can be used to select a certain layer of first storage cell 101A and second storage cell 101B.

[0136] S31. The second word line WL corresponding to the second memory cell 101B to be written receives a second gate bias voltage. The second gate bias voltage is used to control multiple first transistors 102, multiple second transistors 103 and multiple third transistors 104 located in the same column along the second direction Y to be turned on. Other second word lines WL receive another gate bias voltage to control multiple first transistors 102, multiple second transistors 103 and multiple third transistors 104 in other columns to be turned off.

[0137] It should be noted that when the magnetic random access memory 200 includes a second transistor 103 electrically connected to the second memory cell 101B to be written, but does not include a third transistor 104, the second word line WL receives a second gate bias voltage, controlling the conduction of a plurality of first transistors 102 and a plurality of second transistors 103 located in the same column as the second transistor 103 electrically connected to the second memory cell 101B to be written along the second direction Y. When the magnetic random access memory 200 includes a third transistor 104 electrically connected to the second memory cell 101B to be written, but does not include a second transistor 103, the second word line WL receives a second gate bias voltage, controlling the conduction of a plurality of first transistors 102 and a plurality of third transistors 104 located in the same column as the third transistor 104 electrically connected to the second memory cell 101B to be written along the second direction Y. When the magnetic random access memory 200 includes a second transistor 103 and a third transistor 104 electrically connected to the second memory cell 101B to be written, the second word line WL receives a second gate bias voltage and controls the multiple first transistors 102, multiple second transistors 103 and multiple third transistors 104 located in the same column along the second direction Y to be turned on.

[0138] It is understandable that step S31 can select a column of first storage cell 101A and second storage cell 101B in the XY plane through the second word line WL.

[0139] S32, receiving write voltage V from one of the first bit line BL and the second bit line BL', which are electrically connected to the second memory cell 101B to be written. write One source line SL, which receives ground voltage and is electrically connected to the first memory cell 101A corresponding to the second memory cell 101B to be written, is in a floating state, i.e., disconnected. The other source lines SL, the first bit line BL, and the second bit line BL' receive ground voltage.

[0140] When one of the first bit line BL and the second bit line BL', which is electrically connected to the second memory cell 101B to be written, receives a write voltage V. write When a receiving ground voltage is applied, current flows through the second storage cell 101B to be written, thereby enabling the writing of data to the second MTJ1014 in the second storage cell 101B.

[0141] It is understood that step S32 can write data to a specific second storage cell 101B in a column of first storage cells 101A and second storage cells 101B selected in step S31 by using the first bit line BL and the second bit line BL'.

[0142] Based on the structure of the magnetic random access memory 200 provided in Embodiment 2 above, when it is necessary to write data to the first memory cell 101A, the method for selecting the first memory cell 101A to be written to can refer to steps S30 and S31, which will not be repeated here. The difference is that in step S32, one of the source line SL and the first bit line BL, which are electrically connected to the first memory cell 101A to be written to, receives the write voltage V. write A second bit line BL', which receives ground voltage and is electrically connected to the second storage cell 101B corresponding to the first storage cell 101A to be written, is in a floating state, thereby realizing the writing of data to the first storage cell 101A.

[0143] The data reading method of the magnetic random access memory 200 specifically includes the following steps: S40. The first word line wl electrically connected to the second memory cell 101B to be read receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor 1011 in the plurality of first memory cells 101A and the fifth transistor 1013 in the plurality of second memory cells 101B located in the same layer as the second memory cell 101B to be read to be in a conducting state. Other first word lines wl besides the first word line wl electrically connected to the second memory cell 101B to be read receive another gate bias voltage, controlling the first memory cells 101A and second memory cells 101B in other layers to be in a disconnected state.

[0144] S41. The second word line WL corresponding to the second memory cell 101B to be read receives a second gate bias voltage. The second gate bias voltage is used to control multiple first transistors 102, multiple second transistors 103 and multiple third transistors 104 located in the same column along the second direction Y to be turned on. Other second word lines WL provide another gate bias voltage to control multiple first transistors 102, multiple second transistors 103 and multiple third transistors 104 in other columns to be turned off.

[0145] It should be noted that steps S40 and S41 can refer to steps S30 and S31 above, and will not be repeated here.

[0146] S42, receiving a read voltage V from one of the first bit line BL and the second bit line BL', which are electrically connected to the second memory cell 101B to be read. read One source line SL, which receives ground voltage and is electrically connected to the first memory cell 101A corresponding to the second memory cell 101B to be read, is in a floating state. The other source lines SL, the first bit line BL, and the second bit line BL' receive ground voltage.

[0147] When one of the first bit line BL and the second bit line BL', which is electrically connected to the second memory cell 101B to be read, receives a read voltage V. read One source line SL, which receives the ground voltage and is electrically connected to the first storage cell 101A corresponding to the second storage cell 101B to be read, is in a floating state. When the other source lines SL, the first bit line BL, and the second bit line BL' receive the ground voltage, only the second storage cell 101B to be read has current flowing through it. Therefore, the resistance of the second MTJ1014 in the second storage cell 101B can be determined based on the magnitude of the current. In turn, it can be determined whether the second MTJ1014 stores the first logic information "0" or the second logic information "1".

[0148] Based on the structure of the magnetic random access memory 200 provided in Embodiment 2 above, when it is necessary to read the data stored in the first storage cell 101A, the method for selecting the first storage cell 101A to be read can refer to steps S40 and S41, which will not be repeated here. The difference is that in step S42, one of the source line SL and the first bit line BL electrically connected to the first storage cell 101A to be read receives the read voltage V. read A second bit line BL' that receives ground voltage and is electrically connected to the second storage unit 101B corresponding to the first storage unit 101A to be read is in a floating state, thereby realizing the reading of data from the first storage unit 101A to be read.

[0149] The second type: such as Figure 16 As shown, the magnetic random access memory 200 further includes multiple second bit lines BL', and multiple second memory cells 101B of the multiple memory strings 101 arranged along the first direction are electrically connected to the same source line SL and the same second bit line BL', respectively. It can be understood that multiple first memory cells 101A and multiple second memory cells 101B of the multiple memory strings 101 arranged along the first direction X share a source line SL.

[0150] Based on this, the magnetic random access memory 200 also includes a plurality of second transistors and / or a plurality of third transistors corresponding one-to-one with each memory string 101.

[0151] Each source line SL is electrically connected to a first transistor 102 and a plurality of first memory cells 101A and a plurality of second memory cells 101B in the memory string 101 corresponding to the first transistor 102.

[0152] In the case where the magnetic random access memory 200 includes a second transistor 103, each first bit line BL is electrically connected to a plurality of first memory cells 101A in the memory string 101 corresponding to the second transistor 103 through the second transistor 103, and the gates of the plurality of first transistors 102 arranged along the second direction Y and the gates of the plurality of second transistors 103 are electrically connected to the same second word line WL.

[0153] When the first storage cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, the connection relationship between the fourth transistor 1011, the first MTJ 1012 and the first transistor 102 and the second transistor 103 in the first storage cell 101A can be referred to the above, and will not be repeated here.

[0154] In the case where the magnetic random access memory 200 includes a third transistor 104, each second bit line BL' is electrically connected to a plurality of second memory cells 101B in the memory string 101 corresponding to the third transistor 104; the gates of a plurality of first transistors 102 arranged along the second direction Y and the gates of a plurality of third transistors 104 are electrically connected to the same second word line WL.

[0155] In the case where the second memory cell 101B includes a fifth transistor 1013 and a second MTJ 1014 connected in series with the fifth transistor 1013, the second memory cell 101B is electrically connected to the source line SL and the second bit line BL', specifically as follows: Figure 17 As shown, in the plurality of memory strings 101 arranged along the first direction X, the source or drain of the plurality of fifth transistors 1013 in each memory string 101 is electrically connected to the same source line SL through a first transistor 102. In the plurality of memory strings 101 arranged along the first direction X, the plurality of second MTJs 1014 in each memory string 101 are electrically connected to the same second bit line BL' through a third transistor 104 corresponding to that memory string 101; or it can be as follows. Figure 16 As shown, in the plurality of memory strings 101 arranged along the first direction X, the source or drain of the plurality of fifth transistors 1013 of each memory string 101 is electrically connected to the same second bit line BL' through the third transistor 104 corresponding to the memory string 101. In the plurality of memory strings 101 arranged along the first direction X, the plurality of second MTJs 1014 of each memory string 101 are electrically connected to the same source line SL through the first transistor 102 corresponding to the memory string 101.

[0156] In the case where the first memory cell 101A includes a fourth transistor 1011 and a first MTJ 1012 connected in series with the fourth transistor 1011, the connection relationship between the fourth transistor 1011, the first MTJ 1012 and the source line SL and the first bit line BL in the first memory cell 101A can be referred to the above, and will not be repeated here.

[0157] Based on the structure of the magnetic random access memory 200 described above, Embodiment 2 of this application also provides a data writing and data reading method for the magnetic random access memory 200. The data writing method for the magnetic random access memory 200 can refer to steps S30 to S32 described above, except that step S32 is replaced by step S50.

[0158] S50, a write voltage V received from one of the source line SL and the second bit line BL', which are electrically connected to the second memory cell 101B to be written. write One bit line BL, which receives ground voltage and is electrically connected to the first memory cell 101A corresponding to the second memory cell 101B to be written, is in a floating state. The other source lines SL, the first bit line BL, and the second bit line BL' receive ground voltage.

[0159] The data reading method of the magnetic random access memory 200 can refer to the above steps S40 to S42, except that step S42 is replaced by step S60.

[0160] S60, a receive read voltage V from the source line SL and the second bit line BL', which are electrically connected to the second memory cell 101B to be read. read One bit line BL, which receives ground voltage and is electrically connected to the first memory cell 101A corresponding to the second memory cell 101B to be read, is in a floating state. The other source lines SL, the first bit line BL, and the second bit line BL' receive ground voltage.

[0161] In addition, the data writing and data reading methods of the first storage unit 101A can be referred to the above, and will not be repeated here.

[0162] In Embodiment 2, since the multiple first storage cells 101A and multiple second storage cells 101B of the multiple storage strings 101 arranged along the first direction X share a source line SL or a bit line BL, the number of source lines or bit lines, i.e. the number of signal lines, is further reduced in Embodiment 2 compared to Embodiment 1 when the number of storage cells is the same. This further reduces the number of signal lines electrically connected to the peripheral control circuit, thereby further reducing the wiring difficulty and saving the area occupied by wiring.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A magnetic random access memory, characterized in that, include: Multiple storage strings are arrayed along a first direction and a second direction, each storage string comprising multiple first storage cells stacked sequentially; The magnetic random access memory further includes: multiple first word lines, multiple second word lines, multiple source lines, multiple first bit lines, and multiple first transistors corresponding one-to-one with each of the memory strings; Multiple first storage cells located on the same layer are electrically connected to the same first word line; In the plurality of memory strings arranged along a first direction, the plurality of first memory cells in each memory string are electrically connected to the same source line through the first transistor, and the first memory cells in the plurality of memory strings arranged along the first direction are also electrically connected to the same first bit line; the gates of the plurality of first transistors arranged along a second direction are electrically connected to the same second word line. The first direction and the second direction are not parallel.

2. The magnetic random access memory according to claim 1, characterized in that, Each storage string also includes a plurality of second storage units that correspond one-to-one with each of the first storage units; the corresponding first storage units and second storage units are located on the same layer; Multiple first storage cells and multiple second storage cells located on the same layer are electrically connected to the same first word line; the magnetic random access memory also includes multiple second bit lines, and the second storage cells of multiple storage strings arranged along the first direction are respectively electrically connected to the same first bit line and the same second bit line; The magnetic random access memory further includes a plurality of second transistors corresponding one-to-one with each of the memory strings. Each first bit line is electrically connected to a plurality of first memory cells and a plurality of second memory cells through the second transistors. The gates of the plurality of first transistors arranged along the second direction and the gates of the plurality of second transistors are electrically connected to the same second word line. And / or, the magnetic random access memory further includes a plurality of third transistors corresponding one-to-one with each of the memory strings, each of the second bit lines being electrically connected to a plurality of the second memory cells through the third transistors; the gates of the plurality of first transistors arranged along the second direction and the gates of the plurality of third transistors are electrically connected to the same second word line.

3. The magnetic random access memory according to claim 1, characterized in that, Each storage string also includes a plurality of second storage units that correspond one-to-one with each of the first storage units; the corresponding first storage units and second storage units are located on the same layer; Multiple first storage cells and multiple second storage cells located on the same layer are electrically connected to the same first word line; the magnetic random access memory also includes multiple second bit lines, and the second storage cells of multiple storage strings arranged along the first direction are respectively electrically connected to the same source line and the same second bit line; Each of the source lines is electrically connected to a plurality of the first memory cells and a plurality of the second memory cells respectively through the first transistor; The magnetic random access memory further includes a plurality of second transistors corresponding one-to-one with each of the memory strings. Each first bit line is electrically connected to a plurality of first memory cells through the second transistors. The gates of the plurality of first transistors arranged along the second direction and the gates of the plurality of second transistors are electrically connected to the same second word line. And / or, the magnetic random access memory further includes a plurality of third transistors corresponding one-to-one with each of the memory strings, each of the second bit lines being electrically connected to a plurality of the second memory cells through the third transistors; the gates of the plurality of first transistors arranged along the second direction and the gates of the plurality of third transistors are electrically connected to the same second word line.

4. The magnetic random access memory according to any one of claims 1-3, characterized in that, Each of the first memory cells includes a fourth transistor and a first magnetic tunnel junction (MTJ) connected in series with the fourth transistor; The gate of the fourth transistor is electrically connected to the first word line; The fourth transistor is also electrically connected to the source line through the first transistor, and the first MTJ is electrically connected to the first bit line; or, the fourth transistor is also electrically connected to the first bit line, and the first MTJ is electrically connected to the source line through the first transistor.

5. The magnetic random access memory according to claim 2, characterized in that, Each of the second memory cells includes a fifth transistor and a second MTJ connected in series with the fifth transistor; The gate of the fifth transistor is electrically connected to the first word line; The fifth transistor is electrically connected to the first bit line, and the second MTJ is electrically connected to the second bit line; or, the fifth transistor and the second bit line are electrically connected, and the second MTJ is electrically connected to the first bit line.

6. The magnetic random access memory according to claim 3, characterized in that, Each of the second memory cells includes a fifth transistor and a second MTJ connected in series with the fifth transistor; The gate of the fifth transistor is electrically connected to the first word line; The fifth transistor is electrically connected to the source line, and the second MTJ is electrically connected to the second bit line; or, the fifth transistor and the second bit line are electrically connected, and the second MTJ is electrically connected to the source line.

7. The magnetic random access memory according to claim 1, characterized in that, The first transistor is a thin-film transistor, a polycrystalline silicon transistor, an amorphous silicon transistor, or a carbon nanotube transistor.

8. The magnetic random access memory according to claim 1, characterized in that, The first transistor is a vertical transistor, and the source and drain of the first transistor are arranged along the direction in which the plurality of first memory cells are stacked in the memory string.

9. The magnetic random access memory according to claim 1, characterized in that, The first transistor is a planar transistor, and the source and drain of the first transistor are arranged in a direction perpendicular to the stacking of the plurality of first memory cells in the memory string.

10. The magnetic random access memory according to claim 1, characterized in that, The magnetic random access memory also includes a substrate; The first transistor, the second word line, the source line, and the first bit line are close to the substrate relative to the memory string; Alternatively, the memory string is located close to the substrate relative to the first transistor, the second word line, the source line, and the first bit line.

11. An electronic device, characterized in that, Includes printed circuit boards and magnetic random access memory as described in any one of claims 1-10; The printed circuit board and the magnetic random access memory are electrically connected.

12. A data writing method for a magnetic random access memory as described in any one of claims 1-10, characterized in that, Each first memory cell includes a fourth transistor and a first MTJ connected in series with the fourth transistor; the data writing method includes: A first word line electrically connected to the first memory cell to be written receives a first gate bias voltage, which is used to control the fourth transistor in a plurality of first memory cells located on the same layer as the first memory cell to be written to be in an on state. The second word line corresponding to the first memory cell to be written receives a second gate bias voltage. The second gate bias voltage is used to control the conduction of a plurality of first transistors located in the same column as the first transistors electrically connected to the first memory cell to be written along the second direction. One of the source line and the first bit line, which are electrically connected to the first memory cell to be written, receives the write voltage, and the other receives the ground voltage.

13. The data writing method according to claim 12, characterized in that, Each memory string further includes a plurality of second memory cells, each second memory cell being electrically connected to a first bit line and a second bit line; each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; The data writing method further includes: The first word line, which is electrically connected to the second memory cell to be written, receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in a plurality of first memory cells and the fifth transistor in a plurality of second memory cells located in the same layer as the second memory cell to be written to be in the on state. The second word line corresponding to the second memory cell to be written receives a second gate bias voltage. The second gate bias voltage is used to control a plurality of first transistors, a plurality of second transistors and a plurality of third transistors that are located in the same column along the second direction and are electrically connected to the second memory cell to be written. One of the first bit line and the second bit line electrically connected to the second memory cell to be written to receives a write voltage, and the other receives a voltage. The source line electrically connected to the first memory cell corresponding to the second memory cell to be written to is in a floating state.

14. The data writing method according to claim 12, characterized in that, Each memory string further includes a plurality of second memory cells, each second memory cell being electrically connected to a source line and a second bit line; each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; The data writing method further includes: The first word line, which is electrically connected to the second memory cell to be written, receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in a plurality of first memory cells and the fifth transistor in a plurality of second memory cells located in the same layer as the second memory cell to be written to be in the on state. The second word line corresponding to the second memory cell to be written receives a second gate bias voltage. The second gate bias voltage is used to control a plurality of first transistors, a plurality of second transistors and a plurality of third transistors that are located in the same column along the second direction and are electrically connected to the second memory cell to be written. One of the source line and the second bit line electrically connected to the second memory cell to be written to receives the write voltage, and the other receives the ground voltage. The first bit line electrically connected to the first memory cell corresponding to the second memory cell to be written to is in a floating state.

15. A data reading method for a magnetic random access memory as described in any one of claims 1-10, characterized in that, Each first memory cell includes a fourth transistor and a first MTJ connected in series with the fourth transistor; the data reading method includes: A first word line electrically connected to the first memory cell to be read receives a first gate bias voltage, which is used to control the fourth transistor in a plurality of first memory cells located on the same layer as the first memory cell to be read to be in an on state. The second word line corresponding to the first memory cell to be read receives a second gate bias voltage. The second gate bias voltage is used to control the conduction of a plurality of first transistors located in the same column as the first transistors electrically connected to the first memory cell to be read along the second direction. One of the source line and the first bit line, which are electrically connected to the first memory cell to be read, receives the read voltage, and the other receives the ground voltage.

16. The data reading method according to claim 15, characterized in that, Each memory string further includes a plurality of second memory cells, each second memory cell being electrically connected to a first bit line and a second bit line; each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; The data reading method further includes: The first word line, which is electrically connected to the second memory cell to be read, receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in a plurality of first memory cells and the fifth transistor in a plurality of second memory cells located in the same layer as the second memory cell to be read to be in the on state. The second word line corresponding to the second memory cell to be read receives a second gate bias voltage. The second gate bias voltage is used to control a plurality of first transistors, a plurality of second transistors and a plurality of third transistors that are located in the same column along the second direction and are electrically connected to the second memory cell to be read to be turned on. One of the first bit line and the second bit line electrically connected to the second memory cell to be read receives a read voltage, and the other receives a ground voltage. The source line electrically connected to the first memory cell corresponding to the second memory cell to be read is in a floating state.

17. The data reading method according to claim 15, characterized in that, Each memory string further includes a plurality of second memory cells, each second memory cell being electrically connected to a source line and a second bit line; each second memory cell includes a fifth transistor and a second MTJ connected in series with the fifth transistor; The data reading method further includes: The first word line, which is electrically connected to the second memory cell to be read, receives a first gate bias voltage. The first gate bias voltage is used to control the fourth transistor in a plurality of first memory cells and the fifth transistor in a plurality of second memory cells located in the same layer as the second memory cell to be read to be in the on state. The second word line corresponding to the second memory cell to be read receives a second gate bias voltage. The second gate bias voltage is used to control a plurality of first transistors, a plurality of second transistors and a plurality of third transistors that are located in the same column along the second direction and are electrically connected to the second memory cell to be read to be turned on. One of the source line and the second bit line electrically connected to the second memory cell to be read receives the read voltage, and the other receives the ground voltage. The first bit line electrically connected to the first memory cell corresponding to the second memory cell to be read is in a floating state.

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