High-precision time synchronization method for the master clock of communication networks used in user plane functions

By receiving PTP or gPTP messages and adjusting the time and frequency using the data plane clock servo module, the synchronization problem between the NW-TT module and GM in the UPF is solved, achieving high-precision time synchronization of TSN terminal stations in 5G communication networks and supporting seamless integration.

CN117044322BActive Publication Date: 2026-07-31HONG KONG APPLIED SCI & TECH RES INST
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HONG KONG APPLIED SCI & TECH RES INST
Filing Date
2023-02-22
Publication Date
2026-07-31

AI Technical Summary

Technical Problem

In the seamless integration of 5G and TSN systems, how can we achieve high-precision time synchronization between the NW-TT module in the UPF and the GM in the time domain to ensure the time synchronization accuracy of TSN terminal stations in the 5G communication network?

Method used

By receiving PTP or gPTP messages, the time offset between the UPF N3 interface and the NW-TT module and the GM is determined. The data plane clock servo module is used to adjust the time and frequency, including the data plane clock filter, PI controller and frequency adjuster, to achieve synchronization between the UPF N3 interface and the NW-TT module and the GM.

Benefits of technology

It achieves high-precision time and frequency synchronization between the UPF N3 interface and the NW-TT module and the 5G GM, ensuring the time synchronization accuracy of TSN terminal stations in the 5G communication network and supporting the seamless integration of the 5G system and the TSN system.

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Abstract

This invention describes a method for synchronizing a TSN NW-TT module within a UPF with the master clock (GM) in the time domain of a communication network. The method includes: receiving one or more PTP or gPTP messages on the N3 interface of the UPF. The method further includes: determining a first time offset value between the GM and the UPF N3 interface based on information received in the PTP or gPTP messages; adjusting the clock of the UPF N3 interface using the determined first time offset value to synchronize the time between the UPF N3 interface and the GM. The method also includes: determining a second time offset value between the UPF N3 interface and the NW-TT module; and adjusting the clock of the NW-TT module using the determined second time offset value to synchronize the time between the NW-TT module and the GM.
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Description

Technical Field

[0001] This invention relates to a method for high-precision time synchronization of the communication network grandmaster (GM) in New Radio (NR) communication networks, particularly for 5G User Plane Functions (UPF). This invention is especially useful for TSN technology in wireless communication systems. Background Technology

[0002] Fifth-generation (5G) wireless communication and Time-Sensitive Networking (TSN) are key technologies for industrial communication; 5G is used for wireless connectivity, while TSN is used for wired connections. In addition to enhanced mobile bandwidth, 5G also supports unprecedented reliability and extremely low latency communication, as well as massive Internet of Things (IoT) connectivity.

[0003] TSN comprises a series of Ethernet standards developed by the Institute of Electrical and Electronics Engineers (IEEE) 802.1 group, defining mechanisms for deterministic communication over wired Ethernet links, ensuring packet delivery with limited latency, low packet latency variation, and extremely low packet loss. Both technologies aim to provide converged communication for a wide range of services over public network infrastructure. Significant benefits can be gained by enabling TSN and 5G to work together.

[0004] To achieve seamless integration between the 5G system (5GS) and the TSN system, the 3rd Generation Partnership Project (3GPP) proposes that these two systems interoperate in a transparent manner to minimize the impact on other TSN entities. Therefore, the 5G system acts as one or more virtual TSN bridges within the TSN network. This virtual bridge model defines multiple gateways between the TSN and 5G systems, including a network-side TSN translator (NW-TT) on the User Plane Function (UPF) side.

[0005] Precision Time Protocol (PTP) or Generalized PTP (gPTP) is a computer network protocol used to synchronize the clocks of network components. It is a crucial component of 5G mobile networks, requiring an accurate time source. PTP or gPTP is a protocol for synchronizing the clocks of the entire communication network, achieving sub-microsecond clock accuracy, making it a perfect choice for applications requiring stringent time synchronization.

[0006] A PTP or gPTP system consists of a clock source, namely the Grandmaster (GM), which transmits synchronization information to multiple clock targets (slave devices).

[0007] IEEE 802.1AS contains the IEEE standard for time synchronization of time-sensitive applications using gPTP in local area networks (LANs) and metropolitan area networks (MANs). GM / Slave refers to the clock source generated by the gPTP GM in the network. The slave clock uses an offset to adjust its time to match the master clock. In addition to offset adjustment, the slave clock's frequency should also be synchronized with the gPTP GM. Without frequency synchronization, the slave clock's time may still be faster or slower than the GM.

[0008] 5G networks support time synchronization between 5G-based logical TSN bridges as defined by IEEE 802.1AS, using Ethernet PDU (Packet Data Unit) session types in the TSN time domain. 5G-based logical TSN bridges need to calculate the dwell time of the 5G network. The 5G network provides an internal system clock for internal 5G synchronization, where the base station (gNB), the NW-TT on the UPF side, and the device-side TST converter (DS-TT) on the user equipment (UE) side should all be synchronized with the 5G GM in the 5G time domain to calculate the dwell time.

[0009] TSN on 5G systems brings many benefits to communication networks, but these benefits are not without challenges.

[0010] There is a need for a method to help the NW-TT module in the UPF synchronize with the GM in the time domain. This is a key step to further support high-precision time synchronization of TSN terminal stations in the communication network.

[0011] Purpose of the invention

[0012] One object of the present invention is to mitigate or avoid to some extent one or more problems associated with known methods that support high-precision time synchronization of TSN terminal stations on communication networks.

[0013] The above objective is achieved by a combination of features of the main claim; the dependent claims disclose further advantageous embodiments of the invention.

[0014] Another object of the present invention is to provide a method and system to assist the NW-TT module in the UPF in time synchronization with the GM in the time domain.

[0015] Other objects of the invention will become apparent to those skilled in the art from the following description. Therefore, the foregoing statement of objects is not exhaustive and is merely intended to illustrate some of the many objects of the invention. Summary of the Invention

[0016] In a first key aspect, the present invention provides a method for synchronizing a network-side Time-Sensitive Network (TSN) converter (NW-TT) module within a user plane function (UPF) of a communication network with a master clock (GM) in the time domain of the communication network. The method includes: receiving one or more Precision Time Protocol (PTP) or Universal Precision Time Protocol (gPTP) messages on the N3 interface of the UPF. The method further includes: determining a first time offset between the GM and the UPF N3 interface based on information received in the one or more PTP or gPTP messages. N3 Using the determined first time offset value (Offset) N3 This method involves adjusting the clock of the UPF N3 interface to synchronize the time between the UPF N3 interface and the GM. The method includes determining a second time offset value between the UPF N3 interface and the NW-TT module. NW-TT Using a determined second time offset value (Offset) NW-TT This is used to adjust the clock of the NW-TT module to synchronize the time between the NW-TT module and the GM.

[0017] Preferably, the method includes: using a determined first time offset value (Offset) N3 The UPF N3 interface clock frequency adjustment value is determined using the second time offset value. NW-TT This determines the NW-TT module clock frequency adjustment value, which is then used to adjust the clock frequency of the NW-TT module.

[0018] In a second principal aspect, the present invention provides a UPF module for synchronizing a network-side time-sensitive network (TSN) converter (NW-TT) module within a user plane function (UPF) of a communication network with a master clock (GM) in the time domain of the communication network. The module includes a memory storing machine-readable instructions and a processor for executing the machine-readable instructions, such that when the processor executes the machine-readable instructions, it configures the UPF module to perform the steps of the first principal aspect of the present invention.

[0019] In a third key aspect, the present invention provides a data plane clock servo module in a UPF module for synchronizing a network-side Time-Sensitive Network (TSN) converter (NW-TT) module within the User Plane Function (UPF) of a communication network with the master clock (GM) in the time domain of the communication network. This data plane clock servo module includes: a first module for receiving a first time offset value between the GM and the UPF N3 interface. N3 Or the second time offset value between the UPF N3 interface and NW-TT (Offset) NW-TT First time offset value (Offset) N3 The second time offset value is determined by one or more Precision Time Protocol (PTP) or Universal Precision Time Protocol (gPTP) messages received from the N3 interface. NW-TT The first time offset is determined by the hardware clock of the NW-TT module and the synchronization clock of the UPF N3 interface; the second module is used to determine the received first time offset value. N3 or the second time offset value (Offset) NW-TT Whether it is greater than a predetermined, calculated, or selected time period; data plane clock filter, which includes a moving average filter, upon receiving the first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT When receiving the first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT The clock offset is smoothed to attenuate impulse noise, generating a smooth clock offset output for the 5G data plane clock offset controller; the data plane proportional-integral (PI) controller receives the first time offset value. N3 or the second time offset value (Offset) NW-TT The system provides a smooth clock offset output to generate a clock frequency adjustment value u(t), which coordinates the UPF N3 interface time with the GM time, or coordinates the NW-TT module time with the UPF N3 interface time; the data plane clock frequency adjuster receives the clock frequency adjustment value u(t) from the UPF N3 interface or the NW-TT module to adjust their respective clock frequencies accordingly; wherein, the data plane clock offset controller receives the smooth clock offset output and adjusts the clock of the UPF N3 interface or the clock of the NW-TT module.

[0020] In a fourth principal aspect, the present invention provides a non-transitory computer-readable medium storing machine-readable instructions, wherein, when executed by a processor, the machine-readable instructions configure the processor to implement the method of the first principal aspect of the present invention.

[0021] This invention does not necessarily disclose all the features necessary to define the invention; the invention may exist in sub-combinations of the disclosed features.

[0022] The features of the invention have been broadly outlined above to provide a better understanding of the detailed description that follows. Other features and advantages of the invention, which form the subject of the claims, will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifications or the design of other structures to achieve the same objectives of the invention. Attached Figure Description

[0023] The above and further features of the present invention will become apparent from the following description of preferred embodiments, which are provided by way of example only in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 It is a timing diagram for time synchronization of time-sensitive applications in LANs and MANs based on IEEE 802.1AS;

[0025] Figure 2 This is a schematic block diagram of the TSN time domain and 5G time domain in a TSN network that conforms to IEEE 802.1AS;

[0026] Figure 3 This is a more detailed schematic diagram of the UPF in a TSN network that conforms to IEEE 802.1AS;

[0027] Figure 4 This is a functional block diagram of the 5G data plane clock servo module of the present invention;

[0028] Figure 5 This is a schematic block diagram of an improved wireless device, apparatus, or network node of the present invention, including a 5G data plane clock servo module.

[0029] Figure 6 This is a schematic block diagram illustrating the TSN time domain and 5G time domain of the TSN network in the method steps of the present invention;

[0030] Figure 7 It is a timing diagram showing the transmission of time synchronization information of three adjacent time-aware systems in a TSN network implementing the method of the present invention;

[0031] Figure 8 This is a functional block diagram of a 5G data plane clock servo module that implements the method steps of the present invention;

[0032] Figure 9 This is a functional block diagram of the 5G data plane clock filter of the 5G data plane clock servo module of the present invention;

[0033] Figure 10 This is a functional block diagram of the 5G data plane PI controller of the 5G data plane clock servo module of the present invention. Detailed Implementation

[0034] The following description is merely an example of preferred embodiments and does not limit the combination of necessary features for carrying out the invention.

[0035] The phrase "one embodiment" or "an embodiment" as used in this specification means that a particular feature, structure, or characteristic related to that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment, nor is it a single or alternative embodiment that is mutually exclusive with other embodiments. Furthermore, the various features described may be shown in some embodiments but not in others. Similarly, various requirements are described that may be requirements of some embodiments but not in others.

[0036] It should be understood that the components shown in the figure can be implemented in various forms of hardware, software, or a combination thereof. These components can be implemented in a combination of hardware and software on one or more appropriately programmed general-purpose devices, which may include processors, memory, and input / output interfaces.

[0037] This specification illustrates the principles of the invention. Therefore, it should be understood that those skilled in the art will be able to devise various arrangements, although not expressly described or shown herein, that embody the principles of the invention and are included within its spirit and scope.

[0038] Furthermore, this document describes the principles, aspects, and embodiments of the invention, along with specific examples thereof, and is intended to cover its structural and functional equivalents. Moreover, such equivalents include both currently known equivalents and those developed in the future, i.e., any developed element that performs the same function, regardless of its structure.

[0039] Therefore, for example, those skilled in the art will understand that the block diagrams presented herein represent conceptual diagrams of systems and devices embodying the principles of the present invention.

[0040] The functionality of the various components shown in the diagram can be provided using dedicated hardware and hardware capable of executing software together with appropriate software. When provided by a processor, these functions can be provided by a single dedicated processor, a single shared processor, or multiple separate processors, some of which may be shared. Furthermore, the explicit use of the terms "processor" or "controller" should not be construed as referring only to hardware capable of executing software, and may implicitly include, but is not limited to, digital signal processor ("DSP") hardware, read-only memory ("ROM"), random access memory ("RAM"), and non-volatile memory for storing software.

[0041] In the claims, any element referred to as a means for performing a particular function is intended to cover any manner in which that function is performed, including, for example, a) a combination of circuit elements performing that function or b) any form of software, thus including firmware, microcode, etc., combined with appropriate circuitry to perform the function. The invention as defined by these claims lies in the fact that the functions provided by the various mentioned means are combined and brought together in the manner claimed in the claims. Therefore, any means providing these functions is considered equivalent to the means shown herein.

[0042] The following description of 5G wireless devices does not preclude the application of the methods described herein to wireless devices compatible with mobile communication systems.

[0043] The following description illustrates the implementation of the invention in a 5G communication network by way of example, but is not limited to implementation in suitable communication networks.

[0044] Figure 1 Taking known clock offset adjustment methods as an example, a timing diagram is provided for time synchronization of time-sensitive applications in LANs and MANs according to IEEE 802.1AS.

[0045] IEEE 802.1AS, "IEEE Standard for Local Area Networks and Metropolitan Area Networks - Timing and Synchronization for Time-Sensitive Applications," provides protocols, procedures, and management objects for transmitting timing over local area networks and metropolitan area networks.

[0046] refer to Figure 1 The clock source in the network is generated by gPTP GM (“TSN GM”) 10. The slave clock (“TSN Slave”) 12 uses an offset to adjust its time to be consistent with the master clock gPTP GM 10.

[0047] The steps for determining or calculating the offset include first calculating the clock delay value associated with the "Pdelay_Req" and "Pdelay_Response(T2)" messages. This clock delay value is given by the following formula:

[0048] Delay=[(T2–T1)+(T4–T3)] / 2.

[0049] In the next step, the clock offset value used to adjust the clock of clock 12 to keep in sync with the master clock of gPTP GM 10 utilizes the clock of the "synchronization" message and is given by the following formula:

[0050] Offset = T6 – T5 – Delay.

[0051] In addition to offset clock adjustment, the clock frequency of slave clock 12 should also be synchronized with gPTP GM 10, because without clock frequency synchronization, even if a defined clock offset value is used to adjust the clock of slave clock 12 to match the master clock of gPTP GM 10, slave clock 12 may still run faster or slower than the master clock of gPTP GM 10.

[0052] Figure 1 The "Follow_Up" message in the timing diagram includes a correction field containing the message's transmission and dwell times, and a "RateRatio" field containing the clock rate ratio between the time-aware system and the gPTP GM 10. The correction field C carries the elapsed time in the time-aware system and the elapsed time of the link before the last hop on the path between the gPTP GM 10 and the time-aware system. The rate ratio allows for logical synchronization between the time-aware system and the gPTP GM 10 frequency rate.

[0053] IEEE 802.1AS-2011 defines the gPTP profile, which, like all IEEE 1588 profiles, selects options from IEEE 1588, but also outlines the network architecture to make PTP applicable beyond wired Ethernet networks.

[0054] IEEE 1588, "IEEE Standard for Precision Clock Synchronization Protocol for Networked Measurement and Control Systems," defines a protocol that enables precise clock synchronization in measurement and control systems implemented using technologies such as network communication, local computing, and distributed objects. This protocol is applicable to systems communicating over local area networks that support multicast messaging, including but not limited to Ethernet.

[0055] Therefore, it will be understood that the following description does not preclude the implementation of the method of the present invention in the form of PTP packets in IEEE 1588 compatible networks, or in the form of gPTP packets in IEEE 802.1AS compatible networks. The method of the present invention can use gPTP to achieve point-to-point time synchronization or PTP to achieve end-to-end time synchronization.

[0056] Figure 2 A schematic block diagram of TSN time domain 14 and 5G time domain 16 in a known IEEE 802.1AS compliant TSN network is provided.

[0057] The TSN time domain 14 of 5G networks supports time synchronization between 5G-based logical TSN bridges (as defined by IEEE 802.1AS) and has Ethernet Packet Data Unit (PDU) session types in the TSN time domain 14. 5G-based logical TSN bridges need to calculate the dwell time of the 5G network.

[0058] The 5G time domain 16 of the 5G network provides an internal system clock for 5G internal synchronization. The NW-TT on the gNB and UPF 20 sides and the DS-TT on the UE side should be synchronized with 5G GM 18 in the 5G time domain in order to calculate the dwell time.

[0059] The focus of this invention is time synchronization in 5G time domain 16, which will be described in more detail below.

[0060] Figure 3 A schematic diagram is provided for a more detailed explanation. Figure 2 UPF 20 in TSN networks compliant with IEEE 802.1AS.

[0061] Reference Figure 3 According to the 3GPP specification, the N3 interface 24 of gNB 22 and UPF 20 synchronizes time via the gPTP protocol. However, the method by which the NW-TT module 26 at the N6 interface 28 on the UPF 20 synchronizes its time with the UPF N3 interface 24 is outside the scope of the 3GPP specification. In the 3GPP specification, the NW-TT module 26 is based on the N6 interface 28 of the UPF 20. In most cases, the N3 interface 24 on the same UPF 20 and the NW-TT module 26 based on the N6 interface use different network interfaces. However, different network interfaces typically use different oscillator sources, and therefore usually have different hardware clock sources, and their respective clocks may differ. If the NW-TT module 26 in the UPF 20 is not synchronized with the 5G GM 18 time in the 5G time domain 16, any 5G-based logical TSN bridge 30 ( Figure 2 The dwell time calculation will be incorrect, which will lead to incorrect time synchronization of TSN terminal station 32 on the 5G communication network.

[0062] This invention solves the problem of how to enable the NW-TT module 26 in the UPF 20 to accurately track the 5G GM 18, at least in terms of time synchronization, and preferably also in terms of frequency synchronization. To this end, as... Figure 4 As shown, the present invention provides Figure 6 The 5G data plane clock servo module 40 in the UPF 20.

[0063] Figure 4 This is a functional block diagram of the 5G data plane clock servo module 42 of the present invention. The 5G data plane application layer 50 is also shown, which includes a gPTP module 52, a packet forwarding control protocol module 54, and a bridge module 56. The 5G data plane interface layer 60 includes a UPF N3 interface 24 and an NW-TT module 26 based on the N6 interface 28.

[0064] The 5G data plane clock servo module 42 is located in the 5G data plane time synchronization layer 40, and includes a 5G data plane clock filter 44, a 5G data plane proportional-integral (PI) controller 45, a 5G data plane clock frequency adjuster 46, and a 5G data plane clock offset controller 47.

[0065] The 5G data plane clock filter 44 preferably includes a moving average filter that, upon receiving a first time offset value or a second time offset value, smooths the received first time offset value or second time offset value as described more fully below, to attenuate impulse noise and generate a smooth clock offset output for the 5G data plane clock offset controller 47.

[0066] The 5G data plane proportional-integral (PI) controller 45 is used to receive a smoothed clock offset output of a first time offset value or a second time offset value to generate a clock frequency adjustment u(t) value that coordinates the time of the UPF N3 interface 24 with the time of the 5G GM18, or coordinates the time of the NW-TT module 26 with the time of the UPF N3 interface 24.

[0067] The 5G data plane clock frequency regulator 46 receives the clock frequency adjustment u(t) value from the UPF N3 interface 24 or the NW-TT module 26 to adjust their respective clock frequencies accordingly.

[0068] The 5G data plane clock offset controller 47 receives a smooth clock offset output and adjusts the clock of the UPF N3 interface 24 or the clock of the NW-TT module 26.

[0069] Figure 5 This is a schematic block diagram of an improved wireless device, apparatus, or network node of the present invention, including a 5G data plane clock servo module 42. The improved wireless device apparatus 70 is connected to a gNB 22 operating in a 5G NR communication system environment. However, the improved wireless device apparatus 70 of the present invention is not limited to operation in an NR 5G communication system, but may include a wireless device for any suitable communication network.

[0070] The wireless equipment device 70 may include multiple functional blocks for performing its various functions. For example, the wireless equipment device 70 includes a receiver module 72 that provides received signal processing and is configured to provide received signals and / or information extracted therefrom to a functional block module 74, which may include various data sinks, control elements, user interfaces, etc. Although the receiver module 72 is described as providing received signal processing, it should be understood that this functional block can be implemented as a transceiver, providing both transmitted and received signal processing. Regardless of the specific configuration of the receiver module 72, embodiments include a signal detection module 76 arranged in association with the receiver module 72 for facilitating accurate processing and / or decoding of received information and channel signals according to the present invention.

[0071] Although the signal detection module 76 is shown as being deployed as part of the receiver module 72 (e.g., as part of the radio device module control and logic circuitry), there are no limitations on such deployment configuration according to the concept of the invention. For example, the signal detection module 76 may be deployed as a functional block of the radio device apparatus 70, distinct from but connected to the receiver module 72. For example, the signal detection module 76 may be implemented using logic circuitry and / or executable code / machine-readable instructions stored in the memory 78 of the radio device apparatus 70 for execution by the processor 79, thereby performing the functions described herein. For example, the executable code / machine-readable instructions may be stored in one or more memories 78 (e.g., random access memory (RAM), read-only memory (ROM), flash memory, magnetic storage, optical storage, etc.) suitable for storing one or more instruction sets (e.g., application software, firmware, operating system, applets, etc.), data (e.g., configuration parameters, operating parameters and / or thresholds, collected data, processed data, etc.). One or more memories 78 may include processor-readable memory for use by one or more processors 79 to execute code segments and / or utilize data provided therein to perform the functions of the signal detection module 76 as described herein. Alternatively, the signal detection module 76 may include one or more dedicated processors (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), graphics processing units (GPUs), etc.) configured to perform the functions of the signal detection module 76 as described herein. The signal detection module 76 includes a 5G data plane clock servo module 42 according to the present invention.

[0072] Figure 6 This is a schematic block diagram of the TSN time domain 14 and 5G time domain 16 of the TSN network, outlining the method steps of the present invention.

[0073] UPF 20 transmits gPTP messages between TSN terminal stations to synchronize time across multiple TSN time domains, as is known in other contexts. Simultaneously, the NW-TT module 26 in UPF 20 also needs to synchronize its time with the 5G GM 18 in the 5G time domain 16. According to the present invention, the steps for synchronizing the time of the NW-TT module 26 with the 5G GM 18 in the 5G time domain 16 include a first part ①, which includes UPF 20 receiving or acquiring the 5G GM 18 clock via the underlying gPTP-compatible transport network through the UPF N3 interface 24 by receiving one or more gPTP messages, and then determining or calculating a first time offset value between the 5G GM 18 and the UPF N3 interface 24 based on the information received in the one or more gPTP messages. N3 In Part 2, UPF 20 uses a defined first time offset value. N3 The time of UPF N3 interface 24 is adjusted to synchronize the time between UPF N3 interface 24 and 5G GM 18. Preferably, UPF 20 uses a time offset value. N3 The smoothing value of the UPF N3 interface 24 is adjusted to adjust the time. In Part 3③, the UPF 20 also determines a second time offset value between the UPF N3 interface 24 and the NW-TT module 26. NW-TT ), and use the determined second time offset value (Offset) NW-TT The time of the NW-TT module 26 is adjusted to synchronize the time between the NW-TT module 26 and the 5G GM 18. Preferably, the UPF 20 uses a second time offset value. NW-TT The smoothing value is used to adjust the time of the NW-TT module 26.

[0074] In Part 2, UFPF 20 preferably uses a determined first time offset value. N3 This involves determining the clock frequency adjustment value for the UPF N3 interface 24, and using that UPF N3 interface clock frequency adjustment value to adjust the clock frequency of the UPF N3 interface 24. This may involve using a first time offset value (Offset). N3 ) as the input to the 5G data plane clock servo module 42 in UPF 20, and according to the first time offset value (Offset) N3 ), and perform the steps of part ② on the 5G data plane clock servo module.

[0075] In Part 3, UFPF 20 preferably uses a second time offset value (Offset). NW-TTThis involves determining the clock frequency adjustment value for the NW-TT module 26 and using that value to adjust the clock frequency of the NW-TT module 26. This may involve using a second time offset value. NW-TT ) as the input to the 5G data plane clock servo module 42, and according to the second time offset value (Offset) NW-TT Step ③ is executed on the 5G data plane clock servo module 42.

[0076] Figure 7 It is a timing diagram showing the transmission of time synchronization information among three adjacent time-aware systems in a TSN network implementing the method of the present invention.

[0077] One or more PTP or gPTP messages received by the UPF N3 interface 24 of UPF 20 contain synchronization information in point-to-point or end-to-end mode. The method includes the following steps: storing a first time T1 associated with sending a PTP or gPTP “Pdelay_Req” message; extracting a second time T2 from a PTP or gPTP “Pdelay_Resp” message; extracting a third time T3 from a PTP or gPTP “Pdelay_Resp_Follow_Up” message; storing a fourth time T4 associated with receiving a PTP or gPTP “Pdelay_Resp” message; and then determining the UPF N3 interface delay (Delay) according to a formula. N3 ):

[0078] Delay N3 = [(T2–T1)+(T4–T3)] / 2.

[0079] The first time offset between the 5G GM 18 and the UPF N3 interface 24 (Offset) N3 ) is the delay (Offset) from the UPF N3 interface N3 Exported to obtain the first time offset value between the 5G GM 18 and UPF N3 interface 24. N3 The method includes the following steps: extracting the elapsed time value of the fifth time T5 and the correction field (CF) from the PTP or gPTP "Follow_Up" message; storing the sixth time T6 related to receiving the PTP or gPTP "Synchronization Message"; and then determining the first time offset value between the 5GGM and UPF N3 interfaces according to the formula. N3 ):

[0080] Offset N3 =(T6–T5)-Delay N3 – The time value elapsed for CF.

[0081] The CF carries the elapsed time in the time-aware system and the elapsed time of the link before the last hop on the path between the 5G GM 18 and the time-aware system. In this case, it is the transmission time from the 5G GM master port to the gNB master port.

[0082] The second time offset between the UPF N3 interface and the NW-TT module (Offset) NW-TT The clock of the NW-TT module 26 and the synchronization clock of the UPF N3 interface 24 are determined by the following formula:

[0083] Offset NW-TT =T NW-TT –T N3 ,

[0084] Where T NW-TT The time is obtained from the NW-TT module clock; T N3 The time is obtained from the synchronous clock of the UPF N3 interface.

[0085] The second time offset between the UPF N3 interface and the NW-TT module (Offset) NW-TT The value is determined or calculated by the 5G data plane clock offset controller 47.

[0086] Figure 8 This is a functional block diagram of the 5G data plane clock servo module 42 that implements the method steps of the present invention.

[0087] In this method, the first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT It is used as input 80 of the 5G data plane clock servo module 42 in UPF 20.

[0088] The method may include: in step 82, determining the received first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT The method checks whether the time offset is greater than a predetermined, calculated, or selected time period. This predetermined, calculated, or selected time period may take different values ​​depending on the communication network scenario and / or application. In one embodiment, the predetermined, calculated, or selected time period may be equal to 1 second. If so, the method may control the 5G data plane clock servo module 42 to set the first time offset value (Offset) in step 81. N3 The time offset is sent to the 5G data plane clock offset controller 47 to adjust the time of the UPF N3 interface 24 relative to the 5G GM 18, or a second time offset value is sent. NW-TTThe clock offset controller 47 is used to adjust the time of the NW-TT module 26 relative to the 5G GM 18.

[0089] If in step 82 the result is "No", then the received first time offset value (Offset) is used. N3 or the second time offset value (Offset) NW-TT This serves as the input to the 5G data plane clock filter 44. The 5G data plane clock filter 44 includes a moving average filter, which receives the first time offset value (Offset) as input. N3 or the second time offset value (Offset) NW-TT When receiving the first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT The clock offset is smoothed to attenuate impulse noise and generate a smooth clock offset output for the 5G data plane clock offset controller 47.

[0090] refer to Figure 9 It provides a functional block diagram of the 5G data plane clock filter 44. The moving average filter is based on a low-pass finite impulse response (FIR) filter, which is typically used for smoothing arrays. In this case, it is used to smooth the offset in part ②. N3 Or the Offset in part ③ NW-TT Impulse noise (sometimes with large offsets) may be caused by delayed execution cycles due to sudden events or interruptions in the processing load. The 5G data plane clock filter 44 attenuates impulse noise to prevent jitter from entering the clock servo module 42.

[0091] exist Figure 9 In this context, the unit delay is preferably the z-th degree of the Z-transform symbol. -1 Operator. Clock offset output y from the moving average filter. [n] It is the average of two samples, given by the following formula:

[0092]

[0093] Refer again Figure 8 The method includes: using a 5G data plane proportional-integral (PI) controller 45 to receive a first time offset value. N3 or the second time offset value (Offset) NW-TT It provides a smooth clock offset output and generates a clock frequency adjustment value u(t) that coordinates the UPF N3 interface time with the 5G GM time or the NW-TT module time with the UPF N3 interface time.

[0094] refer to Figure 10It provides a functional block diagram of a 5G data plane PI controller 45, where the proportional (P) term tracks and corrects the direct input, i.e., the time difference between two clocks, the integral (I) term tracks and corrects the steady-state error, i.e., the frequency difference between two clocks, and K... p and K i The parameters can be adjusted statically or dynamically according to the deployment scenario, such as:

[0095]

[0096] Where K p It's the proportional gain, an adjustable parameter;

[0097] K i It's the integral gain, an adjustable parameter;

[0098] e(t) is the clock error (offset) between the 5G GM 18 and the UPF N3 interface 24 or the NW-TT module 26;

[0099] t is time or instantaneous time (current time t);

[0100] τ is the integration variable (its value ranges from time 0 to the current time t).

[0101] The method also includes: using a 5G data plane clock frequency regulator 46 to receive the clock frequency adjustment u(t) value of the UPF N3 interface or the NW-TT module, and adjusting their respective clock frequencies accordingly.

[0102] The 5G data plane clock offset controller 47 receives a smooth clock offset output and adjusts the clock of the UPF N3 interface or the clock of the NW-TT module.

[0103] In short, in part ②, the method allows UPF 20 to use the first offset from part ①. N3 This serves as an input to the 5G data plane clock servo module 42 of the present invention to achieve time synchronization between the UPF N3 interface 24 and the 5G GM 18. In part ③, the method allows the UPF 20 to use a second offset calculated by the 5G data plane clock offset controller 47. NW-TT As an input to the 5G data plane clock servo module 42, it enables time synchronization between the NW-TT module 26 and the UPF N3 interface 24, thereby maintaining high-precision time synchronization between the NW-TT module 26 on the UPF 20 and the 5G GM 18.

[0104] Parts ② and ③ share the same 5G data plane clock servo module 42 to adjust the clock frequency and timing offset. The 5G data plane filter 44 and the 5G data plane PI controller 46 in the clock servo adjust the offset to generate a clock frequency adjustment value to constrain the clock frequency.

[0105] This invention also provides a 5G data plane clock servo module in a UPF module, used to synchronize the network-side Time-Sensitive Network (TSN) converter (NW-TT) module within the user plane function (UPF) of a 5G communication network with the 5G master clock (GM) in the 5G time domain of the 5G communication network. The 5G data plane clock servo module includes: a module for receiving a first time offset value between the 5G GM and the UPF N3 interface. N3 Or the second time offset value between the UPF N3 interface and the NW-TT module (Offset) NW-TT The module, where the first time offset value (Offset) N3 The second time offset value is determined by one or more Precision Time Protocol (PTP) or Universal Precision Time Protocol (gPTP) messages received from the N3 interface. NW-TT The clock speed is determined by the hardware clock of the NW-TT module and the synchronization clock of the UPF N3 interface. The 5G data plane clock servo module also includes: a mechanism for determining the received first time offset value. N3 or the second time offset value (Offset) NW-TT Whether the time offset is greater than a predetermined, calculated, or selected time period; and the 5G data plane clock filter, which includes a moving average filter, upon receiving a first time offset value (Offset). N3 or the second time offset value (Offset) NW-TT When receiving the first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT The clock offset is smoothed to attenuate impulse noise and produce a smooth clock offset output for the 5G data plane clock offset controller.

[0106] The 5G data plane clock servo module also includes a 5G data plane proportional-integral (PI) controller for receiving the first time offset value. N3 or the second time offset value (Offset) NW-TTThe system provides a smooth clock offset output to generate a clock frequency adjustment u(t) value to coordinate the UPF N3 interface time with the 5G GM time, or to coordinate the NW-TT module time with the UPF N3 interface time; and a 5G data plane clock frequency adjuster to receive the clock frequency adjustment u(t) value from the UPF N3 interface or the NW-TT module to adjust their respective clock frequencies accordingly; wherein, the 5G data plane clock offset controller receives the smooth clock offset output and adjusts the clock of the UPF N3 interface or the clock of the NW-TT module.

[0107] The present invention also provides a UPF module for synchronizing a network-side Time-Sensitive Network (TSN) converter (NW-TT) module within the user plane function (UPF) of a 5G communication network with the 5G master clock (GM) in the 5G time domain of the 5G communication network. The module includes a memory storing machine-readable instructions and a processor for executing the machine-readable instructions, such that when the processor executes the machine-readable instructions, it configures the UPF module to perform the method steps of any of the appended method claims.

[0108] The present invention also provides a non-transitory computer-readable medium for storing machine-readable instructions, wherein, when executed by a processor, the machine-readable instructions configure the processor to implement the method of any one of the appended method claims.

[0109] The above-described apparatus can be implemented, at least in part, using software. Those skilled in the art will understand that the above-described apparatus can be implemented, at least in part, using general-purpose computer equipment or using custom-made equipment.

[0110] In this document, various aspects of the methods and apparatus described herein can be executed on any device, including communication systems. The programmatic aspects of this technology can be considered as a “product” or “article,” typically carried or embodied in a machine-readable medium in the form of executable code and / or associated data. “Storage” media include any or all memory, or related modules thereof, of mobile stations, computers, processors, or similar devices, such as various semiconductor memories, tape drives, disk drives, etc., which can provide storage for software programming at any time. All or part of the software can sometimes be communicated via the Internet or various other telecommunications networks. For example, such communication can load software from one computer or processor to another. Therefore, another type of medium that can carry software elements includes light waves, radio waves, and electromagnetic waves, used, for example, at physical interfaces between local devices, via wired and optical terrestrial networks, and via various air links. Physical elements carrying such waves, such as wired or wireless links, optical links, etc., can also be considered as media carrying software. As used herein, unless limited to tangible, non-transitory “storage” media, the term “computer or machine-readable medium” refers to any medium involved in providing instructions to a processor for execution.

[0111] While the invention has been described and illustrated in detail in the accompanying drawings and the foregoing description, it should be considered illustrative rather than restrictive. It should be understood that exemplary embodiments are shown and described only and do not limit the scope of the invention in any way. It will be understood that any feature described herein can be used in any embodiment. The illustrative embodiments do not exclude each other or other embodiments not mentioned herein. Therefore, the invention also provides embodiments that include combinations of one or more of the illustrative embodiments described above. Modifications and variations can be made to the invention without departing from its spirit and scope; therefore, only the limitations set forth in the appended claims should be applied.

[0112] In the appended claims and the foregoing description of the invention, unless the context requires otherwise due to explicit language or necessary implication, the word "comprising" or variations such as "including" are used in an inclusive sense, that is, specifying the presence of the stated features but not excluding the presence or addition of further features in various embodiments of the invention.

[0113] It should be understood that if any prior art publications are mentioned in this document, such reference does not constitute an admission that such publications constitute part of the general knowledge in the art.

Claims

1. A method for synchronizing a network-side time-sensitive network (TSN) converter (NW-TT) module within the user plane function (UPF) of a communication network with the master clock (GM) in the time domain of the communication network, the method comprising the following steps: Receive one or more Precision Time Protocol (PTP) or Universal Precision Time Protocol (gPTP) messages on the N3 interface of the UPF; Based on the information received in one or more PTP or gPTP messages, a first time offset value is determined between the GM and the UPF N3 interface. N3 ); using the determined first time offset value (Offset N3 ) to adjust the time of the UPF N3 interface, so that the UPF N3 interface is time-synchronized with the GM; determining a second time offset value (Offset NW-TT ) between the UPF N3 interface and the NW-TT module; and using the determined second time offset value (Offset NW-TT ) to adjust the time of the NW-TT module to synchronize the time between the NW-TT module and the GM.

2. The method according to claim 1, comprising the following steps: determining a first time offset value (Offset N3 ) using the determined first time offset value (Offset N3 ) to determine a UPF N3 interface clock frequency adjustment value; and Adjust the clock frequency of the UPF N3 interface using the UPF N3 interface clock frequency adjustment value.

3. The method according to claim 2, comprising the following steps: determining a NW-TT module clock frequency adjustment value using the second time offset value (Offset NW-TT ); and Adjust the clock frequency of the NW-TT module using the clock frequency adjustment value of the NW-TT module.

4. The method according to claim 1, wherein the one or more PTP or gPTP messages are received from a network node in the time domain of the communication network.

5. The method according to claim 4, wherein the network node includes a base station (gNB).

6. The method of claim 1, wherein a second time offset value (Offset NW-TT ) between the UPF N3 interface and the NW-TT module is determined using information obtained at an N6 interface of the UPF.

7. The method according to claim 3, comprising: A data plane clock servo module is provided in the UPF; using the first time offset value (Offset N3 ) as an input to the data plane clock servo module; as well as According to the first time offset value (Offset N3 ), the following steps are performed on the data plane clock servo module: Adjust the time of the UPF N3 interface to synchronize the time between the UPF N3 interface and the GM; Determine the UPF N3 interface clock frequency adjustment value; and Adjust the clock frequency of the UPF N3 interface using the UPF N3 interface clock frequency adjustment value.

8. The method of claim 7, comprising: using the second time offset value (Offset NW-TT ) as an input to the data plane clock servo module; as well as According to the second time offset value (Offset NW-TT ), the data plane clock servo module performs the following steps: Adjust the time of the NW-TT module to synchronize the time between the NW-TT module and the GM; Determine the clock frequency adjustment value of the NW-TT module; and Adjust the clock frequency of the NW-TT module using the clock frequency adjustment value of the NW-TT module.

9. The method of claim 8, wherein the one or more PTP or gPTP messages received by the UPF N3 interface contain synchronization information in point-to-point or end-to-end mode, the method comprising the following steps: Store the first time T1, which is related to sending a PTP or gPTP Pdelay_Req message; Extract the second time T2 from the PTP or gPTP Pdelay_Resp message; Extract the third time T3 from the PTP or gPTP Pdelay_Resp_Follow_Up message; Store the fourth time T4, which is related to receiving a PTP or gPTP Pdelay_Resp message; as well as The UPF N3 interface delay (Delay N3 ) is determined from the following equation: Delay N3 = [(T2 - T1) + (T4 - T3)] / 2.

10. The method of claim 9, comprising the following steps: Extract the time value of the fifth time T5 and the correction field (CF) from the PTP or gPTP Follow_Up message; Store the sixth time T6; the sixth time T6 is related to receiving PTP or gPTP synchronization messages; as well as The first time offset value (OffsetGM-UPF) between the GM and the UPF N3 interface is determined by the following equation: N3 ): Offset N3 = (T6 - T5) - Delay N3 - CF elapsed time value.

11. The method of claim 10, wherein the second time offset value between the UPF N3 interface and the NW-TT module (Offset) NW-TT The clock speed is determined by the hardware clock of the NW-TT module and the synchronization clock of the UPF N3 interface according to the following formula: Offset NW-TT = T NW-TT - T N3 , Where T NW-TT The time is obtained from the clock of the NW-TT module; T N3 The time is obtained from the synchronization clock of the UPF N3 interface.

12. The method of claim 11, wherein the data plane clock servo module in the UPF receives the first time offset value (Offset). N3 ) or the second time offset value (Offset) NW-TT As input, the method includes the following steps: Determine the received first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT If the time offset value is greater than a predetermined, calculated, or selected time period, then the data plane clock servo module is controlled to adjust the first time offset value (Offset). N3 ) or the second time offset value (Offset) NW-TT The received first time offset value is sent to the data plane clock servo module's data plane clock offset controller to adjust the time of the UPF N3 interface or the time of the NW-TT module; if not, the received first time offset value is used. N3 or the second time offset value (Offset) NW-TT () serves as the input to the data plane clock filter of the data plane clock servo module.

13. The method of claim 12, wherein the predetermined, calculated, or selected time period takes different values ​​depending on different communication network scenarios and / or applications.

14. The method of claim 12, wherein the data plane clock filter comprises a moving average filter, and upon receiving the first time offset value (Offset) N3 ) or the second time offset value (Offset) NW-TT When the received first time offset value (Offset) is... N3 or the second time offset value (Offset) NW-TT The clock offset is smoothed to attenuate impulse noise, thereby generating a smooth clock offset output for the data plane clock offset controller.

15. The method of claim 14, wherein the data plane proportional-integral (PI) controller of the data plane clock servo module receives the first time offset value (Offset). N3 or the second time offset value (Offset) NW-TT The system outputs a smooth clock offset and generates a clock frequency adjustment value u(t) that coordinates the UPF N3 interface time with the GM time, or coordinates the NW-TT module time with the UPF N3 interface time.

16. The method according to claim 15, wherein the data plane clock frequency adjuster of the data plane clock servo module receives the clock frequency adjustment u(t) value of the UPF N3 interface or the NW-TT module, and adjusts the respective clock frequency accordingly.

17. The method of claim 14, wherein the data plane clock offset controller receives the smoothed clock offset output and adjusts the clock of the UPF N3 interface or the clock of the NW-TT module.

18. A UPF module for synchronizing a network-side time-sensitive network (TSN) converter (NW-TT) module within the user plane function (UPF) of a communication network with a master clock (GM) in the time domain of the communication network, the module comprising: Memory, used to store machine-readable instructions; as well as A processor, configured to execute the machine-readable instructions, wherein when the processor executes the machine-readable instructions, it configures the UPF module to perform the following steps: Receive one or more Precision Time Protocol (PTP) or Universal Precision Time Protocol (gPTP) messages on the N3 interface of the UPF; Based on the information received in one or more PTP or gPTP messages, a first time offset value is determined between the GM and the UPF N3 interface. N3 ); using the determined first time offset value (Offset N3 ), adjust the time of the UPF N3 interface to synchronize the time between the UPF N3 interface and the GM; determining a second time offset value (Offset NW-TT ) between the UPF N3 interface and the NW-TT module; and using the determined second time offset value (Offset NW-TT ) to adjust the time of the NW-TT module to synchronize the time between the NW-TT module and the GM.

19. The method of claim 18, wherein: Using the determined first time offset value (Offset) N3 The steps for adjusting the time of the UPF N3 interface include: using the determined first time offset value (Offset) N3 The smoothing value is used to adjust the timing of the UPF N3 interface; and using the determined second time offset value (Offset NW-TT ) to adjust the time of the NW-TT module. The step of adjusting the time of the NW-TT module using the determined second time offset value (Offset NW-TT ) comprises using a smoothed value of the second time offset value (Offset 20. A data plane clock servo module in a UPF module, used to synchronize a network-side Time-Sensitive Network (TSN) converter (NW-TT) module within the user plane function (UPF) of a communication network with the master clock (GM) in the time domain of the communication network, the data plane clock servo module comprising: The first module is used to receive the first time offset value between the GM and the UPF N3 interface. N3 or the second time offset value between the UPFN3 interface and the NW-TT module. NW-TT The first time offset value (Offset) N3 The second time offset value is determined by one or more Precision Time Protocol (PTP) or Universal Precision Time Protocol (gPTP) messages received by the N3 interface. NW-TT The clock speed is determined by the hardware clock of the NW-TT module and the synchronization clock of the UPF N3 interface. The second module is used to determine the received first time offset value (Offset). N3 or the second time offset value (Offset) NW-TT Whether it is greater than a predetermined, calculated, or selected time period; The data plane clock filter includes a moving average filter, which, upon receiving the first time offset value (Offset) N3 or the second time offset value (Offset) NW-TT When the received first time offset value (Offset) is... N3 or the second time offset value (Offset) NW-TT The clock offset is smoothed to attenuate impulse noise and generate a smooth clock offset output for the data plane clock offset controller. A data plane proportional-integral (PI) controller is used to receive the first time offset value (Offset). N3 or the second time offset value (Offset) NW-TT The smooth clock offset output of the ) generates a clock frequency adjustment u(t) value, which coordinates the UPF N3 interface time with the GM time, or coordinates the NW-TT module time with the UPF N3 interface time; as well as A data plane clock frequency adjuster is used to receive the clock frequency adjustment u(t) value from the UPF N3 interface or the NW-TT module, so as to adjust their respective clock frequencies accordingly. The data plane clock offset controller receives the smoothed clock offset output and adjusts the clock of the UPF N3 interface or the clock of the NW-TT module.