Block copolymers and methods for lithography and methods of manufacturing semiconductor devices

Abstract

The inventive concept relates to a block polymer capable of self-assembly and self-healing for photolithography, a method for photolithography, and a method of manufacturing a semiconductor device, and more particularly, to a block copolymer including a first block including a repeating unit of a polymerized siloxane and a second block including a repeating unit of a polymerized azophenoxyalkanol acrylate. The azophenoxyalkanol can include a linear or branched alkylene group of 1 to 10 carbon atoms, the number of repeating units of the polymerized siloxane is 60 to 80, and the number of repeating units of the polymerized azophenoxyalkanol acrylate is 15 to 25. The block polymer has a columnar phase.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2022-0058206, filed on May 12, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a self-assembling and self-healing block copolymer for photolithography and a photolithography method using the block copolymer. Background Technology

[0003] The self-assembly technology of block copolymers has attracted attention as a next-generation photolithography technique. Since the self-assembly of block copolymers utilizes the spontaneous thermodynamic behavior between polymers, fine patterns can be fabricated based on small molecular weights and high Flory-Huggins interaction parameters.

[0004] For example, fine patterns can be formed by self-assembly of polystyrene-polymethyl methacrylate block copolymers (PS-b-PMMA). However, to form smaller nanopatterns, block copolymers with higher Flory-Huggins interaction parameters compared to PS-b-PMMA are required. Furthermore, the block copolymers need to have a narrow molecular weight distribution and clear interfaces between the two domains.

[0005] To apply block copolymer self-assembly technology to photolithography, defect-free nanopatterns are required. Furthermore, the ability to control the directional self-assembly (DSA) of nanopatterns over large areas is essential. Typically, DSA utilizes epitaxial self-assembly or graphite epitaxy. Epitaxial self-assembly forms uniform nanopatterns from block copolymers, while graphite epitaxy uses guided trenches formed through an etching process to control the arrangement of the nanopatterns. Recently, DSA methods using electric field annealing or zone annealing have been proposed. Summary of the Invention

[0006] The objective of this disclosure is to provide a self-assembling and self-healing block copolymer for photolithography.

[0007] Another objective addressed by this disclosure is to provide a photolithography method using the block copolymer.

[0008] According to an embodiment of the inventive concept, a block copolymer for photolithography includes: a first block comprising a first repeating unit of Formula 1; and a second block comprising a second repeating unit of Formula 2.

[0009] [Formula 1]

[0010]

[0011] R1 and R2 are each independently hydrogen or a straight-chain or branched alkyl group with 1 to 10 carbon atoms, and "x" is an integer from 60 to 80.

[0012] [Equation 2]

[0013]

[0014] R3 is a straight-chain or branched alkylene group with 1 to 10 carbon atoms, "y" is an integer from 15 to 25, and the block copolymer may have a columnar phase.

[0015] According to another embodiment of the inventive concept, a photolithography method includes: forming a polymer layer comprising a block copolymer on a substrate; applying an electric field to the polymer layer to form a first nanostructure and a second nanostructure, the first nanostructure and the second nanostructure extending parallel to each other in a first direction; and selectively removing the first nanostructure. The block copolymer may include: a first block comprising repeating units of polymerized siloxanes; and a second block comprising repeating units of polymerized azophenoxyalkanol acrylates. The azophenoxyalkanol may comprise a straight-chain or branched alkylene group of 1 to 10 carbon atoms, the number of repeating units of the polymerized siloxane may be 60 to 80, the number of repeating units of the polymerized azophenoxyalkanol acrylates may be 15 to 25, the first nanostructure may comprise the first block, and the second nanostructure may comprise the second block.

[0016] According to another embodiment of the inventive concept, a method of manufacturing a semiconductor device includes: forming a transistor on a substrate; and forming wiring extending in a first direction on the transistor. The step of forming the wiring may include: forming an etch target layer on the transistor; forming a polymer layer comprising a block copolymer on the etch target layer; applying an electric field to the polymer layer to form a first nanostructure and a second nanostructure, the first nanostructure and the second nanostructure extending parallel to each other in the first direction; selectively removing the first nanostructure; and patterning the etch target layer using the second nanostructure as an etch mask. The block copolymer may include: a first block, the first block being a polymer with a silicon-oxygen (Si-O) backbone; and a second block, the second block comprising repeating units of polymerized monomers, said monomers comprising azobenzene. The volume ratio of the first block to the block copolymer may be from about 0.45 to about 0.55, each first nanostructure in the first nanostructure may include the first block, and each second nanostructure in the second nanostructure may include the second block. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and form part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0018] Figure 1 This is a conceptual diagram used to explain the block copolymers according to embodiments of the inventive concept;

[0019] Figure 2A and Figure 2B It is a conceptual diagram used to explain the phase (or structure) of self-assembled block copolymers;

[0020] Figure 3 This is a conceptual diagram illustrating a specific chemical structure of a block copolymer according to an embodiment of the inventive concept;

[0021] Figure 4 It is a graph showing the small-angle X-ray scattering data of a block copolymer according to an example embodiment of the inventive concept;

[0022] Figure 5A This is a graph showing the small-angle X-ray scattering data of the block copolymer according to Comparative Example 1;

[0023] Figure 5B This is a graph showing the small-angle X-ray scattering data of the block copolymer according to Comparative Example 2;

[0024] Figure 6 The H of the block copolymer of the inventive concept prepared by experimental example of the inventive concept is shown. 1 -NMR data;

[0025] Figure 7 DSC data of the block copolymer of the inventive concept prepared by experimental examples of the inventive concept are shown;

[0026] Figure 8A and Figure 8B Transmission electron microscopy (TEM) and atomic force microscopy (AFM) images of block copolymers prepared by experimental examples of the inventive concept are shown.

[0027] Figure 9 An image of a polymer layer obtained by self-assembly of a block copolymer according to an inventive concept is shown;

[0028] Figure 10 Images illustrating the self-healing process of the block copolymer demonstrating the inventive concept are shown;

[0029] Figures 11 to 15 It is a perspective view used to explain the photolithography method according to an embodiment of the inventive concept;

[0030] Figures 16 to 18 This is a perspective view used to explain a self-healing method for nanostructures according to embodiments of the inventive concept;

[0031] Figure 19 It is a plan view used to explain the semiconductor device according to the embodiments of the inventive concept;

[0032] Figures 20A to 20D It is along Figure 19 Sectional views of lines A-A', B-B', C-C', and D-D' in the diagram;

[0033] Figure 21 A perspective view of a display device according to an embodiment of the inventive concept; and

[0034] Figure 22 It is along Figure 21 A sectional view of line A-A' in the diagram. Detailed Implementation

[0035] To fully understand the structure and effects of the inventive concept, preferred embodiments will be explained with reference to the accompanying drawings. However, the inventive concept can be implemented in various forms with various modifications and should not be construed as being limited to the embodiments set forth herein. Embodiments are provided to complete the disclosure of the inventive concept through explanation of the embodiments and to fully inform those skilled in the art to which the inventive concept pertains.

[0036] In this disclosure, it will be understood that when an element is referred to as being on another element, the element may be formed directly on said other element, or a third intermediary element may be present. In the accompanying drawings, the thickness of the elements may be exaggerated for the effective interpretation of the technical content. In this disclosure, parts (portions) designated by the same reference numerals always represent the same construction elements.

[0037] The exemplary embodiments are described herein with reference to sectional views and / or plan views illustrating idealized example embodiments. In the drawings, the thickness of layers and regions may be exaggerated for effective interpretation of the technical content. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, nor are they intended to limit the scope of the inventive concept. In the various exemplary embodiments disclosed, although various elements may be described herein using terms such as "first," "second," "third," etc., these elements should not be limited by these terms. These terms are used only to distinguish one element from another. The embodiments explained and illustrated herein may include complementary embodiments thereof.

[0038] The terminology used herein is for the purpose of describing exemplary embodiments only and is not intended to be limiting of the inventive concept. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated elements but do not exclude the presence or addition of one or more other elements.

[0039] In this disclosure, "alkyl" means a monovalent functional group having a straight or branched type with 1 to 10 carbon atoms. In this disclosure, "alkylene" means a divalent functional group having a straight or branched type with 1 to 10 carbon atoms.

[0040] Figure 1 This is a conceptual diagram used to explain block copolymers according to embodiments of the inventive concept. (Refer to...) Figure 1 The block copolymer may include a first block BLK1 and a second block BLK2, wherein the first block BLK1 includes repeating units obtained by polymerizing a first monomer, and the second block BLK2 includes repeating units obtained by polymerizing a second monomer. The first block BLK1 and the second block BLK2 may be bonded to each other by covalent bonds CVB.

[0041] The block copolymers according to the inventive concept can have a Flory-Huggins interaction parameter (χ) of about 0.25 to about 0.5. More specifically, the block copolymers according to the inventive concept can have a χ value of about 0.3 to about 0.5. Generally, block copolymers having a χ value greater than about 0.25 can be considered to have a high Flory-Huggins interaction parameter. The Flory-Huggins interaction parameter is a value that represents the degree to which the first block BLK1 and the second block BLK2 are dissimilar to each other. In other words, the block copolymers according to the inventive concept can have a large repulsive force between the first block BLK1 and the second block BLK2. Therefore, the block copolymers according to the inventive concept can have a specific phase (or structure) through self-assembly even with a low degree of polymerization (N).

[0042] Figure 2A and Figure 2B It is a conceptual diagram used to explain the phase (or structure) of self-assembled block copolymers.

[0043] Reference Figure 2A , Figure 1 The block copolymer can self-assemble to have a lamellar phase. The lamellar phase may include a first layer composed of a first block BLK1 and a second layer composed of a second block BLK2. The first and second layers may be stacked alternately.

[0044] Reference Figure 2B , Figure 1 Block copolymers can self-assemble to have a cylindrical phase. For example, the cylindrical phase can include a columnar (or cylindrical) structure composed of a second block BLK2. The first block BLK1 can fill the spaces between the columnar structures composed of the second block BLK2.

[0045] Depending on the degree of polymerization (N) and the volume fractions of the first block BLK1 and the second block BLK2, the block copolymer can have a layered phase, a columnar phase, or a mixture of layered and columnar phases.

[0046] The block copolymers according to embodiments of the inventive concept can have a columnar phase by controlling the respective volume fractions of the first block BLK1 and the second block BLK2 at a small degree of polymerization (N) of about 75 to about 105.

[0047] Refer again Figure 1 The first block BLK1 of the block copolymer according to an embodiment of the inventive concept may include repeating units of Formula 1.

[0048] [Formula 1]

[0049]

[0050] In Formula 1, R1 and R2 can each be an alkyl group with one to ten carbon atoms, either straight or branched. “x” can be an integer from 60 to 80, for example, an integer between 60 and 80. As shown in Formula 1, the first block BLK1 can be a polymer with a silicon-oxygen (Si-O) backbone.

[0051] The second block BLK2 of the block copolymer according to an embodiment of the inventive concept may include repeating units of Formula 2.

[0052] [Equation 2]

[0053]

[0054] In Formula 2, R3 can be a straight-chain or branched alkylene group with 1 to 10 carbon atoms. “y” can be an integer from 15 to 25, for example, an integer between 15 and 25. As shown in Formula 2, the monomer of the second block BLK2 can include azobenzene.

[0055] Block copolymers according to embodiments of the inventive concept can have a molecular weight of about 5000 g / mol to about 20000 g / mol.

[0056] Figure 3 This is a conceptual diagram illustrating a specific chemical structure of a block copolymer according to an embodiment of the inventive concept. (Refer to...) Figure 3The block copolymer according to the inventive concept may include a first block BLK1 and a second block BLK2, wherein the first block BLK1 includes repeating units obtained by polymerizing a siloxane, and the second block BLK2 includes repeating units obtained by polymerizing azobenzoloxy alkanol acrylate.

[0057] The first monomer MN1 of the first block BLK1 may be a siloxane. In an embodiment, the first monomer MN1 of the first block BLK1 may be a dimethylsiloxane. In other words, the first block BLK1 may include polydimethylsiloxane (PDMS). In another embodiment of the inventive concept, the first monomer MN1 may be a dialkylsiloxane.

[0058] The second monomer MN2 of the second block BLK2 can be an azophenoxyalkanol acrylate. Figure 3 In the chemical structure, "Ar" can be a straight-chain or branched alkylene group with 1 to 10 carbon atoms. In the examples, the second monomer MN2 of the second block BLK2 can be azophenoxyhexyl acrylate.

[0059] Photolithography using block copolymers can involve forming nanostructures with specific pitches on a substrate. However, if the polymer layer is unevenly coated on the substrate, damaged regions can form within the polymer layer due to annealing processes, solvation processes, dust, and material suitability. If an electric field or external field is applied to the polymer layer, the block copolymer can accumulate in the damaged regions, resulting in dewetting. This causes defects in the photolithography process. Furthermore, the polymer layer cannot be reused, making semiconductor processes inefficient.

[0060] The inventive concept can provide a block copolymer capable of self-healing damage to the polymer layer. Therefore, the inventive concept can overcome the shortcomings of photolithography processes using the aforementioned conventional block copolymers.

[0061] When irradiated with light of a specific wavelength, azobenzene can undergo photoisomerization within the molecule, switching between the trans and cis configurations of the double bond relative to the nitrogen atom. In other words, azobenzene is a photosensitive material.

[0062] If an alkyl group is introduced into azobenzene, the azobenzene can be converted from a trans configuration to a cis configuration by irradiation with ultraviolet (UVL) light. Therefore, the chain flowability of the second block BLK2 in the block copolymer can be altered. For example, the UVL light can have a wavelength of approximately 365 nm. If the azobenzene in the second block BLK2 has a cis configuration, the glass transition temperature of the second block BLK2 can be rapidly reduced, and the block copolymer can exhibit liquid-like flowability.

[0063] If the block copolymer of the embodiment is exposed to visible light (VIL), the azobenzene can change from a cis configuration to a trans configuration. Additionally, if a heat transition temperature (HET) is applied to the block copolymer, the azobenzene can change from a cis configuration to a trans configuration. Thus, the chain flowability of the second block BLK2 of the block copolymer can be altered. In the embodiment, the visible light (VIL) can have a wavelength of approximately 470 nm. If the azobenzene of the second block BLK2 has a trans configuration, the glass transition temperature of the second block BLK2 can be rapidly increased, and the block copolymer can exhibit hard, solid-like properties.

[0064] According to embodiments of the inventive concept, a polymer layer is formed by using a block copolymer comprising azobenzene as a photosensitive material, and the damaged area can self-heal even if the polymer layer is damaged. A detailed explanation follows.

[0065] According to embodiments of the inventive concept, a block copolymer can be synthesized by using atom transfer radical polymerization (ATRP) to synthesize a first block BLK1 and a second block BLK2 with different properties. For example, the first block BLK1 is an inorganic polymer based on a silicon-oxygen backbone, and the second block BLK2 is an organic polymer; therefore, they can have different properties from each other. The repulsive force between the first block BLK1 and the second block BLK2 can be very large. As a result, the block copolymer according to the inventive concept can have a high Flory-Huggins interaction parameter. Because the block copolymer according to the inventive concept has a high Flory-Huggins interaction parameter, self-assembly can be easily performed even if the molecular weight of the block copolymer is low (i.e., even if the degree of polymerization is small), and a columnar phase can be achieved.

[0066] Refer again Figure 3The number (x) of repeating units (of the first monomer MN1) of the block copolymer according to the inventive concept can be 60 to 80. The number (y) of repeating units (of the second monomer MN2) of the block copolymer according to the inventive concept can be 15 to 25. The degree of polymerization (N = x + y) of the block copolymer according to the inventive concept can be 75 to 105. In other words, the size (or volume) of the block copolymer according to the inventive concept can be smaller than the size (or volume) of block copolymers used in conventional photolithography processes. Therefore, the nanostructures formed from the block copolymer according to the inventive concept can have linewidths of about 8 nm to about 20 nm, which will be explained in detail later.

[0067] If the product of the Flory-Huggins interaction parameter (χ) and the degree of polymerization (N) (χ×N) is greater than about 10.5, the block copolymer can self-assemble into a phase having a layered phase, a columnar phase, or a mixture of layered and columnar phases. Depending on the volume fraction of each of the first block BLK1 and the second block BLK2, the block copolymer of the inventive concept can have various phases including a spherical phase, a gyroid phase, a columnar phase, a layered phase, and a mixture of layered and columnar phases.

[0068] The block copolymer according to the inventive concept can have a Flory-Huggins interaction parameter (χ) of about 0.25 to about 0.5 (more specifically, about 0.3 to about 0.5). The block copolymer according to the inventive concept has a χ×N value greater than about 10.5 and can have a columnar phase. Specifically, the volume fraction of the first block BLK1 (i.e., the ratio of the volume of the first block BLK1 to the volume of the block copolymer) can be about 0.45 to about 0.55. The volume fraction of the second block BLK2 (i.e., the ratio of the volume of the second block BLK2 to the volume of the block copolymer) can be about 0.45 to about 0.55. If the volume fraction of the first block BLK1 or the second block BLK2 has a value within the above range, the block copolymer according to the inventive concept can have a columnar phase.

[0069] Figure 4 This is a graph showing small-angle X-ray scattering (SAXS) data of a block copolymer according to an example embodiment of the inventive concept. The first block BLK1 of the block copolymer according to the embodiment of the inventive concept may have a volume fraction of about 0.45 to about 0.55. The SAXS of the block copolymer according to this example embodiment was measured, and... Figure 4The obtained data are shown in the figure. The block copolymer of this example has a number-average molecular weight of about 13.3 kg / mol and a dispersion of about 1.10. On the small-angle scattering plot, the polydimethylsiloxane-polyazobenzene block copolymer (i.e., polydimethylsiloxane-polyazophenoxyalkanol acrylate block copolymer) exhibits scattering peaks due to the self-assembly of the first block BLK1 and the second block BLK2.

[0070] Reference Figure 4 The first, second, third, and fourth peaks can have approximately The ratio of the two blocks is given. Therefore, the block copolymer of this example is confirmed to have a columnar phase (or columnar structure). Furthermore, the sum of the linewidths of the first block BLK1 and the second block BLK2 (i.e., the domain spacing between grids) is calculated to be approximately 17.98 nm using Bragg's law with the x-value of the first peak (0.3495452). The domain spacing between grids is the sum of the linewidths of the first block BLK1 and the second block BLK2. For example, the linewidth of either the first block BLK1 or the second block BLK2 is confirmed to be approximately 9 nm. A detailed explanation of this will be given later.

[0071] The volume fraction of the first block BLK1 in the block copolymer according to Comparative Example 1 can be from about 0.35 to about 0.45. Small-angle X-ray scattering of the block copolymer according to Comparative Example 1 was measured, and... Figure 5A The obtained data are shown in the figure. The volume fraction of the first block BLK1 in the block copolymer according to Comparative Example 2 can be from about 0.55 to about 0.65. Small-angle X-ray scattering of the block copolymer according to Comparative Example 2 was measured, and... Figure 5B The obtained data is shown in the figure.

[0072] Reference Figure 5A and Figure 5B As explained above Figure 4 The differences are that peaks of both the layered phase and the columnar phase were measured. In other words, it can be confirmed that the block copolymer according to Comparative Example 1 and the block copolymer according to Comparative Example 2 have a mixed phase of layered and columnar phases.

[0073] Referring to the above Figure 4 , Figure 5A and Figure 5B In order for the block copolymer of the inventive concept to have a single columnar phase, the volume fraction of the first block BLK1 needs to be from about 0.45 to about 0.55. If the volume fraction of the first block BLK1 deviates from the above range, the block copolymer may not have a single columnar phase.

[0074] Conventional block copolymers in Figure 1 The first block BLK1 and the second block BLK2 exhibit conformational symmetry. Therefore, if the volume fraction of the first block BLK1 is from about 0.45 to about 0.55, the block copolymer will have the following characteristics: Figure 2A The layered phase in the middle.

[0075] However, the block copolymer of the inventive concept has very different properties between the first block BLK1 and the second block BLK2, and exhibits conformational asymmetry between them. Specifically, the first block BLK1 of the inventive concept is a polysiloxane (e.g., PDMS) and has soft properties, while the second block BLK2 is a liquid crystal polymer and has hard properties. Therefore, if the volume fraction of the first block BLK1 is from about 0.45 to about 0.55, the block copolymer of the inventive concept can have properties such as... Figure 2B The columnar phase in the middle.

[0076] Experimental Example

[0077] Add 1g of polydimethylsiloxane bromide polymer, 0.03g of cuprous bromide (CuBr), 10g of azophenoxyhexyl acrylate and a magnetic rod to a 100mL flask.

[0078] Polydimethylsiloxane bromide polymers were synthesized via reaction 1 below. The polydimethylsiloxane substrate used in reaction 1 below has an average degree of polymerization of 74.

[0079] [Reaction 1]

[0080]

[0081] Azophenoxyhexyl acrylate was synthesized using a condensation reaction and a Steglich esterification reaction. Azophenoxyhexyl acrylate can be represented by the following formula 3.

[0082] [Formula 3]

[0083]

[0084] An inert atmosphere was created by injecting argon into the flask, and 8 ml of toluene was also injected into the flask. 100 μL of PMDETA (i.e., pentamethyldiethylenetriamine) was then injected into the flask, and the reaction was carried out for approximately 24 to approximately 48 hours while maintaining the temperature at approximately 85°C in an oil bath.

[0085] This reaction can be performed using ATRP between cuprous bromide and polydimethylsiloxane bromide and an initiator in a nonpolar solvent such as toluene. As a result, the block copolymer according to this experimental example can be synthesized via reaction 2 below.

[0086] [Reaction 2]

[0087]

[0088] After the reaction was complete, cuprous bromide was separated by an alumina column. A rotary evaporator was connected to the flask, and the solvent was evaporated. 500 mL of cold methanol was added to the flask to precipitate the solvent, which was then completely dried under vacuum at approximately 50°C (e.g., complete removal of the solvent). Thus, a block copolymer according to an experimental example of the inventive concept was obtained.

[0089] Figure 6 The H of the block copolymer of the inventive concept prepared by experimental example of the inventive concept is shown. 1 -NMR data. (Refer to...) Figure 6 This can confirm the respective volume fractions of the first block BLK1 and the second block BLK2 of the block copolymer.

[0090] exist Figure 6 In the spectrum, the peaks appearing at 7.0 ppm to 8.0 ppm correspond to the H atoms in the benzene ring of azobenzene. The peaks appearing between 3.5 ppm and 3.7 ppm correspond to the H atoms in the CH2 group of the ether group of polydimethylsiloxane. Comparing the integrated values ​​of the peaks based on the number of H atoms confirms this. Figure 3 The ratio of the number of repeating units (x) of the first monomer MN1 to the number of repeating units (y) of the second monomer MN2 is approximately 74:16 to approximately 74:20. More specifically, it was confirmed that the number of repeating units (x) of the first monomer MN1 is 74 and the number of repeating units (y) of the second monomer MN2 is 20.

[0091] In other experimental examples, as described above, the number of repeating units (x) of the first monomer MN1 can be 60 to 80. The number of repeating units (y) of the second monomer MN2 can be 15 to 25. In the experimental examples, the ratio of "y" to "x" (y / x) can be from about 0.2 to about 0.3.

[0092] If "x" and "y" have values ​​within the above range, the block copolymer according to the inventive concept can have a volume fraction of the first block BLK1 of about 0.45 to about 0.55. Therefore, the block copolymer of the inventive concept can have a single columnar phase (refer to the above). Figure 4 (Explanation).

[0093] Figure 7 DSC data for the block copolymer of the inventive concept prepared by experimental example are shown. For the block copolymer prepared by experimental example, heat flow was measured at a heating rate of approximately 20 °C / min and is shown. Figure 7 middle.

[0094] Reference Figure 7 If the azobenzene in the block copolymer has a trans configuration, then during both the first and second heating processes, the glass transition temperature (Tg) will be... g The temperature was measured to be approximately 54°C, and the melting point (T) was... m The temperature was measured to be approximately 78°C.

[0095] If the azobenzene in the block copolymer has a cis structure, then during the first heating process, the glass transition temperature (T) g The temperature was measured to be approximately 1°C. This confirms that the glass transition temperature (T) of the inverted structure is... g Compared to the cis structure, the glass transition temperature (T) g It decreased very significantly.

[0096] In the cis configuration, the liquid crystal (LC) structure of the polyazobenzene (i.e., polyazophenoxyalkanol acrylate) block collapses and does not exhibit a melting point (T). m If the temperature exceeds approximately 90°C, it can be determined that the cis-structured block copolymer transforms into the trans-structure. For example, if a second heating process is performed after the first heating process, the same heat flow as the trans-structure explained above is measured. This means that the block copolymer transforms from a cis-structure to a trans-structure through the first heating process.

[0097] Refer again Figure 3 The block copolymers prepared through experimental examples exhibit changes in physical properties due to photoisomerization. The trans configuration of the block copolymers possesses high thermal stability and a hard, solid-like state. However, the cis configuration is thermally unstable and exhibits a fluid, liquid-like state. (See above reference...) Figure 7 The explanation is that the cis structure is thermally unstable and can be easily transformed into the trans structure by heating.

[0098] When a block copolymer of the inventive concept is irradiated with ultraviolet light of a specific wavelength, the trans-structured azobenzene can absorb light energy and be excited. Therefore, azobenzene can transform into the unstable cis-structure. If azobenzene has a cis-structure, it may not be possible to achieve good stacking between azobenzene molecules, and a large amount of steric hindrance will be generated between polymer chains. Therefore, the glass transition temperature of the block copolymer can be reduced (see...). Figure 7 If the block copolymer of the inventive concept has a trans structure, the block copolymer is a powder-type solid. However, if the block copolymer has a cis structure, the block copolymer is viscous and exhibits flowability.

[0099] Figure 8A and Figure 8BTransmission electron microscopy (TEM) and atomic force microscopy (AFM) images of block copolymers prepared by experimental examples of the inventive concept are shown.

[0100] A bulk-state block copolymer was placed on a TEM grid, and a temperature equal to or higher than the melting point of liquid crystal (approximately 78°C) was applied. The powdered block copolymer melted and spread thinly on the grid to form a polymer layer. The polymer layer was then left to stand, allowing the block copolymers within the polymer layer to undergo self-assembly. A TEM image of the polymer layer was obtained.

[0101] Reference Figure 8A The bright lines in the image correspond to the polydimethylsiloxane block BLK1, and the dark lines correspond to the polyazobenzene block BLK2. The linewidths of both the polydimethylsiloxane and polyazobenzene blocks, measured by TEM, are approximately 9.02 nm (i.e., L0 / 2). This result is consistent with the above. Figure 4 The X-ray scattering analysis results matched.

[0102] A block copolymer and dichloroethane were mixed to prepare a block copolymer solution in which the block copolymer content was from about 0.5 wt% to about 2 wt%. The solution was spin-coated onto a substrate at about 3000 rpm to cast a polymer layer with a thickness of about 20 nm to about 70 nm. An AFM image of the polymer layer was obtained. (Refer to...) Figure 8B This confirms that the block copolymer has the same properties as the above. Figure 8A The image is similar to a horizontal columnar structure with long, extending lines.

[0103] The block copolymer prepared by the experimental example was mixed with dichloroethane as a neutral solvent to prepare 1 g of a block copolymer solution in which the content of the block copolymer was from about 0.5 wt% to about 2 wt%. The solution was irradiated with ultraviolet light to convert the block copolymer in the solution from a trans configuration to a cis configuration. Azobenzene, upon exposure to ultraviolet light, acquired a cis configuration, and the solution turned red. The solution was spin-coated onto a gold-coated substrate prepared for applying an electric field at about 3000 rpm to cast a polymer layer with a thickness of about 20 nm to about 70 nm. A voltage of about 25 V / μm was applied to the two electrodes of the substrate.

[0104] Figure 9 An image of a polymer layer obtained by self-assembling a block copolymer using an inventive concept is shown. (Refer to...) Figure 9 This confirms that the block copolymers in the polymer layer self-assemble along the direction of the electric field E.

[0105] Specifically, it can be confirmed that the polydimethylsiloxane block BLK1 and the polyazobenzene block BLK2 extend in a horizontal columnar shape along the direction of the electric field. When viewed from a plane, each of the columnar structures of the polydimethylsiloxane block BLK1 and the polyazobenzene block BLK2 can have a linear shape parallel to the direction of the electric field. The horizontal columnar structures in a linear shape reach a length of approximately 6 μm.

[0106] Figure 10 An image illustrating the self-healing process of the block copolymer demonstrating the inventive concept is shown. (Refer to...) Figure 10 Applying artificial damage to Figure 9 On a polymer layer, a damaged region (DFR) is formed. Ultraviolet light is irradiated onto the polymer layer to cause the block copolymer to transform into a cis configuration. With this transformation, the fluidity of the block copolymer can increase. If an electric field is applied to the polymer layer again, the block copolymer in the damaged region DFR can self-assemble again, and the damaged region DFR can self-heal.

[0107] Visible light is then irradiated onto the polymer layer to transform the block copolymer into a trans structure. This results in the formation of nanostructures with improved thermal stability (i.e., planar columnar structures comprising a first block (e.g., horizontal columnar structures) and planar columnar structures comprising a second block (e.g., horizontal columnar structures)). Each of the nanostructures may have a linewidth of approximately 9 nm and forms a line shape extending in the direction of the electric field.

[0108] Nanostructures are rigid and possess high thermal stability, and their durability to annealing and solvent processes in semiconductor fabrication can be high. Nanostructures are reusable. However, if damage forms within the nanostructure during repeated use, as described above... Figure 10 This can be explained by the self-healing process of nanostructures to repair damage.

[0109] The block copolymers and photolithography methods using the inventive concept overcome the shortcomings of photolithography using conventional block copolymers. The block copolymers according to the inventive concept can be used in next-generation photolithography processes and in the manufacture of polarizing plates.

[0110] Figures 11 to 15 It is a perspective view used to explain the photolithography method according to an embodiment of the inventive concept. Figures 11 to 15 A method for forming a target pattern using a photolithography method based on an inventive concept is shown.

[0111] Reference Figure 11An etch target layer TGL can be formed on a substrate SUB. In embodiments, the substrate SUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate SUB can be a semiconductor wafer. The etch target layer TGL can include a conductive material or an insulating material. The conductive material can include at least one of semiconductor materials (such as doped silicon, doped germanium, etc.), conductive metal nitrides (such as titanium nitride, tantalum nitride, etc.), metals (such as tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (such as tungsten silicide, cobalt silicide, titanium silicide, etc.). The insulating material can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0112] A hard mask layer HML can be formed on the etch target layer TGL. The hard mask layer HML can include a material that has etch selectivity relative to the etch target layer TGL. In embodiments, the hard mask layer HML can include a spin-coated hard mask (SOH) layer, a spin-coated carbon (SOC) layer, an amorphous carbon layer, a silicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a metal layer. The metal layer can include a titanium layer, a tungsten layer, a titanium oxide layer, or a titanium nitride layer. In another embodiment of the inventive concept, the hard mask layer HML can be a multilayer formed using different materials.

[0113] Reference Figure 12 A polymer layer PML can be formed on the hard mask layer HML. The polymer layer PML can include the above-mentioned references. Figure 3 The block copolymers according to embodiments of the inventive concept are explained. A polymer layer PML can be formed by spin-coating a solution containing the block copolymers of the inventive concept onto a hard mask layer HML. The block copolymers in the polymer layer PML can have a cis configuration by irradiating the solution or the spin-coated polymer layer PML with ultraviolet light (UVL).

[0114] Reference Figure 13 An electric field ELF can be applied along a first direction D1 on the polymer layer PML. Therefore, the first block BLK1 and the second block BLK2 of the block copolymer in the polymer layer PML can self-assemble along the electric field ELF to form a first nanostructure NS1 and a second nanostructure NS2, respectively. The first nanostructure NS1 may include the first block BLK1, and the second nanostructure NS2 may include the second block BLK2.

[0115] Each of the first nanostructure NS1 and the second nanostructure NS2 may have a horizontal columnar structure extending in a first direction D1. When viewed from a planar perspective, each of the first nanostructure NS1 and the second nanostructure NS2 may have a linear shape extending in the first direction D1. The first nanostructure NS1 and the second nanostructure NS2 may be arranged alternately along a second direction D2.

[0116] The adjacent second nanostructure NS2 can have a first pitch P1 in the second direction D2. The adjacent first nanostructure NS1 can also have a first pitch P1 in the second direction D2. The first pitch P1 can be about 16 nm to about 40 nm.

[0117] The second nanostructure NS2 may have a first linewidth LW1, and the first nanostructure NS1 may have a second linewidth LW2. The first linewidth LW1 and the second linewidth LW2 may be the same or different. Each of the first linewidth LW1 and the second linewidth LW2 may be from about 8 nm to about 20 nm.

[0118] As described above, since the block copolymer of the inventive concept has a volume fraction of about 0.45 to about 0.55 for the first block BLK1, it can be easily formed as... Figure 13 The columnar structure in the first nanostructure NS1 and the second nanostructure NS2.

[0119] If the block copolymer has a layered phase, then in order to form such as Figure 13 The first nanostructure NS1 and the second nanostructure NS2 in the process require Figure 2A The first layer of the first block BLK1 and the second layer of the second block BLK2 stand upright.

[0120] To vertically arrange the layered structure of the block copolymer, neutral layers must be formed above and below the polymer layer PML. Despite the formation of neutral layers, achieving a perfectly vertical arrangement of the block copolymer's layered structure is very difficult and introduces instability into the process.

[0121] In contrast, the block copolymers according to the inventive concept have a columnar phase, and the columnar structure is structurally more stable if laid horizontally. Therefore, it is possible to readily form structures such as... by applying only an electric field (ELF) without separate treatment. Figure 13 The first nanostructure NS1 and the second nanostructure NS2 are present in the inventive concept. Therefore, the photolithography process according to the inventive concept can exhibit excellent process efficiency.

[0122] After applying an electric field ELF, the second nanostructure NS2 can achieve a solid-state inverse structure by irradiating the first nanostructure NS1 and the second nanostructure NS2 with visible light VIL or by heating the first nanostructure NS1 and the second nanostructure NS2.

[0123] Reference Figure 14A selective etching process can be performed on the first nanostructure NS1 to selectively remove it. Then, only the second nanostructure NS2 can remain on the hard mask layer HML. The second nanostructure NS2 can have a first pitch P1. Each of the second nanostructures NS2 can have a first linewidth LW1 and a length LE in a first direction D1. In embodiments of the inventive concept, the ratio of the length LE of the second nanostructure NS2 to the first linewidth LW1 (LE / LW1) can be from about 300 to about 500.

[0124] and Figure 14 Refer to together Figure 15 The hard mask layer HML can be patterned using the second nanostructure NS2 as an etching mask to form a hard mask pattern HMP. The hard mask pattern HMP can be formed corresponding to the second nanostructure NS2. Therefore, the hard mask pattern HMP can have a second pitch P2 that is substantially the same as the first pitch P1. The hard mask pattern HMP can have a third linewidth LW3 that is substantially the same as the first linewidth LW1. After this, the retained second nanostructure NS2 can be selectively removed.

[0125] A hard mask pattern (HMP) can be used as an etch mask to pattern the etch target layer (TGL) to form a target pattern (TGP). A target pattern (TGP) can be formed corresponding to the hard mask pattern (HMP).

[0126] As a result, by using photolithography with block copolymers according to the inventive concept, the target pattern TGP can be formed with fine pitch through nanostructures. Compared with the minimum pitch of the pattern obtained by EUV lithography at approximately 45 nm, the photolithography according to the inventive concept can form a finer pattern.

[0127] Figures 16 to 18 This is a perspective view used to explain a self-healing method for nanostructures according to embodiments of the inventive concept. Figures 16 to 18 A method for self-healing and reuse is shown in the case where a damaged region DFR is formed on a first nanostructure NS1 and a second nanostructure NS2 of the inventive concept.

[0128] Reference Figure 16 In reference Figures 11 to 15 During the photolithography process described, damage regions (DFRs) may form on the first nanostructure NS1 and the second nanostructure NS2. Within the damage regions (DFRs), the first nanostructure NS1 and the second nanostructure NS2 are not properly formed, and the damage regions (DFRs) will exhibit significant process defects during the formation of the target pattern TGP.

[0129] By irradiating the first nanostructure NS1 and the second nanostructure NS2, in which the damaged region DFR is formed, the block copolymer in the damaged region DFR can be transformed into a fluid cis structure.

[0130] Reference Figure 17 An electric field ELF can be applied again to the first nanostructure NS1 and the second nanostructure NS2, in which the damaged region DFR is formed. Therefore, the block copolymer in the damaged region DFR can self-assemble again along the electric field ELF, and the first nanostructure NS1 and the second nanostructure NS2 can be formed from the damaged region DFR.

[0131] Reference Figure 18 A first nanostructure NS1 and a second nanostructure NS2 can be formed from the damaged region DFR. If the damaged region DFR is completely removed, visible light (VIL) can be applied to the first nanostructure NS1 and the second nanostructure NS2, or heat (HET) can be applied. Therefore, the second nanostructure NS2 can have a hard trans structure.

[0132] In this inventive concept, a damaged polymer layer formed on azobenzene can be regenerated into a nanostructure by utilizing the photoisomerization between the cis and trans structures. In other words, the polymer layer, including the block copolymer according to this inventive concept, can self-heal even if damaged. Therefore, the photolithography method of this inventive concept exhibits excellent process efficiency.

[0133] Figure 19 It is a plan view used to explain the semiconductor device according to the embodiment of the inventive concept. Figures 20A to 20D It is along Figure 19 Sectional views of lines A-A', B-B', C-C', and D-D'.

[0134] Reference Figure 19 and Figures 20A to 20D The logic unit (LC) can be disposed on the substrate (SUB). The substrate (SUB) can be a semiconductor substrate, including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. For example, the substrate (SUB) can be a silicon substrate.

[0135] Logic transistors that form logic circuits can be disposed on the logic cell LC. The logic cell LC may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be separated from each other in the first direction D1.

[0136] A first active pattern AP1 and a second active pattern AP2 can be defined by forming a trench TR on the substrate SUB. The first active pattern AP1 and the second active pattern AP2 can be disposed in the PMOSFET region PR and the NMOSFET region NR, respectively. The first active pattern AP1 and the second active pattern AP2 can extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 are portions of the substrate SUB and can be vertically extended portions.

[0137] The device isolation layer ST can fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2.

[0138] A first channel pattern CH1 can be disposed on a first active pattern AP1. A second channel pattern CH2 can be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be separated in the vertical direction (i.e., the third direction D3).

[0139] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Preferably, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon.

[0140] Multiple first source / drain patterns SD1 can be disposed on a first active pattern AP1. Multiple first recesses RS1 can be formed on the first active pattern AP1. The first source / drain patterns SD1 can be disposed in the first recesses RS1 respectively. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be disposed between a pair of first source / drain patterns SD1. In other words, the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 can connect a pair of first source / drain patterns SD1 to each other.

[0141] Multiple second source / drain patterns SD2 can be disposed on the second active pattern AP2. Multiple second recesses RS2 can be formed on the second active pattern AP2. The second source / drain patterns SD2 can be disposed in the second recesses RS2 respectively. The second source / drain patterns SD2 can be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be disposed between a pair of second source / drain patterns SD2. In other words, the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 can connect a pair of second source / drain patterns SD2 to each other.

[0142] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at a level substantially the same as the top surface of the third semiconductor pattern SP3. In another embodiment, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surface of the third semiconductor pattern SP3.

[0143] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor material of the substrate SUB. Therefore, a pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 located between them. The second source / drain pattern SD2 may comprise the same semiconductor material as the semiconductor material of the substrate SUB (e.g., Si).

[0144] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 on the first semiconductor layer SEL1. See again... Figure 20A The shape of the cross-section of the first source / drain pattern SD1 in the second direction D2 will be explained. The first semiconductor layer SEL1 may cover the inner wall of the first recess RS1. The first semiconductor layer SEL1 may have a U-shape along the contour of the first recess RS1. The second semiconductor layer SEL2 may fill the remaining area of ​​the first recess RS1 except for the first semiconductor layer SEL1. The volume of the second semiconductor layer SEL2 may be larger than the volume of the first semiconductor layer SEL1.

[0145] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include silicon germanium (SiGe). Specifically, the first semiconductor layer SEL1 may contain germanium (Ge) at a relatively low concentration. In another embodiment of the inventive concept, the first semiconductor layer SEL1 may contain only silicon (Si) and not germanium (Ge). The concentration of germanium (Ge) in the first semiconductor layer SEL1 may be from about 0 at% to about 10 at%.

[0146] The second semiconductor layer SEL2 may contain germanium (Ge) at a relatively high concentration. In embodiments, the concentration of germanium (Ge) in the second semiconductor layer SEL2 may be from about 30 at% to about 70 at%. The concentration of germanium (Ge) in the second semiconductor layer SEL2 may gradually increase in the third direction D3. For example, the second semiconductor layer SEL2 adjacent to the first semiconductor layer SEL1 has a germanium (Ge) concentration of about 40 at%, while the upper part of the second semiconductor layer SEL2 may have a germanium (Ge) concentration of about 60 at%.

[0147] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include impurities (e.g., boron) such that the first source / drain pattern SD1 can be p-type. The concentration (e.g., atomic percentage) of the impurities in the second semiconductor layer SEL2 can be greater than the concentration of the impurities in the first semiconductor layer SEL1.

[0148] A gate electrode GE can be provided, intersecting the first channel pattern CH1 and the second channel pattern CH2 and extending in the first direction D1. The gate electrode GE can be arranged in the second direction D2 according to the third pitch P3. Each of the gate electrodes GE can be vertically stacked with the first channel pattern CH1 and the second channel pattern CH2.

[0149] The gate electrode GE may include a first portion PO1 disposed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second portion PO2 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0150] Refer again Figure 20A The first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE on the PMOSFET region PR can have different widths. For example, the maximum width of the third portion PO3 in the second direction D2 can be greater than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the first portion PO1 in the second direction D2 can be greater than the maximum width of the third portion PO3 in the second direction D2.

[0151] Refer again Figure 20D The gate electrode GE can be disposed on the top surface TS, bottom surface BS, and two sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. In other words, the transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0152] Reference Figure 19 and Figures 20A to 20D A pair of gate spacers GS may be disposed on the two sidewalls of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer dielectric 110, which will be explained later. The gate spacers GS may include at least one of SiCN, SiCON, and SiN. In another embodiment, the gate spacers GS may include a multilayer composed of at least two of SiCN, SiCON, and SiN.

[0153] A gate overlay pattern GP may be formed on the gate electrode GE. The gate overlay pattern GP may extend along the gate electrode GE in a first direction D1. The gate overlay pattern GP may include a material having etch selectivity relative to the first interlayer dielectric 110 and the second interlayer dielectric 120, which will be explained later. Specifically, the gate overlay pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0154] A gate insulating layer GI can be disposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI can cover the top surface TS, bottom surface BS, and two sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI can also cover the top surface of the device isolation layer ST below the gate electrode GE (see...). Figure 20D ).

[0155] In embodiments of the inventive concept, the gate insulating layer GI may include a silicon oxide layer, a silicon nitride layer, and / or a high-k layer. The high-k layer may include a high-k material having a dielectric constant higher than that of silicon oxide. For example, the high-k material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0156] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. By controlling the thickness and composition of the first metal pattern, the desired threshold voltage of the transistor can be achieved. For example, the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be composed of the first metal pattern as the work function metal.

[0157] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), as well as nitrogen (N). Furthermore, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked active power metal layers.

[0158] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0159] Refer again Figure 20B The inner spacer IP can be disposed on the NMOSFET region NR. The inner spacer IP can be disposed between the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE and the second source / drain pattern SD2. The inner spacer IP can be in direct contact with the second source / drain pattern SD2. Each of the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE can be separated from the second source / drain pattern SD2 by the inner spacer IP.

[0160] A first interlayer dielectric 110 may be disposed on the substrate SUB. The first interlayer dielectric 110 may cover the gate spacer GS, the first source / drain pattern SD1, and the second source / drain pattern SD2. The top surface of the first interlayer dielectric 110 may be substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS. A second interlayer dielectric 120 covering the gate overlay pattern GP may be disposed on the first interlayer dielectric 110. In an embodiment, the first interlayer dielectric 110 and the second interlayer dielectric 120 may include a silicon oxide layer.

[0161] A pair of isolation structures DB facing each other in the second direction D2 can be positioned on both sides of the logic cell LC. For example, the isolation structure DB can be positioned on the boundary of the logic cell LC. The isolation structure DB can extend parallel to the gate electrode GE in the first direction D1. The pitch between the isolation structure DB and the adjacent gate electrode GE can be the same as the third pitch P3.

[0162] The isolation structure DB can pass through the first interlayer dielectric 110 and the second interlayer dielectric 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The isolation structure DB can pass through the first channel pattern CH1 and the second channel pattern CH2. The isolation structure DB can separate the PMOSFET region PR and NMOSFET region NR of the logic cell LC from the PMOSFET region and NMOSFET region of another cell.

[0163] Active contacts AC can be provided that pass through the first interlayer dielectric 110 and the second interlayer dielectric 120 and are electrically connected to the corresponding source / drain patterns in the first source / drain pattern SD1 and the second source / drain pattern SD2. A pair of active contacts AC can be respectively provided on both sides of the gate electrode GE. When viewed from a planar perspective, the active contacts AC can have a strip shape extending in the first direction D1.

[0164] The active contact AC can be a self-aligned contact. In other words, the active contact AC can be formed by utilizing the self-alignment of the gate cover pattern GP and the gate spacer GS. For example, the active contact AC can cover at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC can cover a portion of the top surface of the gate cover pattern GP.

[0165] A silicide pattern SC may be disposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to the source / drain pattern SD1 or SD2 via the silicide pattern SC. The silicide pattern SC may include a metal silicide, and may include at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0166] A gate contact GC can be provided that passes through the second interlayer dielectric 120 and the gate overlay pattern GP and is electrically connected to the gate electrode GE. For example, refer to Figure 20B The upper portion of each of the active contacts AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. This prevents process defects such as short circuits caused by contact between the gate contact GC and the adjacent active contacts AC.

[0167] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The blocking pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The blocking pattern BM may include a metal layer / metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0168] In the third interlayer dielectric 130, a first metal layer M1 may be provided. The first metal layer M1 may include a first power wiring MPR1, a second power wiring MPR2, a first lower wiring MI1 to a fifth lower wiring MI5, and a lower via VI1. The lower via VI1 may be provided below the first power wiring MPR1, the second power wiring MPR2, and the first lower wiring MI1 to the fifth lower wiring MI5.

[0169] The first power wiring MPR1 and the second power wiring MPR2 can extend parallel to each other in the second direction D2, while crossing the logic cell LC. The drain voltage VDD and the source voltage VSS can be applied to the first power wiring MPR1 and the second power wiring MPR2, respectively.

[0170] Reference Figure 19 A first cell boundary CB1 extending in the second direction D2 can be defined within a logic cell LC. On the opposite side of the first cell boundary CB1, a second cell boundary CB2 extending in the second direction D2 can be defined. A first power trace MPR1 for applying a drain voltage VDD can be provided on the first cell boundary CB1. In other words, the first power trace MPR1 for applying the drain voltage VDD can extend along the first cell boundary CB1 in the second direction D2. A second power trace MPR2 for applying a source voltage VSS (i.e., ground voltage) can be provided on the second cell boundary CB2. In other words, the second power trace MPR2 for applying the source voltage VSS can extend along the second cell boundary CB2 in the second direction D2.

[0171] The first lower wiring MI1 to the fifth lower wiring MI5 can be located between the first power wiring MPR1 and the second power wiring MPR2. Specifically, the first wiring trace MTR1 to the fifth wiring trace MTR5 can be defined between the first power wiring MPR1 and the second power wiring MPR2. The first wiring trace MTR1 to the fifth wiring trace MTR5 can extend parallel to each other in the second direction D2. The first lower wiring MI1 to the fifth lower wiring MI5 can be arranged along the first direction D1 according to the fourth pitch P4. For example, the fourth pitch P4 can be smaller than the third pitch P3.

[0172] At least one first down-running MI1 can be set on the first routing trace MTR1, at least one second down-running MI2 can be set on the second routing trace MTR2, at least one third down-running MI3 can be set on the third routing trace MTR3, at least one fourth down-running MI4 can be set on the fourth routing trace MTR4, and at least one fifth down-running MI5 can be set on the fifth routing trace MTR5.

[0173] The first lower wiring MI1 to the fifth lower wiring MI5 can extend parallel to each other along the first wiring trace MTR1 to the fifth wiring trace MTR5 respectively in the second direction D2. When viewed in a plane, each of the first lower wiring MI1 to the fifth lower wiring MI5 can have a line shape or a strip shape.

[0174] Each of the first power cabling MPR1 and the second power cabling MPR2 may have a fourth line width LW4. Each of the first lower cabling MI1 to the fifth lower cabling MI5 may have a fifth line width LW5. The fifth line width LW5 may be smaller than the fourth line width LW4 (see...). Figure 20C For example, the fifth linewidth LW5 can be less than approximately 12 nm. The fourth linewidth LW4 can be greater than approximately 12 nm.

[0175] The lower via VI1 can be disposed between the first power wiring MPR1 and the second power wiring MPR2 and the active contact AC. The lower via VI1 can be disposed between the first lower wiring MI1 to the fifth lower wiring MI5 and the active contact AC and the gate contact GC.

[0176] For example, the first power wiring MPR1, the second power wiring MPR2, and the first lower wiring MI1 to the fifth lower wiring MI5 may include metals selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0177] The wirings MPR1, MPR2, and MI1 to MI5 of the first metal layer M1, and the underlying via VI1, can be formed by a separate process. According to embodiments of the inventive concept, the wirings MPR1, MPR2, and MI1 to MI5 of the first metal layer M1 can be formed using reference... Figures 11 to 15 The photolithography method explained is used to form it. For example, Figure 15 The target pattern TGP can be from the first down-wiring MI1 to the fifth down-wiring MI5.

[0178] In the fourth interlayer dielectric 140, a second metal layer M2 may be provided. The second metal layer M2 may include upper wirings M2_I. Each of the upper wirings M2_I may have a line shape or a strip shape extending in the first direction D1. In other words, the upper wirings M2_I may extend parallel to each other in the first direction D1.

[0179] The second metal layer M2 may also include an upper via VI2. The upper via VI2 may be located below the upper wiring M2_I. The upper via VI2 may be located between the wirings MPR1, MPR2 and MI1 to MI5 of the first metal layer M1 and the upper wiring M2_I.

[0180] The upper wiring M2_I may include a metal selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). In embodiments of the inventive concept, the upper wiring M2_I of the second metal layer M2 may also be constructed using a reference. Figures 11 to 15 The photolithography method explained is used to form it. For example, Figure 15 The target pattern TGP can be the top wiring M2_I.

[0181] In embodiments of the inventive concept, the gate electrode GE explained above can also be used by referring to Figures 11 to 15 The photolithography method explained is used to form it. For example, Figure 15 The target pattern TGP can be a gate electrode GE or a silicon pattern (e.g., a polysilicon pattern) used to replace the gate electrode GE.

[0182] In embodiments of the inventive concept, metal layers stacked on the fourth interlayer dielectric 140 may be additionally provided. Each of the stacked metal layers may include wiring. The wiring in the stacked metal layers may also be formed using the photolithography method of the inventive concept.

[0183] Figure 21 This is a perspective view of a display device according to an embodiment of the inventive concept. Figure 22 It is along Figure 21 A sectional view of line A-A' in the diagram.

[0184] Reference Figure 21 and Figure 22The display device may include a first display substrate DPS1, a second display substrate DPS2, and a liquid crystal layer LCL. The first display substrate DPS1 may include a first array layer ARL1 and a first polarizing layer PLL1 disposed on the first substrate SUB1. The first array layer ARL1 may be disposed on a first surface of the first substrate SUB1, and the first polarizing layer PLL1 may be disposed on a second surface of the first substrate SUB1. The first surface of the first substrate SUB1 may be adjacent to the liquid crystal layer LCL. The first display substrate DPS1 may also include a first protective layer PTL1 disposed on the first polarizing layer PLL1. In an embodiment, the first substrate SUB1 may be a glass substrate.

[0185] The first polarizing layer PLL1 may include a first lattice pattern GPT1. A first separation portion SEP1 may be provided between adjacent first lattice patterns GPT1. The first separation portion SEP1 may partially expose the second surface of the first substrate SUB1. The first lattice pattern GPT1 may have a line shape extending parallel to each other in a first direction D1. The first lattice pattern GPT1 may be arranged along a second direction D2.

[0186] In an embodiment, the first grid pattern GPT1 may have a stripe shape. The first grid pattern GPT1 may reflect and / or absorb a portion of the light incident on the first polarizing layer PLL1. For example, the first grid pattern GPT1 may include aluminum, silver, or gold with high reflectivity. Light incident on the first polarizing layer PLL1 may pass through the first separation portion SEP1 and be provided to the liquid crystal layer LCL. In other words, the first polarizing layer PLL1 can polarize the incident light.

[0187] The first array layer ARL1 may include multiple pixels. The first array layer ARL1 may include a switching element TFT and a pixel electrode PXEL disposed to each pixel. The first array layer ARL1 may also include a passivation layer PSL covering the switching element TFT.

[0188] The switching element TFT may include a gate electrode GE, a gate insulating layer GI on the gate electrode GE, an active layer ACL on the gate insulating layer GI, and a source electrode SCEL and a drain electrode DEL on the active layer ACL. The active layer ACL may include a semiconductor layer SEL and an ohmic contact layer OCL between each of the source electrode SCEL and the drain electrode DEL and the semiconductor layer SEL. The pixel electrode PXEL may be disposed on the passivation layer PSL and may be connected to the drain electrode DEL.

[0189] The second display substrate DPS2 may include a second array layer ARL2 and a second polarizing layer PLL2 disposed on a second substrate SUB2. The second array layer ARL2 may be disposed on a first surface of the second substrate SUB2. The second polarizing layer PLL2 may be disposed on a second surface of the second substrate SUB2. The first surface of the second substrate SUB2 may be adjacent to the liquid crystal layer LCL. The second display substrate DPS2 may also include a second protective layer PTL2 disposed on the second polarizing layer PLL2.

[0190] The second polarizing layer PLL2 may include a second grid pattern GPT2. A second separation portion SEP2 may be provided between adjacent second grid patterns GPT2. The second grid pattern GPT2 may have a line shape extending parallel to each other in a second direction D2. The second grid pattern GPT2 may be arranged along a first direction D1.

[0191] In an embodiment, the second grid pattern GPT2 may have a stripe shape. The second grid pattern GPT2 may reflect and / or absorb a portion of the light passing through the liquid crystal layer LCL. For example, the second grid pattern GPT2 may include aluminum, silver, or platinum, which have high reflectivity. The second polarizing layer PLL2 may polarize the light passing through the liquid crystal layer LCL.

[0192] The second array layer ARL2 may include a masking pattern SHL, a color filter CLF, a coating layer CTL, and a common electrode CMEL. The masking pattern SHL can divide or define pixels. The color filter CLF can be set in each pixel.

[0193] According to an embodiment of the inventive concept, the first grid pattern GPT1 can be obtained by using a reference. Figures 11 to 15 The photolithography method explained is used to form it. For example, Figure 15 The target pattern TGP can be the first grid pattern GPT1.

[0194] The second grid pattern GPT2 according to an embodiment of the inventive concept can be obtained by using a reference. Figures 11 to 15 The photolithography method explained is used to form it. For example, Figure 15 The target pattern TGP can be the second grid pattern GPT2.

[0195] The block copolymers according to the inventive concept can achieve high Flory-Huggins interaction parameters by bonding first and second blocks with different properties via an ATRP synthesis method. The block copolymers have a specific volume fraction of first or second blocks and can have a columnar phase. The block copolymers are capable of directional self-assembly and self-healing by utilizing the polarization and photosensitivity properties of azobenzene.

[0196] According to the photolithography method based on the inventive concept, block copolymers can be used to form directional nanostructures. Furthermore, even if damaged regions are formed within the nanostructure, these regions can self-heal and transform back into nanostructures. As a result, the photolithography of the inventive concept can form finer patterns compared to EUV lithography and offers superior process efficiency.

[0197] Although embodiments of the invention have been described, it is understood that the invention should not be limited to these embodiments, but rather various changes and modifications can be made by those skilled in the art within the spirit and scope of the claimed invention.

Claims

1. A block copolymer for photolithography, the block copolymer comprising: The first block includes the first repeating unit of Equation 1 below; as well as The second block includes the second repeating unit of Equation 2 below: [Formula 1] ， R1 and R2 are each independently hydrogen or straight-chain or branched C1 to C10 alkyl groups, and "x" is an integer between 60 and 80. [Equation 2] ， R3 is a straight-chain or branched C1 to C10 alkylene group. "y" is an integer between 15 and 25, and The block copolymer has a columnar phase.

2. The block copolymer for photolithography according to claim 1, wherein, The ratio of "y" to "x" is 0.2 to 0.

3.

3. The block copolymer for photolithography according to claim 1, wherein, The volume ratio of the first block to the volume of the block copolymer is 0.45 to 0.

55.

4. The block copolymer for photolithography according to claim 1, wherein, R1 and R2 are methyl groups.

5. The block copolymer for photolithography according to claim 1, wherein, The linewidth of the columnar structure of the second block is 8 nm to 20 nm.

6. A method for photolithography, the method comprising the following steps: A polymer layer comprising block copolymers is formed on a substrate; An electric field is applied to the polymer layer to form a first nanostructure and a second nanostructure, the first nanostructure and the second nanostructure extending in a first direction and parallel to each other; as well as Selectively remove the first nanostructure. Block copolymers include: The first block comprises repeating units of polymerized siloxane; and The second block comprises repeating units of polymerized azophenoxyalkanol acrylate. The azophenoxyalkanol comprises a straight-chain or branched alkylene group with 1 to 10 carbon atoms. The number of repeating units in the polymerized siloxane is 60 to 80. The number of repeating units in the polymerized azophenoxyalkanol acrylate is between 15 and 25. The first nanostructure includes a first block, and The second nanostructure includes a second block.

7. The method according to claim 6, further comprising: Visible light is irradiated onto the first and second nanostructures during or after the application of an electric field.

8. The method according to claim 6, wherein, The second nanostructure has a columnar structure formed using a second block.

9. The method according to claim 8, wherein, The columnar structure extends horizontally in the first direction.

10. The method according to claim 6, wherein, The steps for forming the polymer layer include spin-coating a solution containing a block copolymer onto a substrate.

11. The method according to claim 6, further comprising: Before or during the formation of the polymer layer, the block copolymer is irradiated with ultraviolet light.

12. The method according to claim 6, wherein, The linewidth of each nanostructure in the first and second nanostructures ranges from 8 nm to 20 nm.

13. The method according to claim 6, wherein, The ratio of the length of the second nanostructure in the first direction to the linewidth of the second nanostructure is 300 to 500.

14. The method according to claim 6, further comprising: Irradiate the damaged area of ​​the polymer layer with ultraviolet light; as well as An electric field is applied again to the damaged region to form at least one nanostructure extending in the first direction.

15. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming transistors on a substrate; as well as Wiring is formed on the transistor, and the wiring extends in a first direction. The steps involved in forming the wiring include: Forming an etch target layer on the transistor; A polymer layer comprising block copolymers is formed on the etched target layer; An electric field is applied to the polymer layer to form a first nanostructure and a second nanostructure, the first nanostructure and the second nanostructure extending in a first direction and parallel to each other; Selectively removing the first nanostructure; and The target layer for etching is patterned using a second nanostructure as an etching mask. The block copolymer comprises: a first block, a polymer comprising a silicon-oxygen backbone; and a second block, comprising repeating units containing azobenzene, wherein the repeating units containing azobenzene are represented by the following Formula 2. [Equation 2] ， In Formula 2, R3 is a straight-chain or branched C1 to C10 alkylene group, and "y" is an integer from 15 to 25. The volume ratio of the first block to the block copolymer is between 0.45 and 0.

55. Each of the first nanostructures in the first nanostructure includes a first block, and Each of the second nanostructures in the second nanostructure includes a second block.

16. The method of manufacturing a semiconductor device according to claim 15, wherein, The first nanostructure and the second nanostructure are arranged alternately in a second direction that intersects the first direction.

17. The method of manufacturing a semiconductor device according to claim 15, wherein, The second nanostructure has a columnar structure formed using a second block.

18. The method of manufacturing a semiconductor device according to claim 15, wherein, The linewidth of each second nanostructure in the second nanostructure is 8 nm to 20 nm, and The width of each trace in the wiring is 8nm to 20nm.

19. The method of manufacturing a semiconductor device according to claim 15, wherein, The ratio of the length of the second nanostructure in the first direction to the linewidth of the second nanostructure is 300 to 500.

20. The method for manufacturing a semiconductor device according to claim 15, in, The degree of aggregation of the first block is 60 to 80, and The degree of polymerization of the second block is 15 to 25.

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