A radar receiver jamming signal detection method

Abstract

The present application belongs to the technical field of radar receiver, and particularly relates to a radar receiver interference signal detection method, wherein the radar receiver comprises a narrowband receiver, a wideband imaging channel, an FPGA and an ADC; a coupler or an equivalent signal distribution circuit is used to simultaneously output radar echo signals received by the radar receiver to the narrowband receiver and the wideband imaging channel, and the narrowband receiver and the wideband imaging channel complete signal processing in the corresponding bandwidth of the echo signals; the present application can realize detection of interference signals in the working bandwidth without changing the existing radar hardware architecture.

Description

Technical Field

[0001] This invention belongs to the field of radar receiver technology, and specifically relates to a method for detecting interference signals in a radar receiver. Background Technology

[0002] The radar receiver is the physical channel for receiving radar echo signals, and its main functions are to amplify, frequency convert, and filter the radar echo signals.

[0003] Radar receivers use wideband filters at the radio frequency (RF) input of the radar signal to simplify circuit design and reduce size, while using narrowband filters at the intermediate frequency (IF) input to achieve the required interference suppression capability. The radar analyzes the IF signal output from the radar receiver to identify the presence of interference signals. When the interference signal is located within the RF filter band and outside the IF filter band, the radar will not be able to detect the interference due to the filter's influence, but the interference signal will still degrade radar performance due to its effect on the RF circuitry. Summary of the Invention

[0004] In view of this, the present invention provides a method for detecting interference signals in a radar receiver, which can detect interference signals that enter the receiver's radio frequency filter band but are located outside the intermediate frequency filter, thereby improving the radar's performance in complex electromagnetic environments.

[0005] To achieve the above-mentioned technical objectives, the specific technical solution adopted by the present invention is as follows:

[0006] A method for detecting interference signals in a radar receiver, wherein the radar receiver includes a narrowband receiver, a broadband imaging channel, an FPGA, and an ADC;

[0007] The interference signal detection method includes the following steps:

[0008] 1) The radar echo signal received by the radar receiver is simultaneously output to the narrowband receiver and the broadband imaging channel using a coupler or equivalent signal distribution circuit. The narrowband receiver and the broadband imaging channel complete the signal processing within the corresponding bandwidth of the echo signal.

[0009] 2) The analog signals output by the narrowband receiver and the broadband imaging channel are digitized using an ADC and then processed and transmitted to the FPGA;

[0010] 3) The FPGA performs digital down-conversion processing on the analog signal to obtain the baseband IQ signal;

[0011] 4) The FPGA performs the detection and parameter measurement of the baseband IQ signal;

[0012] 5) The FPGA sends the interference signal and parameters to the radar's processing unit via the data bus.

[0013] Furthermore, the radar receiver also includes a FLASH memory, which communicates with the FPGA and is used to store the operating logic and threshold parameters for implementing the interference signal detection method.

[0014] Furthermore, in the process of achieving 1), the radar echo signal enters both the narrowband receiver and the broadband imaging channel simultaneously after passing through the coupler or equivalent signal distribution circuit; at this time, the narrowband receiver is set to normal working state, and the broadband imaging channel is set to the corresponding working state according to the interference signal monitoring bandwidth requirements.

[0015] Furthermore, the operating bandwidth of the broadband imaging channel is the same as the bandwidth of the interference signal, and the receiving gain of the broadband imaging channel is set according to the sensitivity and dynamic range required for monitoring the interference signal, so that the receiving gain can meet the functional requirements of monitoring.

[0016] Furthermore, in step 2), the ADC includes a narrowband ADC and a wideband ADC, which respectively perform wideband digitization and narrowband digitization of the radar callback signal.

[0017] Furthermore, in step 3), when the FPGA completes the digital downconversion and interference monitoring of the narrowband receiving channel, the FPGA is used to complete the digital downconversion, noise power calculation, reading the noise threshold parameter according to the gain control and signal bandwidth parameters, and completing the saturation interference decision after comparing the noise power with the threshold.

[0018] Furthermore, in step 3), when the FPGA completes the digital down-conversion and interference detection of the broadband imaging channel, the FPGA is used to complete the channelized reception and detection of the signal, the parameter measurement of the time-domain and frequency-domain characteristics of the signal, and the output of the time-domain and frequency-domain characteristic parameters of the interference signal.

[0019] Furthermore, the time-domain characteristics of the signal include the pulse period and pulse width of the interference signal; the frequency-domain characteristics include the frequency and power of the interference signal.

[0020] Furthermore, in step 4), the FPGA is also used to map the interference signal. When mapping the interference signal, the FPGA maps the interference signal to the radar signal processing plane according to the current operating parameters of the radar.

[0021] Then, the time-domain and frequency-domain interference signal parameters are calculated after mapping.

[0022] Finally, the calculated interference signal parameters and radar echo signal data are packaged together and sent to the signal processing unit via the data bus.

[0023] Furthermore, the input terminal of the narrowband receiver is connected to the output terminal of the coupler; the input terminal of the coupler receives radar echoes, and the output terminal is simultaneously connected to the input terminal of the narrowband receiver and the input terminal of the broadband imaging channel.

[0024] The output of the narrowband receiver is connected to the input of the narrowband ADC; the output of the narrowband ADC is connected to the FPGA; the FPGA is connected to the data bus of the radar receiver carrier.

[0025] The output of the broadband imaging channel is connected to the input of the broadband ADC; the output of the broadband ADC is connected to the FPGA.

[0026] The FPGA is externally connected to FLASH.

[0027] By adopting the above technical solution, the present invention can bring the following beneficial effects:

[0028] This invention can detect interference signals within the operating bandwidth without changing the existing radar hardware architecture. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a radar receiver in a specific embodiment of the present invention. Detailed Implementation

[0031] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0032] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0033] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0034] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0036] In one embodiment of the present invention, a method for detecting interference signals in a radar receiver is proposed, such as... Figure 1 As shown, the radar receiver includes a narrowband receiver, a wideband imaging channel, an FPGA, and an ADC;

[0037] The interference signal detection method includes the following steps:

[0038] 1) Use a coupler or equivalent signal distribution circuit to simultaneously output the radar echo signal received by the radar receiver to the narrowband receiver and the broadband imaging channel. The narrowband receiver and the broadband imaging channel complete the signal processing within the corresponding bandwidth of the echo signal.

[0039] 2) The analog signals output by the narrowband receiver and the broadband imaging channel are digitized using an ADC and then processed and transmitted to the FPGA;

[0040] 3) The FPGA performs digital down-conversion processing on the analog signal to obtain the baseband IQ signal;

[0041] 4) The FPGA performs the detection and parameter measurement of the baseband IQ signal;

[0042] 5) The FPGA sends the interference signal and parameters to the radar processing unit via the data bus.

[0043] The radar receiver also includes FLASH, which communicates with the FPGA to store the operating logic and threshold parameters for implementing the interference signal detection method.

[0044] In this embodiment, during the implementation of 1), the radar echo signal enters both the narrowband receiver and the broadband imaging channel simultaneously after passing through the coupler or equivalent signal distribution circuit. At this time, the narrowband receiver is set to normal operating state, and the broadband imaging channel is set to the corresponding operating state according to the interference signal monitoring bandwidth requirements.

[0045] In this embodiment, the operating bandwidth of the broadband imaging channel is the same as the bandwidth of the interference signal. The receiving gain of the broadband imaging channel is set according to the sensitivity and dynamic range required for monitoring the interference signal, so that the receiving gain can meet the functional requirements of the monitoring.

[0046] In this embodiment, in 2), the ADC includes a narrowband ADC and a wideband ADC, which respectively perform wideband digitization and narrowband digitization of the radar callback signal.

[0047] In this embodiment, in step 3), when the FPGA completes the digital downconversion and interference monitoring of the narrowband receiving channel, the FPGA is used to complete the digital downconversion, noise power calculation, reading the noise threshold parameter according to the gain control and signal bandwidth parameters, and completing the saturation interference decision after comparing the noise power with the threshold.

[0048] In this embodiment, when the FPGA completes the digital down-conversion and interference detection of the broadband imaging channel in step 3), the FPGA is used to complete the parameter measurement of the signal channelization reception and signal detection, the time domain characteristics and frequency domain characteristics of the signal, and the time domain characteristics and frequency domain characteristics parameters of the output interference signal.

[0049] In this embodiment, the time-domain characteristics of the signal include the pulse period and pulse width of the interference signal; the frequency-domain characteristics include the frequency and power of the interference signal.

[0050] In this embodiment, in step 4), the FPGA is also used to map the interference signal. When mapping the interference signal, the FPGA maps the interference signal to the radar signal processing plane according to the current operating parameters of the radar.

[0051] Then, the time-domain and frequency-domain interference signal parameters are calculated after mapping.

[0052] Finally, the calculated interference signal parameters and radar echo signal data are packaged together and sent to the signal processing unit via the data bus.

[0053] In this embodiment, as Figure 1As shown, the input of the narrowband receiver is connected to the output of the coupler; the input of the coupler receives radar echoes, and the output is connected to both the input of the narrowband receiver and the input of the broadband imaging channel.

[0054] The output of the narrowband receiver is connected to the input of the narrowband ADC; the output of the narrowband ADC is connected to the FPGA; the FPGA is connected to the data bus of the radar receiver's carrier.

[0055] The output of the broadband imaging channel is connected to the input of the broadband ADC; the output of the broadband ADC is connected to the FPGA.

[0056] The FPGA has an external FLASH memory.

[0057] This embodiment analyzes the noise power in the intermediate frequency band output of the radar narrowband receiver to determine interference, and then uses the radar's broadband imaging channel to analyze the characteristics of the interference signal, ultimately detecting the interference signal. Specifically:

[0058] 1) Use a coupler to simultaneously output the radar echo signal to both the narrowband receiver and the broadband imaging channel to complete signal processing within the corresponding bandwidth.

[0059] 2) The two output signals are digitized using analog-to-digital converters (ADCs) and sent to a field-programmable array (FPGA).

[0060] 3) The FPGA completes the digital down-conversion processing of the corresponding signal.

[0061] 4) Interference signal detection and parameter measurement are performed within the FPGA.

[0062] 5) The FPGA sends the interference signals and parameters to the processing unit via the data bus.

[0063] The radar receiver in this embodiment consists of a coupler, a narrowband receiver, a wideband imaging channel, a FLASH memory, an FPGA, and an ADC, and their connections are as follows: Figure 1 As shown in the diagram. The coupler is used for signal distribution between the narrowband receiver and the broadband imaging channel. The narrowband receiver and the broadband imaging channel complete echo signal processing within their respective bandwidths. The ADC digitizes the receiver output signal. The FLASH memory is used to store the program and threshold parameters. The FPGA performs digital down-conversion, interference detection, and data cross-linking with external systems. Figure 1 The coupler in the circuit can also be implemented using a power divider or other circuits capable of simultaneously outputting radio frequency signals. The working principle is as follows:

[0064] 1. After power-on, the FPGA loads the local program from the FLASH and obtains the threshold parameters;

[0065] The local program includes a digital downconversion processing program, an interference signal detection and measurement program, and a noise power monitoring program.

[0066] 2. The radar echo signal passes through a coupler (or equivalent signal distribution circuit) and enters the narrowband receiver and the broadband imaging channel respectively.

[0067] a. The narrowband receiver is set to normal operating status.

[0068] b. The broadband imaging channel is set to the corresponding working status according to the bandwidth requirements for monitoring interference signals.

[0069] c. Narrowband ADC and wideband ADC respectively complete the digitization of the signal.

[0070] 3FPGAs complete the digital downconversion and interference monitoring of the narrowband receiving channel;

[0071] a. FPGA performs digital downconversion.

[0072] b. The FPGA performs noise power calculation.

[0073] c. The FPGA reads the noise threshold parameters based on parameters such as gain control and signal bandwidth.

[0074] d. Compare the noise power with the threshold to complete the saturation interference decision.

[0075] 4 FPGAs complete digital down-conversion and interference detection for broadband imaging channels;

[0076] a. The FPGA completes the channelized reception of signals.

[0077] b. The FPGA performs signal detection.

[0078] c. The FPGA performs measurements of the signal's time-domain characteristics (pulse period, pulse bandwidth) and frequency-domain characteristics (frequency, power).

[0079] d. Time-domain and frequency-domain characteristics of the FPGA output interference signal.

[0080] 5. The FPGA completes the interference signal mapping;

[0081] a. The FPGA maps the interference signal to the radar signal processing plane according to the current radar operating parameters;

[0082] b. Calculate the time-domain and frequency-domain interference signal parameters after the FPGA completes the mapping.

[0083] The FPGA packages the calculated interference signal parameters and radar echo signal data together and sends them to the signal processing unit via the data bus.

[0084] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for detecting interference signals in a radar receiver, characterized in that, The radar receiver includes a narrowband receiver, a wideband imaging channel, an FPGA, and an ADC; The interference signal detection method includes the following steps: 1) The radar echo signal received by the radar receiver is simultaneously output to the narrowband receiver and the broadband imaging channel using a coupler or equivalent signal distribution circuit. The narrowband receiver and the broadband imaging channel complete the signal processing within the corresponding bandwidth of the echo signal. 2) The analog signals output by the narrowband receiver and the broadband imaging channel are digitized using an ADC and then processed and transmitted to the FPGA; 3) The FPGA performs digital down-conversion processing on the analog signal to obtain the baseband IQ signal; 4) The FPGA performs the detection and parameter measurement of the baseband IQ signal; 5) The FPGA sends the interference signal and parameters to the radar's processing unit via the data bus.

2. The interference signal detection method according to claim 1, characterized in that, The radar receiver also includes a FLASH memory, which communicates with the FPGA and is used to store the operating logic and threshold parameters for implementing the interference signal detection method.

3. The interference signal detection method according to claim 2, characterized in that, In the process of achieving 1), the radar echo signal enters the narrowband receiver and the broadband imaging channel simultaneously after passing through the coupler or equivalent signal distribution circuit; at this time, the narrowband receiver is set to normal working state, and the broadband imaging channel is set to the corresponding working state according to the interference signal monitoring bandwidth requirements.

4. The interference signal detection method according to claim 3, characterized in that, The operating bandwidth of the broadband imaging channel is the same as the bandwidth of the interference signal. The receiving gain of the broadband imaging channel is set according to the sensitivity and dynamic range required for monitoring the interference signal, so that the receiving gain can meet the functional requirements of monitoring.

5. The interference signal detection method according to claim 4, characterized in that, In step 2), the ADC includes a narrowband ADC and a wideband ADC, which respectively perform wideband digitization and narrowband digitization of the radar echo signal.

6. The interference signal detection method according to claim 5, characterized in that, In step 3), when the FPGA completes the digital downconversion and interference monitoring of the narrowband receiving channel, the FPGA is used to complete the digital downconversion, noise power calculation, reading the noise threshold parameter according to the gain control and signal bandwidth parameters, and completing the saturation interference decision after comparing the noise power with the threshold.

7. The interference signal detection method according to claim 6, characterized in that, When the FPGA completes the digital down-conversion and interference detection of the broadband imaging channel in step 3), the FPGA is used to complete the channelized reception and detection of the signal, the parameter measurement of the time-domain and frequency-domain characteristics of the signal, and the output of the time-domain and frequency-domain characteristic parameters of the interference signal.

8. The interference signal detection method according to claim 7, characterized in that, The time-domain characteristics of the signal include the pulse period and pulse width of the interference signal; the frequency-domain characteristics include the frequency and power of the interference signal.

9. The interference signal detection method according to claim 8, characterized in that, In step 4), the FPGA is also used to map the interference signal. When mapping the interference signal, the FPGA maps the interference signal to the radar signal processing plane according to the current operating parameters of the radar. Then, the time-domain and frequency-domain interference signal parameters are calculated after mapping. Finally, the calculated interference signal parameters and radar echo signal data are packaged together and sent to the signal processing unit via the data bus.

10. The interference signal detection method according to claim 1, characterized in that, The input of the narrowband receiver is connected to the output of the coupler; the input of the coupler receives radar echoes, and the output is connected to both the input of the narrowband receiver and the input of the broadband imaging channel. The output of the narrowband receiver is connected to the input of the narrowband ADC; the output of the narrowband ADC is connected to the FPGA; the FPGA is connected to the data bus of the radar receiver carrier. The output of the broadband imaging channel is connected to the input of the broadband ADC; the output of the broadband ADC is connected to the FPGA. The FPGA is externally connected to FLASH.

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