Internally packaged optoelectronic module

Abstract

This disclosure provides an in-package optoelectronic module. The in-package multichannel optical engine is packaged into four or more sub-components for use in an optoelectronic module. Each sub-component is assembled with at least four laser chips, one or more driver chips, and one or more transimpedance amplifier (TIA) chips, which are flip-chip mounted on a silicon photonic inserter and coupled to optical interface blocks and electrical interface blocks on a sub-module substrate. The in-package multichannel optical engine also includes a first frame retainer and a second frame retainer, the first frame retainer holding the four or more sub-components, and the second frame retainer being configured to hold the first frame retainer together with the four or more sub-components. The in-package multichannel optical engine also includes an insert plate inserted between the sub-module substrate and a module substrate and compressed between a backplate member attached to the bottom side of the module substrate and a top plate member configured as a heat sink with multiple heat sink structures.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese invention patent application No. 202110626668.7, filed on June 4, 2021, entitled "Internal Encapsulation Optoelectronic Module". Technical Field

[0003] This invention relates to optical communication technology. More specifically, this invention provides an in-package optoelectronic module and an optoelectronic system having the in-package optoelectronic module, wherein the in-package optoelectronic module is assembled with multiple sub-modules, each sub-module being configured to include a multi-channel optical engine containing an optoelectronic transceiver based on a silicon photonics platform. Background Technology

[0004] With the rapid advancement of science and technology, the processing speed and capacity of computers have increased accordingly. Communication using traditional cables is limited by their bandwidth and transmission speed, and the massive amounts of information required in modern life cause traditional communication transmissions to become overloaded. To meet these demands, fiber optic transmission systems have gradually replaced traditional communication transmission systems. Fiber optic communication has been chosen for systems requiring higher bandwidth and longer distances that cables cannot provide. The current electronics industry is conducting research on optical transmission, and even for short-distance communication, optical transmission will become the mainstream in the future. Optical communication is a technology in which light waves are used as signal carriers and transmitted between two nodes via optical fibers. An optical communication system includes an optical transmitter and an optical receiver. Through an optical transceiver, the received optical signal can be converted into an electrical signal that can be processed by an integrated circuit (IC), or the processed electrical signal can be converted into an optical signal to be transmitted via optical fiber. Therefore, the purpose of communication can be achieved.

[0005] Over the past few decades, the use of communication networks has surged. In the early days of the internet, popular applications were limited to email, bulletin boards, and largely informational, text-based web browsing, with relatively small amounts of data being transmitted. Today, the internet and mobile applications require massive amounts of bandwidth to transmit photos, videos, music, and other multimedia files. For example, social networks like Facebook process over 500TB of data daily. Such high demands on data and its transmission necessitate improvements to existing data communication systems to address these needs.

[0006] Achieving broadband wavelength division multiplexing (WDM) optical transmission with data rates of 40 Gbps and then 100 Gbps over existing single-mode fiber is the goal of next-generation fiber optic communication networks. Recently, optical components have been integrated onto silicon (Si) substrates for the fabrication of large-scale photonic integrated circuits that coexist with microelectronic chips. For many applications, such as broadband dense wavelength division multiplexing (DWDM) or coarse wavelength division multiplexing (CWDM) communications and wavelength-manipulated optical detection, chip-scale lasers directly packaged within silicon photonic optoelectronic systems have attracted considerable interest. Complete photonic components, including filters, demultiplexers, splitters, modulators, and photodetectors, primarily on silicon-on-insulator (SOI) platforms, have been demonstrated. Because silicon (n=3.48) and its oxide SiO2 (n=1.44) are both transparent and form high refractive index contrast and highly confined waveguides, the SOI platform is particularly suitable for the standard DWDM communication band around 1550nm or the CWDM communication band around 1310nm, which is ideal for medium-to-high integration planar integrated circuits (PICs).

[0007] With advancements in optical communication technology and market-driven applications, the demand for increasing optical communication bandwidth and reducing the package size of optical transceivers has become increasingly strong. Integrating all necessary components into increasingly smaller module packages is becoming increasingly challenging. For state-of-the-art optical transceiver products, all critical components—including clock data recovery (CDR), modulator drivers, transimpedance amplifiers (TIAs), and programmable logic controller (PLC) photonic blocks with optical passive components, modulators, and photodetectors—are assembled side-by-side in a 2D manner on the same SOI-based component substrate. This approach has at least two drawbacks for developing any future optical transceivers with data rates greater than 400G. First, the side-by-side placement of these components occupies a large portion of the board area of ​​the optical transceiver, which is a pluggable product, or the main substrate area of ​​the board optics, making it difficult to further reduce product size. Second, side-by-side placement on the substrate results in longer electrical transmission lengths and often requires wire bonding between the electrical dies and photonic dies, introducing more electrical losses that compromise signal integrity for very high data rate transceiver products (e.g., >56Gbaud symbol rates). Specifically, wire bonding can lead to impedance mismatch due to its high inductance, thus degrading higher-frequency signals. Therefore, using wire bonding for electrical interconnects between chips or between chips and circuit boards is impractical for applications transmitting high-frequency (e.g., >40GHz) analog signals. The large inductance of wire bonding has become a bottleneck for high-speed data transmission.

[0008] To shorten the interconnect length of conventional wire bonding between electronic devices (e.g., from modulator drivers / TIAs to digital signal processors (DSPs)) or between electronic devices (drivers / TIAs) and photonic devices (e.g., CDRs and PAM4 ASICs), the use of through-silicon vias (TSVs) and silicon interposers in Si photonic dies has begun to replace wire bonding for interconnection. With advancements in silicon TSV manufacturing processes, the fabrication of silicon photonic components and the integration of active components into wafer-level assemblies and aging tests, along with in-package optoelectronic modules assembling multiple optical engines on a single module substrate, will offer significant performance advantages and required bandwidth capacity for a wide range of applications involving backplane reach, mid-range, short-range, or ultra-short-range interconnect switches for high-speed data communications. Summary of the Invention

[0009] This invention relates to optical communication technology. More specifically, it provides an in-package optoelectronic module that assembles multiple sub-modules on a single line card, each sub-module being configured to include a multi-channel optical engine with an optoelectronic transceiver based on a silicon photonics platform. By way of example only, this invention discloses a sub-component for a sub-module that integrates multiple laser chips providing multiple CWDM channels on a single silicon photonics substrate; a compact package for multiple such sub-components of a sub-module on a single line card, providing a total data exchange capacity of 1.6 Tbit / s or higher in various applications of high-speed data communication with different interconnect lengths, although other applications are also possible.

[0010] In modern electrical interconnect systems, high-speed serial links have replaced parallel data buses, and serial link speeds are rapidly increasing due to advancements in CMOS technology. According to Moore's Law, internet bandwidth nearly doubles every two years. However, Moore's Law will end within the next decade. Standard CMOS silicon transistors will shrink to around 3nm. Furthermore, the increase in internet bandwidth due to process scaling will plateau. However, internet and mobile applications continuously demand significant bandwidth for transmitting photos, videos, music, and other multimedia files. This disclosure describes techniques and methods to improve communication bandwidth beyond Moore's Law.

[0011] In one embodiment, the present invention provides an in-package multichannel optical engine. The in-package multichannel optical engine includes four or more sub-components of an optoelectronic module. Each sub-component is assembled in a housing forming a cover member that covers peripheral side members on the peripheral edge region of the sub-module substrate. Each optoelectronic module includes at least four laser chips, one or more driver chips, and one or more transimpedance amplifier (TIA) chips, which are flip-chip mounted on a silicon photonics substrate and coupled to an optical interface block and an electrical interface block commonly mounted on the corresponding sub-module substrate. The in-package multichannel optical engine also includes a first frame retainer having cross-joining rods across a central region to form four or more window structures configured to allow four or more sub-components to be mounted to the top surface of the top cover member and the bottom surface of the corresponding sub-module substrate, respectively. Furthermore, the in-package multichannel optical engine includes a second frame retainer configured to hold the first frame retainer together with the four or more sub-components. The in-package multichannel optical engine also includes an insertion board having a top side, a bottom side, and multiple through-plate conductive vias and internal conductive paths. The top side has four or more first sets of conductive bumps, and the bottom side has four or more second sets of patterned conductive bumps. The through-plate conductive vias and internal conductive paths are configured to connect the first sets of conductive bumps to the four or more second sets of patterned conductive bumps. Each first set of conductive bumps is configured to be bonded to a corresponding submodule substrate. Furthermore, the in-package multichannel optical engine includes a module substrate having a top side with four or more sets of conductive bump contacts configured to be bonded to the four or more second sets of conductive bumps, respectively. The in-package multichannel optical engine also includes a backplane member attached to the bottom side of the module substrate. Furthermore, the in-package multichannel optical engine includes a top plate component configured to compress a second frame fixture that vertically secures a first frame fixture, which has four or more sub-assemblies, an insert plate, and a module substrate, to a back plate component. The top plate component is configured as a heat sink with a multi-fin structure.

[0012] In a specific embodiment, the present invention provides a sub-assembly of a multi-channel optical engine. The sub-assembly includes a sub-module substrate divided as a bottom member, and a peripheral frame member having four sides arranged along a peripheral region on the front side of the sub-module substrate. The peripheral frame member has an opening slot passing through at least one side. The sub-assembly also includes a silicon photonics substrate electrically bonded via through-substrate via bump contacts on the front side of the sub-module substrate. The silicon photonics substrate is configured to fabricate a plurality of Si-based waveguide devices therein. Furthermore, the sub-assembly includes one or more driver chips, one or more transimpedance amplifier chips, and a plurality of laser chips, which are respectively mounted on the silicon photonics substrate and coupled to corresponding Si-based waveguide devices to form transmitter and receiver units. The sub-assembly also includes an optical interface block containing a plurality of planar waveguide devices formed on a glass or sapphire substrate mounted on the front side of the sub-module substrate adjacent to the silicon photonics substrate. The plurality of planar waveguides are optically coupled to corresponding Si-based waveguide devices and optical fibers in an optical fiber cable, the optical fibers being laid through an opening slot passing through at least one side. The optical interface block is configured to transmit the output from the transmitter unit to the output optical fiber and to receive input multi-wavelength optical signals from the input optical fiber for the receiver unit. Furthermore, the sub-assembly includes an electrical interface block comprising multiple ASIC chips mounted on the front or rear of the sub-module substrate. These ASIC chips are configured to receive data signals (based on which control signals for the laser chip are generated) and process the incident optical signals into digital signals for use by the main unit. Additionally, the sub-assembly includes a top cover member that covers the peripheral frame members to surround the optical engine. Attached Figure Description

[0013] Figure 1 This is a simplified block diagram of an integrated optoelectronic module according to an embodiment of the present invention.

[0014] Figure 2 This is an example diagram of an optoelectronic transceiver integrating four lasers according to an embodiment of the present invention, which is configured with four CWDM channels and four replication channels.

[0015] Figure 3 This is a schematic top view of a wafer-level assembly of multiple packaged silicon photonic chips on a single substrate according to an embodiment of the present invention.

[0016] Figure 4 This is a schematic top view of an encapsulated optoelectronic module containing four sub-module optical engines according to an embodiment of the present invention.

[0017] Figure 5 It is a method for using according to an embodiment of the present invention. Figure 4An exploded view of the package of the optoelectronic module, which is integrated with a heat sink and interfaces with a line card printed circuit board.

[0018] Figure 6 It is according to an embodiment of the present invention. Figure 5 The exploded diagram of the four sub-modules of the light engine in the encapsulation.

[0019] Figure 7 It is according to an embodiment of the present invention. Figure 6 An exploded view of the light engine sub-module, which is a sub-module of the light engine. Detailed Implementation

[0020] This disclosure relates to structural analysis for determining fault types in safety-related logic.

[0021] Integrated circuit (IC) designs include safety circuitry (e.g., security mechanisms) for detecting faults within the IC design. The IC design may be a system-on-a-chip (SoC) design. The safety circuitry detects faults associated with an influence cone. The influence cone used for the safety circuitry may be referred to as a safety cone. An influence cone includes one or more observation points (e.g., outputs) of the IC design, one or more inputs of the IC design, and one or more circuit elements of the IC design coupled between the observation points and the inputs. The safety circuitry is part of the safety-related features of the IC design and is implemented to detect faults or failures within the IC device. For example, a fault might be due to signal corruption and / or circuit element failure. Detected faults can be mitigated by adjusting the functionality of the corresponding IC device. In other examples, other mitigation techniques may be applied. However, not all faults can be detected by the associated safety circuitry. The associated safety circuitry corresponds to a fault cone of the fault. Therefore, such a fault may lower the safety analysis rating of the corresponding IC device.

[0022] During the IC design process, data is collected based on faults and used to identify functional safety-related aspects. Functional safety-related aspects may include Design Failure Mode and Effects Analysis (DFMEA) or Fault Tree Analysis (FTA).

[0023] The DFMEA process includes capturing various failure modes in the IC design and determining the impact of each failure mode. The IC design includes safety-critical design elements, which include non-safety-critical logic and safety-critical logic. Failures occurring in non-safety-critical logic are considered not to cause a violation of the safety objectives in the IC design. Such failures can be referred to as safety failures. A failure is a fault within a circuit element or signal in the IC design. When a circuit element fails, its function differs from its intended behavior. Furthermore, faults in signals correspond to signals with unexpected values.

[0024] Security objectives correspond to the desired functionality of the corresponding circuitry. For example, security objectives correspond to the correct transmission and / or reception of signals. In one or more examples, a breach of a security objective occurs when a circuit element (e.g., logic) involved in data transmission malfunctions. Security circuitry or another monitoring device (e.g., external circuitry or electrical components) is involved. This invention relates to optical communication technology. More specifically, the invention provides an in-package optoelectronic module that assembles multiple sub-modules on a single line card, each sub-module being configured to include a multi-channel optical engine based on a silicon photonics platform optoelectronic transceiver. By way of example only, the invention discloses a sub-assembly for integrating a sub-module with four CWDM channels and four optically replicated CWDM channels on a single silicon photonics substrate; a compact package for multiple such sub-assemblies on a single line card, which provides high-speed data of 0.4 Tbit / s or higher per sub-module to build the required switching capacity in various applications utilizing different interconnect lengths, although other applications are also possible.

[0025] In one aspect, the present invention provides an integrated optoelectronic module based on a silicon photonics platform and an in-package optical assembly comprising four or more sub-modules on a module substrate having an optical channel speed of 1.6 Tbit / s or higher for PAM backplane / optical range for various interconnect ranges of data communication. With the increasing data transmission capacity in WDM systems, the demand for high-speed, compact optical transceivers based on silicon photonics platforms has attracted increasing attention in recent years. For example, compact pluggable optical transceivers. However, compact optical transceivers are still standalone devices that need to be coupled to separate passive optical devices (e.g., multiplexers / demultiplexers and one or more gearboxes or retimers) to connect with electrical switching devices to form a functional optical engine, which requires a considerable package size and high power consumption.

[0026] Figure 1 A simplified block diagram of an integrated optoelectronic module according to an embodiment of the present invention is shown. Figure 1This is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As shown, in one embodiment, the integrated optoelectronic module includes: a host interface configured to receive host data input via N 25G (NRZ) or 50G (PAM4) or 100G (PAM4) channels; and a digital processor processing the data signals via a retimer chip having N to N channels. Optionally, the digital processor processes the data signals via gearbox N to M channels, where N is a multiple of M. Optionally, the host interface is configured in one or more chips, the host interface including forward error correction (FEC) channel coding for controlling errors in data transmission over unreliable or noisy communication channels. In this embodiment, the integrated optoelectronic module also includes an optical line interface configured with four wavelength CWDM lasers modulated to convert N electrical data into optical signals in N optical channels. Optionally, an optical engine with a similar configuration can form >4 wavelengths. Optionally, four or more wavelengths can be selected to have half the spacing compared to a nominal CWDM channel. The optical signal is transmitted via optical line data output multiplexed in a waveguide or optical fiber. Optionally, the laser chip, driver chip, and transimpedance amplifier (TIA) chip are integrated on a silicon photonics substrate. Optionally, the silicon photonics substrate is mounted via an inserter on the same submodule substrate for mounting one or more chips containing a host interface. Optionally, the silicon photonics substrate is the inserter. Optionally, an analog control chip for laser and modulator control is mounted on the rear of the submodule substrate. Optionally, the TIA chip, driver chip, or microcontroller chip may also be mounted on the rear of the submodule substrate. Optionally, the integrated optoelectronic module is configured to have an external power interface for power coupling and to receive module control signals via a host control interface such as an I2C interface.

[0027] Figure 2 This is an example diagram of an optoelectronic transceiver integrating four lasers according to an embodiment of the present invention, which provides four CWDM channels and four replication channels. Figure 2This is merely an example and the figure should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. In one embodiment, the optotransceiver 1000 integrates four laser chips 110 with a driver chip 150 and a TIA chip 140 flip-chip mounted on a silicon photonics (SiPho) substrate 100 to form a SiPho chip coupled to an external planar optical circuit (PLC) block 200. As shown, the optotransceiver 1000 is specifically configured as a 4-wavelength CWDM optical transceiver including an optical receive path and an optical transmit path. In the optical receive path, the optotransceiver 1000 is configured to receive four incident optical signals of four wavelengths demultiplexed from an optical input 221. In the optical transmit path, the optotransceiver 1000 is configured to output four optical signals of four CWDM channel wavelengths multiplexed into a single optical output 211. The 4-to-1 multiplexer (Mux) 210 is a PLC waveguide device formed on a glass or sapphire substrate and configured to multiplex four CWDM channel wavelengths into one waveguide or optical fiber. The 1-to-4 demultiplexer (Demux) 220 is another PLC waveguide device formed on the same glass or sapphire substrate, configured to demultiplex an incident optical signal into four multiplexed wavelengths carrying a high-speed modulated signal from the network. The optoelectronic transceiver 1000 also includes a plurality of high-speed photodetectors 130 that detect each of the four optical signals having the four demultiplexed wavelengths. In this embodiment, both the multiplexer 210 and the demultiplexer 220 are integrated into the PLC block 200. Optionally, the PLC block 200 includes a plurality of optical waveguides formed in a single glass or sapphire substrate, which are aligned with corresponding waveguides in the silicon photonics substrate 100.

[0028] refer to Figure 2The optoelectronic transceiver 1000 includes a set of four CWDM lasers 110, which provide four CWDM channel optical signals with wavelengths centered at 1270 nm, 1290 nm, 1310 nm, and 1330 nm, respectively. Optionally, each laser device is a DFB laser chip. Optionally, each laser chip 110 is configured as a separate laser chip manufactured individually and flip-chip mounted on a silicon photonics substrate 100. Optionally, each optical signal output from a corresponding laser chip is aligned to a silicon waveguide embedded in the silicon photonics substrate 100. First, each optical signal is coupled to a power splitter 120 through the silicon waveguide and split into two optical signals in two independent branches with a separation ratio from 5:95 to 50:50. Optionally, one of the split optical signals from the secondary split branch of the power splitter 120 is used for monitoring, wavelength locking, or feedback control. Optionally, an optical signal from a main split branch of power splitter 120 is fed into one of four modulators 160. Optionally, the power splitter is a 50:50 splitter, converting the optical signal into two replicated optical signals, which essentially doubles the number of channels. Each replicated optical signal is fed into a modulator. Overall, Figure 2 The optoelectronic transceiver 1000 is shown with four modulators 160 for receiving optical signals from four first branches (01), while four other modulators for four second (replica) branches (02) are not explicitly shown. Of course, many variations in functional settings or optical layouts are possible besides a single optoelectronic transceiver (including four CWDM channels and four replicated CWDM channels) to process these optical signals and to configure the optoelectronic module 100 differently for different applications. For example, the optoelectronic transceiver 1000 may optionally include a group (>4) of lasers with a smaller channel spacing than the CWDM channels to provide >4 wavelengths. The entire system would then have to operate within the same multi-wavelength plane.

[0029] Optionally, the modulator 160 in any of the first branches 01 is based on a Mach-Zehnder modulation scheme using linear waveguides. Each modulator 160 includes two waveguide branches with a desired phase delay, configured to match a corresponding one of the four wavelengths 1270nm, 1290nm, 1310nm, and 1330nm for the four CWDM channels. Optionally, the four wavelengths can be selected from a group of 1270nm, 1280nm, 1290nm, and 1300nm or a group of 1300nm, 1310nm, 1320nm, and 1330nm with a smaller channel spacing. A driver module 150 is provided as a separately fabricated CMOS or SiGe chip flip-chip mounted on the same silicon photonics substrate 100. Optionally, redundant or duplicated driver modules 150' are also provided. Figure 2The redundant or duplicate driver module 150', which is a chip flip-chip mounted on the same silicon photonics substrate 100, is used to drive the other four modulators (not shown) in the duplicated split branch. Driver module 150 is configured to drive all four modulators 160 to modulate optical signals in four CWDM channels. Optionally, an 8-channel driver can drive four channels and four duplicated channels. Optionally, driver module 150 uses a PAM-N (N is an integer) modulation protocol or an NRZ modulation protocol to modulate the optical signals. For example, modulator 160 is provided as a silicon waveguide-based Mach-Zehnder interferometer, configured to provide PAM4 modulation, although other formats may be used. After modulation, the optical signals from the four CWDM channels are directed to a 4-to-1 multiplexer (Mux) 210 in PLC block 200, which outputs the multiplexed optical signals to output port 211 of submodule 1000 via optical fiber (not shown). Optionally, another 4-to-1 multiplexer (not shown) is formed in PLC block 200 to combine the other four replicated CWDM channels of the optical signal into a single multiplexed optical signal, which is guided to output port 211 via another optical fiber (not shown). Effectively, the combination of four laser chips 110 and four or eight modulators 160 driven by driver module 150 or a replica driver module 150' forms an integrated 4-channel optical transmission path and another 4-channel replicated optical transmission path. Figure 2 (Not shown in the image).

[0030] Refer again Figure 2The optoelectronic transceiver submodule 1000 includes a four-channel optical receiving path. In this optical receiving path, an optical demultiplexer 220 in the PLC block 200 receives input optical signals from an external network via an input port 221, which is configured to operate at four CWDM channel wavelengths to transmit corresponding data signals. The input optical signal carrying the four multiplexed wavelengths is demultiplexed into four individual optical signals of the corresponding four wavelengths, which are respectively guided into four waveguides formed in the silicon photonic substrate 100. A high-speed photodetector 130 is used to detect these four optical signals separately and convert them into corresponding current signals. In this embodiment, the four-channel optical receiving path of the optoelectronic transceiver submodule 1000 also includes a transimpedance amplifier (TIA) module 140, which independently processes the current signals converted from each of the four individual optical signals for communication with the host power grid system via a host interface. Optionally, the TIA module 140 is formed separately and flip-chip mounted on the same silicon photonics substrate 100. Optionally, because the four replicated channel optical signals can be demultiplexed from the other input optical signal by another demultiplexer, the optoelectronic transceiver submodule 1000 also includes replicated 4-channel optical receive paths. The replicated 4-channel optical receive paths may include replicated TIA modules 140' (…). Figure 2 (Not shown in the image), the replicated TIA module 140' is used to independently process four additional electrical signals converted from the corresponding four replicated optical signals in order to communicate with a host electrical network system having a bandwidth extended by 2x. Optionally, the TIA module 140 is also a flip chip mounted on the same silicon photonics substrate.

[0031] In another aspect, this disclosure provides a manufacturing process for integrated optoelectronic modules (such as transceiver submodule 1000) based on a silicon photonics platform. In some embodiments, the manufacturing process includes wafer-level assembly of a 2.5D silicon photonic substrate involving a 2.5D silicon inserter and a 220nm silicon-on-insulator (SOI) substrate. The process includes monolithically forming multiple silicon or silicon nitride waveguides in the silicon photonic substrate 100 for connection or alignment with several different silicon photonic devices, including a power splitter, a SiGe or Ge high-speed photodetector, and a Si / SiN-based Mach-Zehnder interferometer modulator device formed in the same silicon photonic substrate 100. The process also includes coupling the silicon waveguides to passive PLC devices, such as optical multiplexers and optical demultiplexers formed on a glass or sapphire substrate and mounted as PLC blocks 200 on the silicon photonic substrate. The process also includes flip-chip mounting of active devices, such as laser chips, onto a silicon photonic substrate as part of a packaging design, and aligning the laser chip directly with a waveguide in the silicon photonic substrate or a PLC device in a PLC block. Optionally, some of the aforementioned silicon photonic components are themselves monolithically formed silicon waveguides in the same manufacturing process for use in fabricating the silicon photonic substrate to integrate the optoelectronic transceiver submodule 1000.

[0032] Figure 3 A schematic top view of multiple packaged silicon photonic chip wafer-level assemblies on a single substrate according to an embodiment of the present invention is shown. Figure 3 This is merely an example and the figure should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. As illustrated, using an integrated optoelectronic transceiver submodule as an example, the silicon photonic substrate 100 is a die manufactured using a CMOS-compatible process plus a post-CMOS wafer-level assembly of an SOI wafer 10. In this example, each die 100 is used to form an optoelectronic module by directly processing the SOI wafer to form a silicon photonic through-substrate via (TSV) inserter. Further details regarding the fabrication process of the TSV inserter can be found in U.S. Patent Application No. 15 / 887758, filed February 2, 2018, and co-assigned to Inphi Corp., Santa Clara, CA. The above application is incorporated herein by reference for all purposes. Using this silicon photonic TSV inserter, several optical or electrical components for forming an optoelectronic module can be directly mounted. References Figure 3Enlarging a die 100 in wafer 10 to show several electrical and optical components, the die includes two driver chips 150, 150', two TIA chips 140, 140', two dummy chips 190, and four field-effect transistors 145 (for applying bias to laser chip 110). The driver chips 150, 150', two TIA chips 140, 140', two dummy chips 190, and four field-effect transistors 145 are flip-chip mounted to the top side of the die in a post-CMOS wafer-level assembly. Specifically, the four laser chips 110 are also directly flip-chip mounted to their respective chip locations on the die and aligned with the waveguide optics formed therein as a package component without requiring any additional wire bonding.

[0033] For further reference Figure 3 Multiple redundant dies are arranged in multiple pairs of rows on a wafer substrate 10. Each die 100 includes four CWDM laser chips 110. The wafer substrate 10 is also configured to accommodate multiple rows of scintillation detection pads 300, which are designed for convenient wafer-level aging and testing. Each detection pad 300 includes an electrode 310 for easy coupling to external test electrodes to allow appropriate bias current to be applied in series to the multiple laser chips on the wafer substrate 10. Further details regarding the design of chip locations on the dies for mounting the laser chips and performing wafer-level aging and testing on the laser chips can be found in U.S. Patent Application No. 16 / 800974, filed February 25, 2020, co-assigned to Inphi Corp., Santa Clara, CA, and incorporated herein by reference for all purposes.

[0034] In another aspect, this disclosure provides an internally packaged optoelectronic module that is assembled with the four optoelectronic modules described above. Figure 4 A schematic top view of an internally packaged optoelectronic module comprising four sub-module optical engines according to an embodiment of the present invention is shown. Figure 4 This is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Figure 4 In the illustrated embodiment, the in-package optoelectronic module 3000 is provided by uniformly packaging four sub-modules 2000A, 2000B, 2000C, and 2000D in four compact regions on a common component substrate 2001. Optionally, each sub-module is formed on its own component substrate, referred to as the sub-module substrate.

[0035] Figure 4Each of the four sub-modules is essentially redundant and independently functions as a 4-wavelength transceiver driven by 4 packaged lasers, providing 4 optical signals for 4 CWDM channels and 4 replicated CWDM channels, such as... Figure 2 The block diagram is shown. Optionally, the in-package optoelectronic module can integrate two sub-modules. Optionally, the in-package optoelectronic module can integrate six or more sub-modules. (See reference...) Figure 4 In the example, each 4-wavelength transceiver includes... Figure 3 A silicon photonics (SiPho) chip 100 is cut from a die of a wafer substrate 10. Four CWDM channels are provided by four optical signals from four laser chips 110, centered at wavelengths of 1270 nm, 1290 nm, 1310 nm, and 1330 nm, respectively. These four laser chips are flip-chip-mounted directly onto the SiPho chip 100 with their p-type sides facing the SiPho chip. The lasers emitted from each laser chip 110 are aligned with silicon-based waveguides formed within the SiPho chip 100. Optionally, the silicon-based waveguides include optical splitters to split the lasers into two branches, providing four CWDM channels and four replicated CWDM channels. Accordingly, each SiPho chip 100 includes a driver chip 150 and a TIA chip 140 for processing the transmission and detection of optical signals involving four CWDM channels, and includes a duplicate driver chip 150' and a duplicate TIA chip 140' for processing the transmission and detection of optical signals associated with the four duplicate CWDM channels. The SiPho chip 100 is coupled to a planar optical circuit (PLC) block 200, both of which are bonded to the top side of the corresponding submodule substrate 2001.

[0036] Optionally, Figure 4Each of the four sub-modules (e.g., 2000A in the upper left section) also includes a digital signal processing (DSP) chip 2030 and a replica DSP chip 2030' and a microcontroller chip 2040, all mounted on the top surface of the sub-module substrate 2001 on the same side as the SiPho chip 100 and the PLC block 200. Both driver chips 150 and 150' interface with an external host system via the DSP chips 2030 (and 2030') respectively through a host interface to process electrical data input from the host system. The DSP chip is also configured to interact with the microcontroller chip 2040 via a host control interface to provide the module control and power required to operate the SiPho chip 100. Optionally, the DSP chips 2030 and 2030' include a gearbox or retimer chip for converting analog signals to digital signals via N-to-N channel electrical data transmission, a digital processor for processing the digital signals, one or more interface devices for communicating with an external host system, and a current driver for driving the four laser chips. Optionally, the microcontroller chip 2040 is associated with a corresponding submodule 2000A and configured to control the operation of the DSP chip 2030, driver 150, TIA 140, and the interfaces therein. Optionally, the modulator in the SiPho chip is configured to modulate the laser signal based on the PAM-N protocol (e.g., the PAM-4 protocol) or the NRZ protocol. Optionally, the modulator is configured in a Mach-Zehnder interferometer formed by silicon-based waveguides in a silicon photonic substrate.

[0037] The PLC block 200 associated with each of the four submodules 2000A (to 2000D) includes at least: a first optical multiplexer in the optical transmission path (see...). Figure 2 The PLC block 200 has a first optical multiplexer to multiplex the optical signals of four CWDM channels into one output light in one optical fiber; and a second optical multiplexer in the replicated optical transmission path to multiplex the four replicated optical signals into another output light in another optical fiber. Each optical multiplexer in the PLC block 200 is a planar waveguide formed on a glass or sapphire substrate and suitably coupled to an optical fiber. Both optical fibers can be encapsulated in an onboard fiber optic cable 2010A (to 2010D) coupled between the PLC blocks 200. For each submodule (e.g., 2000A), an optical transceiver transmits eight total output optical signals to an external optical network, carrying four CWDM channels and four replicated CWDM channels. In this embodiment, the compact in-package optoelectronic module 3000 includes a total of four submodules 2000A to 2000D to transmit a total of 32 CWDM channel signals to an external optical network.

[0038] In this embodiment, the PLC block 200 associated with the same module (e.g., 2000A (to 2000D)) of the four sub-modules also includes a built-in optical receiving path configured to receive optical signals incident from the network via an optical fiber. The PLC block 200 includes at least one first optical demultiplexer to demultiplex an incident optical signal (carrying four wavelengths) from a single optical fiber into four separate optical signals having corresponding four CWDM channel wavelengths. Each optical demultiplexer in the PLC block 200 is a planar waveguide formed on a glass or sapphire substrate and suitably coupled to an optical fiber. Each of the four separate optical signals is coupled from the planar waveguide in the PLC block 200 to a waveguide in a silicon photonics substrate and then transmitted to a photodetector module (see [link to PLC block 200]). Figure 2 ). Photodetector block (130, such as Figure 2 Each optical signal (as shown) is individually detected and converted into a current signal, which is then passed to and processed by the transimpedance amplifier (TIA) module 140 to generate a voltage signal. The voltage signal is further processed or digitized by the onboard DSP chip 2030 and fed to an external host receiver. The incident optical signal, as described above, can be received via optical fiber also encapsulated in the onboard fiber optic cable 2010A. Optionally, a second optical demultiplexer is included in the PLC block 200 for receiving and demultiplexing another incident optical signal carrying four replicated CWDM channel wavelengths into the replicated receive optical path to provide additional bandwidth for the four replicated CWDM channels, which can be individually detected by the photodetector and converted into corresponding electrical signals. The electrical signals can be processed by the replicated TIA module 140' and digitally processed by the DSP chip 2030' in the same submodule.

[0039] In this embodiment, PLC block 200 includes two 4-to-1 or two 1-to-4 demultiplexers to create two sets of four optical paths. For a multi-channel optical engine 3000 that packages a total of four optoelectronic modules 2000A, 2000B, 2000C, and 2000D, the multi-channel optical engine 3000 can detect different input optical signals in 32 channels. With each channel carrying data at a rate of 50 Gbit / s, each quadrant submodule uses four CWDM lasers to transmit data at a rate of 400 Gbit / s. The in-package optoelectronic module 3000 can provide a data exchange communication capacity of 1.6 Tbit / s. In another case, using an improved modulator, driver chip, TIA chip, and DSP chip, each channel can carry a rate of 100 Gbit / s even if each quadrant submodule uses the same four CWDM lasers. As a result, the in-package optoelectronic module 3000 can extend its data exchange communication speed to 3.2 Tbit / s.

[0040] On the other hand, this disclosure provides, as stated above Figure 4 The encapsulation component of the internally packaged optoelectronic module. Figure 5 , Figure 6 and Figure 7 Several exploded views are shown at different levels of the encapsulation structure and the mounting fasteners for the sub-modules and components within that encapsulation structure. Figure 5 It is a method for using according to an embodiment of the present invention. Figure 4 An exploded view of the encapsulation assembly 5000 of an internally packaged optoelectronic module, which is integrated with a heat sink and interfaces with a printed circuit board-based module line card. Figure 6 This illustrates an embodiment of the invention for use in... Figure 5 The encapsulation component of the four sub-modules in the middle encapsulates the sub-components of the four sub-modules 3000A. Figure 7 The present invention illustrates an embodiment of the present invention. Figure 5 and Figure 6 Detailed sub-components of all parts in a submodule 2000A. Figure 5 , Figure 6 and Figure 7 This is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications.

[0041] like Figure 5 As shown, compression is achieved between the top plate member 3020 at the top and the back plate member 3060 at the bottom. Figure 4 The multi-channel optical engine 3000 uses a sub-component 3000A to set the encapsulation component 5000. For example... Figure 6 As shown, the sub-assembly 3000A of the internally packaged optoelectronic module 3000 includes a single solid frame fastener member 3002 having two interlocking intermediate rods to form four tightly encapsulated window structures 3008A, 3008B, 3008C, and 3008D. The four window structures are designed to allow the installation of four sub-assemblies (i.e., 2000A, 2000B, 2000C, and 2000D), respectively. Each sub-assembly (e.g., 2000A) is designed to encapsulate the corresponding submodule within a housing closed at the top by a cover member 2200A and sealed at the bottom by a peripheral side member 2100A surrounding the submodule substrate 2300A. Figure 7 The encapsulation structure and component layout of each sub-component with sub-modules (e.g., 2000A) are shown. Further details are described in the following paragraphs.

[0042] refer to Figure 6The solid fastener member 3002 includes recesses 3005-1 and 3005-2, which at least partially open downwards at one intermediate rod and one side of the frame fastener member 3002. The cover member (e.g., 2200B) of each subassembly (e.g., 2000B) includes an opening slot 2105-B that extends upwards through one side of the peripheral member 2100B to align with recess 3005-1. The opening slot 2105-B provides an opening space for laying optical cable pairs 2010A and 2010B, which encapsulate optical fibers outside the optoelectronic modules within subassemblies 2000A and 2000B, respectively. Similarly, another pair of optical cables 2010C and 2010D also encapsulate optical fibers outside of sub-assemblies 2000D and 2000C, and this other pair of optical cables 2010C and 2010D are laid in the open space provided by the opening slot 2105-C aligned with the notch 3005-2.

[0043] refer to Figure 5 and Figure 6 When sub-component 3000A is assembled in encapsulation assembly 5000, the top surfaces of the cover members (e.g., 2200A) of the four sub-components (e.g., 2000A) are mechanically pressed against the bottom surface of the top plate member 3020 in encapsulation assembly 5000 in a manner with good thermal contact. In an embodiment, as... Figure 5 As shown, a heat sink is disposed on the top side of the top plate member 3020, the heat sink having a plurality of vertically extending heat sink structures 3021. The height of the plurality of heat sink structures is designed to facilitate the release of module heat with sufficiently high efficiency. Optionally, a thermal pad (not shown) may be inserted between the top surface of the cover member and the bottom surface of the top plate member 3020 to enhance thermal conductivity. The heat sink is configured to release heat generated by four sub-modules in the sub-assembly 3000A, each of which contains four CWDM lasers and a plurality of pre-packaged CMOS chips (such as driver chip 150 and TIA chip 140 and DSP chip 2030). Mechanically, the top plate member 3020 is pressed by a plurality of spring-loaded compression pins 3030 having threaded heads applied from the top side to lock with the back plate member 3060 in the package assembly 5000 in the corresponding socket 3063.

[0044] refer to Figure 7The sub-assembly of submodule 2000A includes a housing with a top cover member 2200A covering a peripheral side member 2100A located in the peripheral boundary region surrounding the top of submodule substrate 2300A, which serves as the bottom member of subassembly 2000A. Optionally, subassembly 2000A is assembled with a quadrant portion of one of the four window structures (e.g., 3008A) of encapsulating subassembly 3000A. Optionally, peripheral side member 2100A includes at least one opening slot 2105-A for laying at least one fiber optic cable 2010A for the optical input / output fiber of the optoelectronic module in the subassembly. Optionally, a thermal pad (not shown) may be attached to the top surface 2201A of cover member 2200A to enhance the heat dissipation efficiency of subassembly 2000A. Alternatively, the submodule substrate 2300A is also configured to allow heat to be effectively conducted through itself.

[0045] In one implementation, such as Figure 7 As shown, the submodule encapsulated in sub-assembly 2000A includes a SiPho chip encapsulated on a silicon photonics substrate 100, which is mounted on the top side of the submodule substrate 2001A. The SiPho chip 100 is substantially similar to that used in... Figure 3 The wafer-level assembly process shown is identical to that used to form a die on SOI wafer 10. (Reference) Figure 7 The SiPho chip 100 includes a driver chip 150 and a duplicate driver chip 150', a TIA chip 140 and a duplicate TIA chip 140', and four laser chips 110, all of which are flip-chip mounted on top of the same silicon photonics substrate 100. Some virtual chips (not shown) and field-effect transistor devices 145 may also be mounted on top of the same silicon photonics substrate 100. The SiPho chip includes a transmitter unit configured to generate multi-channel optical signals from the four laser chips, which are modulated by four modulator devices driven by the driver chip based on data received via an electrical interface block. The multi-channel optical signals are sent to an optical transmission path coupled to the optical interface block to output multiplexed optical signals.

[0046] In this embodiment, the same SiPho chip also includes a receiver unit configured to use a set of photodetectors to detect multi-channel optical signals received in the optical receiving path and demultiplexed from incident multiplexed optical signals in the optical interface block. A TIA chip is used to convert the detected multi-channel optical signals into current signals, which are digitized and processed in the electrical interface block before being transmitted as N-to-N channel digitized signals to the host computer. An optical transmission path and an optical receiving path are included in the same silicon photonic substrate 100. A driver chip 150 and a TIA chip 140 in the SiPho chip are involved in processing the transmission of four optical signals from four laser chips to the optical transmission path and detecting four incident optical signals from the optical receiving path. Another driver chip 150' and another TIA chip 140' are respectively involved in processing the transmission of four replicated optical signals from four laser chips to the optical transmission path and detecting four additional incident optical signals from the optical receiving path. The TIA / driver chips in each SiPho chip of the packaged sub-component 2000A are configured to process the reception and transmission of optical signals in two replicates of four CWDM channels, each with a wavelength center at 1270 nm, 1290 nm, 1310 nm, and 1330 nm. Optionally, the electrical interface block includes a digital signal processing (DSP) chip 2030 configured to process N to N channels of digitized signals at a data rate of 25 Gbits per second per channel. Optionally, the electrical interface block includes a digital signal processing (DSP) chip 2030 configured to process N to N channels of digitized signals at a data rate of 50 Gbits per second per channel. Optionally, the electrical interface block includes a digital signal processing (DSP) chip 2030 configured to process N to N channels of digitized signals at a data rate of 50 Gbits per second per channel. Optionally, the electrical interface block includes a copy of the digital signal processing (DSP) chip 2030' and the microcontroller chip 2040.

[0047] For further reference Figure 7 Along one side of the SiPho chip on the silicon photonics substrate 100, a PLC block 200 is also mounted on the submodule substrate 2300A. The PLC block 200 includes one or more multiplexers and one or more demultiplexers formed in a PLC-based waveguide on a glass or sapphire substrate for guiding light waves to the optical output port of the sub-assembly 2000A and guiding light waves from the optical input port of the sub-assembly 2000A by coupling optical signals between the PLC block 200 and the input / output fiber. The input / output fiber of each sub-assembly is encapsulated in a fiber optic cable 2005-1.

[0048] In addition, refer to Figure 7 Along the other side of the SiPho chip on the silicon photonics substrate 100, one or more ASIC chips, such as digital signal processing (DSP) chips 2030 (2030'), can be flip-chip mounted on the same submodule substrate 2300A. Each DSP chip 2030 or 2030' is configured in an electrical interface block to support the functions of a TIA chip 140 and a driver chip 150 for processing or modulating optical / electrical signals involving a 4-channel CWDM optical transmit / receive path, or to support the functions of a replicated TIA chip 140' and a replicated driver chip 150' for processing or modulating optical / electrical signals involving a replicated 4-channel CWDM transmit / receive path. Furthermore, a microcontroller chip 2040 is also flip-chip mounted adjacent to the replicated DSP chip 2030' onto the submodule substrate 2300A and configured in the electrical interface block to support the operation of the DSP chip or the replicated DSP chip, as well as the operation of the SiPho chip. (Reference) Figure 7 A DSP chip 2030 (2030') or a microcontroller chip 2040 is mounted to the front side of the submodule substrate 2300A via multiple conductive bonding bumps 2108. Optionally, the submodule substrate 2300A also provides its bottom side for mounting additional functional chips to more effectively utilize the substrate to enhance the performance of the optical engine. For example, an ASIC chip 2050 for analog control of the laser and modulator is mounted on the bottom side of the submodule substrate 2300A via multiple bumps 2109 based on through-substrate vias.

[0049] refer to Figure 5 and Figure 6 The sub-assembly 3000A of the in-package optical engine 3000 is received or disposed within the socket frame member 3010 from its top side. An insertion plate 3040 is configured to be disposed between the bottom sides of the four sub-module substrates (e.g., 2300A) of the sub-assembly 3000A and the top side of the module substrate 3050. Optionally, the four sub-module substrates 2300A to 2300D (see...) Figure 6The module substrate 3050 can be considered as a common substrate. Optionally, the module substrate 3050 is configured as a line card including associated electrical connection circuitry to the host in a printed circuit board (PCB). Optionally, the module substrate 3050 itself is part of a larger line card. The PCB associated with the module substrate 3050 is configured with an integrated circuit having a line interface connected to four sub-components of the optoelectronic module via four sets of conductive bump contacts, and is configured as a line card having a host interface for connecting the multi-channel optical engine to a data center and an external power interface for accessing an external power supply. Optionally, the insertion board 3040 includes four sets of patterned through-substrate vias (TSVs) (e.g., 3044A) designed to couple to the bottom sides of the four sub-module substrates 2300A to 2300D of the four optoelectronic modules 2000A to 2000D, respectively.

[0050] Optionally, the insert plate 3040 is a passive inserter with four quadrant grids of conductor-filled through-substrate via (TSV) bumps, each quadrant grid formed on a quadrant region of the insert plate projected onto four sub-module substrates. For example, the quadrant grids of TSV bump 3044A are designed to form an electrical connection between direct bonding interconnect (DBI) contacts 3052A in corresponding quadrant regions of sub-module substrate 2300A and module substrate 3050. Optionally, each quadrant grid of the TSV bump (e.g., 3044A) is configured to surround a quadrant hollow region (e.g., 3042A) of the insert plate 3040 for mounting an optional ASIC chip (e.g., ASIC) behind the sub-module substrate (e.g., 2300A). Figure 7 The space generated in 2050).

[0051] Optionally, the insertion board 3040 is an active insertion device that includes a four-quadrant grid of TSV bumps for connecting I / O and power supplies, and provides an active area for embedded circuit devices to pass electrical signals using a buffer between two DBI contacts. Optionally, the insertion board 3040 is a 2.5D silicon insertion device. Optionally, the insertion board 3040 is a 3D silicon insertion device.

[0052] refer to Figure 5The module substrate 3050 includes a plurality of alignment vias 3051 that align with similar alignment vias 3041 in the insert plate 3040 and similar alignment vias 3011 in the socket frame member 3010. The backplane member 3060 includes alignment pins 3061 configured to pass through the alignment vias 3051, 3041, and 3011 to properly stack these component members. The module substrate 3050 also has a plurality of through-holes 3053 that allow compression pins 3030 to pass through to lock all portions of the package assembly 5000 with the backplane member 3060. The backplane member 3060 includes a plurality of open window regions (e.g., 3062A) designed to provide space for mounting additional chips on the rear of the module substrate 3050. Optionally, these window regions provide improved thermal conductivity for the package assembly 5000. The backplate component 3060 has a plurality of threaded holes 3063, which allow corresponding compression pins 3030 with threaded heads to lock in the plurality of threaded holes 3063, thereby enabling the encapsulation assembly 5000 to be tightly assembled.

Claims

1. A light engine, comprising: The first substrate (2300A) has a first surface and a second surface opposite to the first surface. The first substrate includes a first through substrate via extending between the first surface and the second surface, and also includes a first integrated circuit mounted on the second surface, the first integrated circuit being connected to the first through substrate via. as well as A silicon photonic substrate (100), separate from a first substrate, has a third surface and a fourth surface opposite to the third surface, the fourth surface facing the first surface of the first substrate. The silicon photonic substrate includes a second through-hole extending between the third surface and the fourth surface and connected to the first through-hole of the first substrate. The silicon photonic substrate also includes a plurality of optical devices and a plurality of integrated circuit devices mounted on the third surface and connected to the second through-hole. The plurality of optical devices include a plurality of laser chips (110), and The plurality of integrated circuit devices include a plurality of laser drivers (150) and a plurality of transimpedance amplifiers (140) coupled to the laser chip via the second through-substrate via. The first through-substrate via and the second through-substrate via are disposed on the first substrate and the silicon photonic substrate, and are configured to integrate the plurality of optical devices and the plurality of integrated circuit devices on the silicon photonic substrate to minimize the corresponding length of the electrical connection between the first integrated circuit mounted on the first substrate and the plurality of optical devices and the plurality of integrated circuit devices mounted on the silicon photonic substrate.

2. The optical engine of claim 1 further includes a plurality of digital signal processors (DSPs) (2030, 2030') mounted on the first surface of the first substrate, wherein the DSPs are coupled to the plurality of laser chips and the plurality of integrated circuit devices via the first through-substrate via and the second through-substrate via, through electrical connections between the plurality of optical devices and the plurality of integrated circuit devices mounted on the silicon photonic substrate and the plurality of digital signal processors mounted on the first substrate via the first through-substrate via and the second through-substrate via.

3. The optical engine of claim 1 further includes a microcontroller (2040) mounted on the first surface of the first substrate and connected to the first through-substrate via, the microcontroller being configured to control the plurality of optical devices and the plurality of integrated circuit devices mounted on the silicon photonic substrate via electrical connections from the microcontroller through the first through-substrate via and the second through-substrate via to the plurality of optical devices and the plurality of integrated circuits.

4. An integrated circuit assembly, comprising: Multiple optical engines (2000A-2000D), each of the multiple optical engines comprising: A first substrate (2300A-2300D) has a first surface and a second surface opposite to the first surface. The first substrate includes a first through-hole extending between the first surface and the second surface, and further includes a first integrated circuit mounted on the second surface, the first integrated circuit being connected to the first through-hole. A silicon photonic substrate (100) has a third surface and a fourth surface opposite to the third surface, the fourth surface facing the first surface of a first substrate. The silicon photonic substrate includes a second through-hole extending between the third surface and the fourth surface and connected to the first through-hole of the first substrate. The silicon photonic substrate also includes a plurality of optical devices and a plurality of integrated circuit devices mounted on the third surface and connected to the second through-hole. An inserter (3040) having a fifth surface and a sixth surface opposite to the fifth surface and including a plurality of sets of through-substrate vias, each set of through-substrate vias being defined by a plurality of through-substrate vias extending between the fifth surface and the sixth surface, wherein a plurality of optical engines are mounted on the inserter such that a second surface of a first substrate faces the fifth surface of the inserter, and a second through-substrate via of each of the plurality of optical engines is connected to a through-substrate via of a respective set of the plurality of sets of through-substrate vias of the inserter; and The second substrate (3050) has multiple sets of electrical contacts for a corresponding set of through-board vias connected to the inserter.

5. The integrated circuit assembly of claim 4, wherein the inserter includes a plurality of openings configured to provide mounting of the first integrated circuit on the first substrate of a respective optical engine among the plurality of optical engines, the respective optical engine being physically and electrically close to the plurality of optical devices and the plurality of integrated circuit devices mounted on the silicon photonic substrate.

6. The integrated circuit assembly of claim 5, wherein the plurality of through-substrate vias are respectively arranged around the plurality of openings, and wherein the plurality of electrical contacts are arranged on the second substrate to align with corresponding through-substrate vias among the plurality of through-substrate vias of the inserter.

7. The integrated circuit assembly of claim 4 further includes a heat sink (3020, 3021) in thermal contact with the plurality of optical engines to remove heat dissipated by the plurality of optical engines.

8. The integrated circuit assembly of claim 4, further comprising a backplane (3060) on a surface of the second substrate opposite to the surface having the plurality of electrical contacts, the backplane having a plurality of windows (3062A-3062D) configured to improve the thermal conductivity of the integrated circuit assembly.

9. The integrated circuit assembly of claim 4, further comprising a backplane mounted on the second substrate, the backplane having a plurality of windows configured to provide additional circuitry on a surface of the second substrate opposite to a surface having the plurality of electrical contacts.

10. The integrated circuit assembly of claim 4, further comprising: A frame (3010) surrounds the plurality of light engines, the frame having a plurality of windows, each of the plurality of windows being configured to surround a corresponding light engine among the plurality of light engines; as well as A backplate mounted on the second substrate, wherein the inserter and the backplate include a plurality of alignment pins passing through corresponding holes in the second substrate, the inserter and the frame, and configured to align the second through-board vias of the plurality of optical engines, the sets of through-board vias of the inserter and the sets of electrical contacts of the second substrate.

11. The integrated circuit assembly of claim 10, further comprising: A heat sink is mounted on the plurality of optical engines; as well as Multiple compression pins pass through i) corresponding through holes in the heat sink, ii) corresponding cutouts in each of the frame and the insert, and iii) corresponding through holes in the second substrate, the multiple compression pins being configured to lock into corresponding threaded holes in the back plate.

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