Memory system

Abstract

A memory system that suppresses a decrease in reliability is provided. A memory system of an embodiment is provided with a nonvolatile memory including a first block including a plurality of memory cells, and a memory controller that performs an erase process in a sub-block unit for data stored in the nonvolatile memory. The first block has a first sub-block including first memory cells and a second sub-block including second memory cells. The second memory cells are connected in series to the first memory cells, or are connected in parallel to the first memory cells to the same bit line. The memory controller is configured to perform, in a case where a first value corresponding to the first sub-block reaches a first threshold value, a process of reading out first data from the first sub-block, performing error correction processing for the first data read out from the first sub-block, and writing the first data for which the error correction processing has been performed into the nonvolatile memory.

Description

[0001] Related applications

[0002] This application enjoys priority to Japanese Patent Application No. 2022-079428 (filed on May 13, 2022). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation involves a memory system. Background Technology

[0004] A memory system is known to include NAND flash memory as non-volatile memory and a memory controller that controls the non-volatile memory. The memory controller writes data to the non-volatile memory according to a request from the host. Summary of the Invention

[0005] Provides a memory system that suppresses the reduction in reliability.

[0006] The memory system of the embodiment includes a non-volatile memory and a memory controller. The non-volatile memory has a first block containing a plurality of memory cells. The first block has a first sub-block containing first memory cells and a second sub-block containing second memory cells. The second memory cells are connected in series with the first memory cells or connected in parallel with the first memory cells on the same bit line. The memory controller performs sub-block-level erasure processing on data stored in the non-volatile memory. The memory controller is configured to perform the following processing when a first value corresponding to the first sub-block reaches a first threshold: read first data from the first sub-block, perform error correction processing on the first data read from the first sub-block, and write the first data with the error correction processing performed into the non-volatile memory. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of the information processing system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating an example of a signal used in the memory bus of the first embodiment.

[0009] Figure 3 This is a block diagram illustrating an example of the memory configuration of the non-volatile memory in the first embodiment.

[0010] Figure 4 This is a circuit diagram illustrating an example of the circuit configuration of the non-volatile memory in the first embodiment.

[0011] Figure 5This is a top view showing an example of the planar layout of the blocks of the non-volatile memory in the first embodiment.

[0012] Figure 6 This is an example of the cross-sectional structure of a block possessed by the non-volatile memory of the first embodiment, along... Figure 5 A cross-sectional view of the VI-VI line.

[0013] Figure 7 This is an example of a cross-sectional structure of the memory cylinders provided in the first embodiment of the non-volatile memory, along... Figure 6 A cross-sectional view of line VII-VII.

[0014] Figure 8 This is a diagram illustrating a first example of the erase process for sub-block units in the memory system of the first embodiment.

[0015] Figure 9 This is a diagram illustrating a second example of the erase process for sub-block units in the memory system of the first embodiment.

[0016] Figure 10 This is a flowchart illustrating an example of a reliability determination process based on the USBD (Unselected Sub-Block Disturb) quantity in a memory system according to the first embodiment.

[0017] Figure 11 This is a flowchart illustrating an example of a reliability determination process based on fatigue quantity in a memory system according to the second embodiment.

[0018] Figure 12 This is a flowchart illustrating an example of a fatigue-based reliability determination process in a memory system according to the third embodiment.

[0019] Explanation of reference numerals in the attached figures

[0020] 1…Information Processing System

[0021] 2… host

[0022] 3…Memory System

[0023] 10…Non-volatile memory

[0024] 11…System Area

[0025] 12…User Area

[0026] 20…Memory Controller

[0027] 21…Control Circuit

[0028] 22…Host Interface Circuit

[0029] 23…ECC circuit

[0030] 24… Memory Interface Circuit

[0031] 25… counter

[0032] 50, 51, 52, 53, 54, 55… Conductor layers

[0033] 60…core membrane

[0034] 61… Semiconductor film

[0035] 62…Laminated film

[0036] 63…Tunnel insulation film

[0037] 64…charge accumulation film

[0038] 65…barrier insulating film Detailed Implementation

[0039] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and configuration will be labeled with the same reference numerals as in the accompanying drawings.

[0040] 1. First Implementation Method

[0041] 1.1 Composition

[0042] 1.1.1 Information Processing System

[0043] The configuration of the information processing system according to the first embodiment will be described.

[0044] Figure 1 This is a block diagram illustrating the configuration of the information processing system according to the first embodiment. For example... Figure 1 As shown, the information processing system 1 includes a host 2 and a memory system 3.

[0045] Host 2 is a data processing device that uses memory system 3 to process data. Host 2 is, for example, a personal computer or a server in a data center.

[0046] Memory system 3 is a storage device configured to be connected to host computer 2. Memory system 3 is, for example, an SD card. TM Memory systems include memory cards like memory cards, UFS (Universal Flash Storage), and SSDs (Solid State Drives). The memory system 3 performs data write, read, and erase operations based on requests from the host 2. The memory system 3 can also perform write, read, and erase operations internally.

[0047] 1.1.2 Memory System

[0048] The internal structure of the memory system in the first embodiment will be described.

[0049] The memory system 3 includes a non-volatile memory 10 and a memory controller 20.

[0050] The non-volatile memory 10 is, for example, NAND flash memory. The non-volatile memory 10 contains multiple blocks BLK (BLK0 to BLKn). Each BLK contains multiple sub-blocks SBLK (SBLK0 to SBLKm). m and n are integers greater than or equal to 1. Each sub-block SBLK contains multiple memory cells. Each memory cell non-volatilely stores data. The blocks BLK and sub-blocks SBLK are, for example, the data erasure units in an erasure process. Hereinafter, the erasure process using blocks BLK as the erasure unit will also be referred to as the block-unit erasure process. The erasure process using sub-blocks SBLK as the erasure unit will also be referred to as the sub-block-unit erasure process. For ease of explanation, the case where a block BLK contains two sub-blocks SBLK0 and SBLK1 (the case where m = 1) will be described below.

[0051] The memory controller 20 includes, for example, an integrated circuit such as a System-on-a-Chip (SoC). The memory controller 20 controls the non-volatile memory 10 based on requests from the host 2.

[0052] Specifically, for example, the memory controller 20 writes write data to the non-volatile memory 10 based on a write request from the host 2. Additionally, the memory controller 20 reads read data from the non-volatile memory 10 based on a read request from the host 2. Furthermore, the memory controller 20 sends data based on the read data to the host 2.

[0053] 1.1.3 Memory Controller

[0054] Next, continue to refer to Figure 1 The internal structure of the memory controller 20 will be described below. The memory controller 20 includes a control circuit 21, a host interface circuit (host I / F) 22, an ECC (Error Correction and Check) circuit 23, a memory interface circuit (memory I / F) 24, and multiple counters 25. The functions of each part 21 to 25 of the memory controller 20 described below can be implemented by dedicated hardware, a processor executing a program, or any combination thereof.

[0055] The control circuit 21 is a circuit that controls the memory controller 20 as a whole. The control circuit 21 includes, for example, a processor such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory).

[0056] The host interface circuit 22 is responsible for communication between the memory controller 20 and the host 2. The host interface circuit 22 is connected to the host 2 via the host bus HB. The host bus HB, for example, is based on an SD card... TM Interface, SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)) or PCIe TM (Peripheral Component Interconnect express).

[0057] ECC circuit 23 performs error detection and correction processing related to the data stored in non-volatile memory 10. Specifically, during data writing, ECC circuit 23 assigns error correction codes to the written data. During data reading, ECC circuit 23 decodes the read data and detects the presence or absence of fault bits. A fault bit is a bit in the data read from a memory cell (containing bits of 1 or higher) that differs from the data written to that memory cell. Furthermore, when a fault bit is detected, ECC circuit 23 determines the location of the fault bit and corrects the error.

[0058] The memory interface circuit 24 is responsible for communication between the non-volatile memory 10 and the memory controller 20. The memory interface circuit 24 is connected to the non-volatile memory 10 via the memory bus MB. The memory bus MB is, for example, based on an SDR (single data rate) interface, a dual DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0059] Each of the multiple counters 25 includes, for example, a register. The number of counters 25 corresponds, for example, to the number of sub-blocks SBLK within the non-volatile memory 10. Each counter 25 stores a count value according to an instruction from the control circuit 21. Each counter 25 can also be an incrementing counter. In the case of an incrementing counter, each counter 25 counts up (increments) the count value according to an instruction from the control circuit 21. Each counter 25 can also be a decrementing counter. In the case of a decrementing counter, each counter 25 counts down (decreases) the count value according to an instruction from the control circuit 21. Each counter 25 resets its count value to an initial value according to an instruction from the control circuit 21. The initial value can be set to any value. Specifically, in the case of an incrementing counter, the initial value can be set to 0. In the case of a decrementing counter, the initial value can be set to a positive value.

[0060] 1.1.4 Memory Bus

[0061] Next, an example of the signals exchanged between the non-volatile memory 10 and the memory controller 20 will be described. Figure 2 This is a block diagram illustrating an example of a signal used in the memory bus of the first embodiment.

[0062] Signals used in the memory bus (MB) include, for example, the chip enable signal CE-, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WE-, the read enable signal RE-, the write protect signal WP-, the ready / busy signal RB-, and input / output (I / O) signals. In this specification, a "-" at the end of a signal name indicates that the signal is asserted to be at a "L (Low)" level.

[0063] The chip enable signal CE is used to enable the non-volatile memory 10.

[0064] The instruction latch enable signal CLE and the address latch enable signal ALE are signals that notify the non-volatile memory 10 that the input signals I / O to the non-volatile memory 10 are for instructions and addresses, respectively.

[0065] The write enable signal WE is a signal used to enable the non-volatile memory 10 to acquire input signal I / O.

[0066] The read enable signal RE is used to read the output signal I / O from the non-volatile memory 10.

[0067] The write protection signal WP is a signal used to indicate to the non-volatile memory 10 that writing and erasing of data is prohibited.

[0068] The Ready-Busy signal RB- indicates whether the non-volatile memory 10 is in a ready or busy state. A ready state means the non-volatile memory 10 can receive commands from the memory controller 20. A busy state means the non-volatile memory 10 cannot receive commands from the memory controller 20. The "L" level of the Ready-Busy signal RB- indicates a busy state.

[0069] Input / output (I / O) signals are, for example, 8-bit signals. I / O signals are entities that transmit and receive data between the non-volatile memory 10 and the memory controller 20. I / O signals include instructions, addresses, and data written and read.

[0070] 1.1.5 Non-volatile memory

[0071] Next, the configuration of the non-volatile memory 10 will be explained.

[0072] 1.1.5.1 Memory Configuration

[0073] Figure 3 This is a block diagram illustrating an example of the memory configuration of the non-volatile memory in the first embodiment. The non-volatile memory 10 includes, for example, a system region 11 and a user region 12.

[0074] System area 11 is a memory area that restricts access from host 2. System area 11 contains multiple sub-blocks SBLK. Specifically, for example, system area 11 contains sub-blocks SBLK that are allocated in a number proportional to the memory capacity of non-volatile memory 10, and sub-blocks SBLK that are allocated in a certain number independent of the memory capacity of non-volatile memory 10. As an example of sub-blocks SBLK that are allocated in a number proportional to the memory capacity of non-volatile memory 10, a sub-block SBLK for storing a LUT (Look-Up Table) representing the correspondence between logical addresses and physical addresses can be listed. As examples of sub-blocks SBLK that are allocated in a certain number independent of the memory capacity of non-volatile memory 10, sub-blocks SBLK for storing firmware, sub-blocks SBLK for storing management data, sub-blocks SBLK for saving data in memory controller 20 when power is off, and sub-blocks SBLK provided as write destinations for LUTs among the sub-blocks SBLK for storing LUTs can be listed.

[0075] User area 12 is a memory area used to store write data from host 2. User area 12 contains multiple sub-block SBLKs. User area 12 may also contain sub-block SBLKs for over-provisioning. In user area 12, for example, all sub-block SBLKs in the non-volatile memory 10, except for the sub-block SBLKs allocated to system area 11, may be allocated. Valid data is stored, for example, in the sub-block SBLKs in user area 12. In addition, user area 12 contains sub-block SBLKs allocated in a number proportional to the memory capacity of non-volatile memory 10, and sub-block SBLKs allocated in a certain number independent of the memory capacity of non-volatile memory 10. Examples of sub-block SBLKs allocated in a certain number independent of the memory capacity of non-volatile memory 10 include free block BLKs stored for performance stabilization, erased block BLKs, and block BLKs provided as write destinations.

[0076] In addition, each sub-block SBLK is dynamically allocated to system region 11 and user region 12. That is, a sub-block SBLK allocated to system region 11 can be re-allocated to user region 12. A sub-block SBLK allocated to user region 12 can be re-allocated to system region 11.

[0077] 1.1.5.2 Circuit Configuration

[0078] Figure 4 This is a circuit diagram illustrating an example of the circuit configuration of the non-volatile memory in the first embodiment. Figure 4 As an example, the structure of a block BLK is shown. A block BLK, for example, contains four string units SU0 to SU3. Furthermore, in... Figure 4 In the diagram, the configurations of the string units SU2 and SU3 are shown in a simplified manner.

[0079] Each string cell SU contains multiple NAND strings NS that are associated with bit lines BL0 to BLk (where k is an integer greater than or equal to 1). Each NAND string NS contains, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2.

[0080] The memory cell transistor MT is a transistor containing a charge accumulation layer. The memory cell transistor MT non-volatilely stores data based on the amount of charge accumulated in the charge accumulation layer. Selection transistors ST1 and ST2 are used to select the serial cell SU for various processing operations.

[0081] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. A selection transistor ST1 is connected between one end of the series-connected memory cell transistors MT0 to MT7 and the associated bit line BL. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source line SL is connected to the source of selection transistor ST2.

[0082] Within the same BLK, the gates of the multiple selection transistors ST1 contained in the serial cells SU0 to SU3 are each connected to the select gate lines SGD0 to SGD3. The control gates of the multiple memory cell transistors MT0 to MT7 are each connected to the word lines WL0 to WL7. The gates of the multiple selection transistors ST2 are each connected to the select gate line SGS.

[0083] Bit lines BL0 to BLk are shared by multiple blocks BLK0 to BLKn. NAND strings NS corresponding to the same column address are connected to the same bit line BL. Word lines WL0 to WL7 are respectively located in blocks BLK0 to BLKn. Source line SL, for example, is shared by multiple blocks BLK.

[0084] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string cell SU is also called a single cell CU. A single cell CU is used, for example, as a unit for writing data. The storage capacity of a single cell CU containing multiple memory cell transistors MT that each store 1 bit of data is defined as "1 page of data". That is, 1 page of data is a data area storing a string of 1-bit data with a number of columns corresponding to the number of memory cell transistors MT within the single cell CU. 1 page of data is used, for example, as a unit for reading data. A single cell CU may have a storage capacity of 2 pages or more, depending on the number of bits of data stored in the memory cell transistors MT. Write processing is classified into multiple write modes corresponding to the number of bits of data written to the memory cell transistors MT. For example, a write mode that writes 1 bit of data is also called SLC (Single Level Cell) mode. A write mode that writes 2 bits of data is also called MLC (Multi Level Cell) mode. A write mode that writes 3 bits of data is also called TLC (Triple Level Cell) mode. A write mode that writes 4 bits of data is also called QLC (Quadruple Level Cell) mode.

[0085] In a block BLK with the circuitry described above, multiple memory cell transistors MT are assigned to one of multiple sub-blocks SBLK0 to SBLKm. Specifically, all memory cell transistors MT in a sub-block SBLK of memory cell transistors MT0 to MT7 within a NAND string NS are connected in series without being connected via memory cell transistors in other sub-blocks SBLK.

[0086] exist Figure 4 The example illustrates a case where multiple memory cell transistors MT within block BLK are contained within either sub-block SBLK0 or SBLK1. In this case, the multiple memory cell transistors MT connected to word lines WL0 to WL3 are contained within sub-block SBLK0. The multiple memory cell transistors MT connected to word lines WL4 to WL7 are contained within sub-block SBLK1. In other words, the memory string containing memory cell transistors MT0 to MT3 in the NAND string NS is contained within sub-block SBLK0. The memory string containing memory cell transistors MT4 to MT7 in the NAND string NS is contained within sub-block SBLK1.

[0087] Furthermore, the circuit configuration of the block BLK described above is merely an example and is not limited to it. For example, the number of block BLKs contained in the non-volatile memory 10 can be designed to be any number. The number of sub-blocks SBLKs contained in each block BLK can be designed to be any number. The number of string cells SU contained in each block BLK can be designed to be any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 contained in each NAND string NS can each be designed to be any number.

[0088] 1.1.5.3 Floor Plan

[0089] The following describes an example of the construction of a block BLK in the non-volatile memory 10. In the accompanying drawings, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate used to form the block BLK.

[0090] In the top view, shading lines are appropriately added to facilitate observation of the accompanying drawings. The shading lines added to the top view are not necessarily related to the raw materials or properties of the constituent elements to which the shading lines are added. In the sectional view, the schematic diagrams of the constituent elements are appropriately omitted to facilitate observation of the accompanying drawings.

[0091] Figure 5 This is a top view showing an example of the planar layout of the blocks included in the non-volatile memory of the first embodiment. Figure 5The diagram shows a portion of a block BLK (i.e., string units SU0 to SU3) and multiple bit lines BL, two components SLT, and three components SHE corresponding to that portion of the block BLK.

[0092] Each component SLT is, for example, a plate-shaped component extending in the XZ plane. Each component SLT includes a contact LI and a spacer SP. The contact LI is a plate-shaped conductor extending in the XZ plane. The spacer SP is an insulator located on the Y-direction side of the contact LI. The contact LI is surrounded by the spacer SP when viewed from the Z-direction. Two components SLT are arranged in the Y-direction such that they sandwich a block BLK.

[0093] Each component SHE is, for example, a plate-shaped insulator extended on the XZ plane. The three components SHE are arranged along the Y direction between the two components SLT.

[0094] The block BLK contains stacked wiring (LS), multiple memory pillars (MP), and multiple contact elements (CV).

[0095] A stacked wiring array (LS) is a structure comprising multiple conductive layers that are separated from each other in the Z direction. The multiple conductive layers in the LS function, for example, as source lines (SL), word lines (WL), and select gate lines (SGD and SGS). The conductive layers in the LS that function as word lines (WL) and select gate lines (SGD and SGS) are disconnected by each component (SLT). The conductive layer in the LS that functions as the select gate line (SGD) is disconnected by each component (SHE).

[0096] Each memory column (MP) is a columnar structure surrounded by stacked wiring (LS) when viewed along the Z direction. Each memory column (MP) functions, for example, as a NAND string (NS). Multiple memory columns (MPs) are arranged, for example, in a staggered arrangement of 19 columns in the region between adjacent components (SLTs). Furthermore, for example, counting from the top of the paper, the memory columns (MPs) in the 5th, 10th, and 15th columns each overlap with a component (SHE).

[0097] Multiple bit lines BL extend in the Y direction and are arranged in the X direction. Each bit line BL in each string cell SU is configured to overlap with at least one memory column MP. Figure 5 The example shows a case where two bit lines BL are configured to overlap with a memory cylinder MP. One of the multiple bit lines BL overlapping the memory cylinder MP is electrically connected to the corresponding memory cylinder MP via a contact CV.

[0098] For example, the contact CV between the memory cylinder MP and the bit line BL that contacts the component SHE is omitted. In other words, the contact CV between the memory cylinder MP and the bit line BL that are connected to two different select gate lines SGD is omitted.

[0099] The planar layout described above is repeated in the Y direction. Furthermore, each region divided by the component SLT corresponds to a block BLK. Additionally, each region divided by either the component SLT or SHE corresponds to a string unit SU.

[0100] Furthermore, the number and configuration of memory cylinders (MP) and components (SHE) between adjacent SLTs are not limited to the use of Figure 5 The configuration described is not fixed and can be modified as appropriate. The number of bit lines BL overlapping with each memory cylinder MP can be designed to be arbitrary.

[0101] 1.1.5.4 Cross-sectional structure

[0102] Figure 6 This is an example of the cross-sectional structure of a block possessed by the non-volatile memory of the first embodiment, along... Figure 5 A cross-sectional view of the VI-VI line. (See attached image.) Figure 6 As shown, the block BLK also includes conductive layers 50-55.

[0103] The conductive layer 50 is, for example, a plate-shaped conductor extending in the XY plane. The conductive layer 50 is used as a p-type well region. The conductive layer 50, for example, contains phosphorus-doped silicon.

[0104] On the upper surface of the conductor layer 50, a conductor layer 51 is disposed with respect to an insulating layer (not shown). The conductor layer 51 is, for example, a plate-shaped conductor extending in the XY plane. The conductor layer 51 is used as the select gate line SGS. The conductor layer 51 contains, for example, tungsten.

[0105] An insulating layer (not shown) and a conductive layer 52 are alternately stacked on the upper surface of the conductive layer 51. The conductive layer 52 is, for example, a plate-shaped conductor extending in the XY plane. The stacked conductive layers 52 are used sequentially as word lines WL0 to WL3 from the conductive layer 51 side. The conductive layer 52 contains, for example, tungsten.

[0106] An insulating layer (not shown) and a conductive layer 53 are alternately stacked on the upper surface of the uppermost conductive layer 52 (the topmost layer of conductive layers 52). The conductive layer 53 is, for example, a plate-shaped conductor extending in the XY plane. The stacked conductive layers 53, starting from the conductive layer 52 side, are sequentially used as word lines WL4 to WL7. The conductive layer 53 may contain, for example, tungsten.

[0107] On the upper surface of the uppermost conductive layer 53 (the very top of the conductive layers 53), a conductive layer 54 is disposed with an insulating layer (not shown) in between. The conductive layer 54 is, for example, a plate-shaped conductor extending in the XY plane. The conductive layer 54 is used as the select gate line (SGD). The conductive layer 54 contains, for example, tungsten.

[0108] On the upper surface of the conductive layer 54, a conductive layer 55 is disposed with respect to an insulating layer (not shown). The conductive layer 55 is, for example, a linear conductor extending along the Y direction. The conductive layer 55 is used as a bit line BL. That is, in the region not shown, multiple conductive layers 55 are arranged along the X direction. The conductive layer 55 contains, for example, copper.

[0109] Multiple memory pillars (MPs) are arranged to extend through conductor layers 51-54. Each memory pillar (MP) extends along the Z-direction. The bottom of each memory pillar (MP) reaches conductor layer 50. The portion where the memory pillar (MP) intersects with conductor layer 51 functions as a select transistor (ST2). The portion where the memory pillar (MP) intersects with either conductor layer 52 or conductor layer 53 functions as a memory cell transistor (MT). The portion where the memory pillar (MP) intersects with conductor layer 54 functions as a select transistor (ST1).

[0110] Each memory column (MP) includes, for example, a core film 60, a semiconductor film 61, and a laminated film 62. The core film 60 extends along the Z-direction. For example, the upper end of the core film 60 is located above the conductive layer 54. The lower end of the core film 60 is located below the conductive layer 51. The semiconductor film 61 covers the periphery of the core film 60. A portion of the semiconductor film 61 is in contact with the conductive layer 50. The laminated film 62 covers the sides and bottom of the semiconductor film 61, except for the portion where the semiconductor film 61 contacts the conductive layer 50. The core film 60 includes, for example, an insulator such as silicon oxide. The semiconductor film 61 includes, for example, silicon.

[0111] In addition, each memory cylinder MP includes an upper UMP and a lower LMP. The lower end of the upper UMP and the upper end of the lower LMP are located between the uppermost layer of the conductor layer 52 and the lowermost conductor layer 53 (the lowest layer of the conductor layers 53) among the plurality of conductor layers 53. The lower end of the upper UMP and the upper end of the lower LMP are in contact in a manner that makes the semiconductor film 61 continuous. The side surface of the lower LMP is not aligned with the extension line of the side surface of the upper UMP (offset). This offset between the side surface of the lower LMP and the extension line of the side surface of the upper UMP is generated in any cross section including the Z direction, and is not limited to... Figure 6 Within the YZ cross-section shown, the portion of the lower LMP containing multiple conductive layers 52 corresponds to sub-block SBLK0. The portion of the upper UMP containing multiple conductive layers 53 corresponds to sub-block SBLK1.

[0112] A columnar contact CV is disposed on the upper surface of the semiconductor film 61 within the memory column MP. In the illustrated area, in each cross-sectional area divided by components SLT and SHE, one contact CV corresponding to one of the two memory columns MP is shown. In memory columns MP that do not overlap with component SHE and are not connected to contact CV, in areas not shown, the corresponding contact CV is connected.

[0113] A conductive layer 55, i.e., a bit line BL, is connected to the upper surface of a contact CV. A conductive layer 55 is connected to a contact CV in each of the spaces defined by components SLT and SHE. That is, memory pillars MP located between adjacent components SLT and SHE and memory pillars MP located between two adjacent components SHE are electrically connected to the conductive layer 55.

[0114] Component SLT disconnects conductive layers 51-54. The upper end of component SLT is located above the upper end of memory cylinder MP. The lower end of contact LI is connected to conductive layer 50. Spacer SP is disposed between contact LI and conductive layers 51-54. That is, contact LI and conductive layers 51-54 are isolated and insulated by spacer SP. Contact LI can be used as part of source line SL.

[0115] The component SHE disconnects the conductive layer 54. The upper end of the component SHE is located above the upper end of the memory cylinder MP. The lower end of the component SHE is located between the uppermost layer of conductive layer 54 and conductive layer 53.

[0116] Figure 7 This is an example of a cross-sectional structure of the memory cylinders provided in the first embodiment of the non-volatile memory, along... Figure 6 A cross-sectional view of line VII-VII. More specifically, Figure 7 The cross-sectional structure of the memory pillar MP and the stacked wiring LS in the layer containing the conductor layer 52 is shown.

[0117] The laminated membrane 62 includes, for example, a tunnel insulating membrane 63, a charge accumulation membrane 64, and a barrier insulating membrane 65.

[0118] In the cross-section containing the conductive layer 52, the core film 60 is, for example, disposed in the central portion of the memory pillar MP. A semiconductor film 61 surrounds the sides of the core film 60. A tunnel insulating film 63 surrounds the sides of the semiconductor film 61. A charge accumulation film 64 surrounds the sides of the tunnel insulating film 63. A barrier insulating film 65 surrounds the sides of the charge accumulation film 64. The conductive layer 52 surrounds the sides of the barrier insulating film 65.

[0119] Semiconductor film 61 serves as the channel (current path) for memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Tunnel insulating film 63 and barrier insulating film 65 each contain, for example, silicon oxide. Charge accumulator film 64 has the function of accumulating charge. Charge accumulator film 64 contains, for example, silicon nitride. Thus, each memory pillar MP can function as a NAND string NS.

[0120] 1.2 Actions

[0121] Next, the operation of the memory system according to the first embodiment will be described.

[0122] 1.2.1 Erase Processing of Sub-block Units

[0123] Figure 8 This is a diagram illustrating a first example of the erase process for sub-block units in the memory system of the first embodiment. Figure 9 This is a diagram illustrating a second example of the erase process for sub-block units in the memory system of the first embodiment. Figure 8 as well as Figure 9 In the section on erasing sub-block units, examples of voltage applied to the NAND string NS are shown. The first example corresponds to the case where data stored in sub-block SBLK1 is maintained and data stored in sub-block SBLK0 is erased. The second example corresponds to the case where data stored in sub-block SBLK0 is maintained and data stored in sub-block SBLK1 is erased.

[0124] like Figure 8 as well as Figure 9 As shown, in either case, a voltage VERA is applied to the p-type well region. VERA is the erase voltage, for example, 20V. The gate lines SGS and SGD, as well as the bit line BL, are selected to be in a floating state.

[0125] While maintaining the data stored in sub-block SBLK1 and erasing the data stored in sub-block SBLK0, a voltage VSS is applied to word lines WL0 to WL3. Voltage VSS is ground voltage, for example, 0V. As a result, holes are injected into the charge accumulation film 64 in memory cell transistors MT0 to MT3, and the data is erased. On the other hand, word lines WL4 to WL7 are set to a floating state. Therefore, no holes are injected into memory cell transistors MT4 to MT7, and the data is maintained.

[0126] While maintaining the data stored in sub-block SBLK0 and erasing the data stored in sub-block SBLK1, word lines WL0 to WL3 are set to a floating state. Therefore, no holes are injected into memory cell transistors MT0 to MT3, and the data is maintained. On the other hand, a voltage VSS is applied to word lines WL4 to WL7. Therefore, holes are injected into memory cell transistors MT4 to MT7, and the data is erased.

[0127] The above actions are used to perform the erase process at the sub-block level.

[0128] Hereinafter, the SBLK of the object to be erased as a sub-block unit is also called the object sub-block SBLK. In addition, the SBLK of the object sub-block is also called the non-object sub-block SBLK.

[0129] 1.2.2 Reliability Judgment Processing

[0130] Erasing a sub-block unit of an object sub-block SBLK may cause fault bits to be generated in a portion of the data stored in non-object sub-block SBLKs within the block BLK containing the object sub-block SBLK. Similarly, writing to an object sub-block SBLK may cause fault bits to be generated in the data stored in non-object sub-block SBLKs within the block BLK containing the object sub-block SBLK. As an indicator of the extent of fault bit generation caused by erasing or writing to object sub-block SBLKs, the USBD (Unselected Sub-Block Disturb) quantity can be used, for example.

[0131] The USBD value represents the reliability of the data stored in the non-volatile memory 10. The lower the reliability of the data, the higher the USBD value. If faulty bits in the data are corrected through error correction processing, the USBD value can be reduced. The USBD value is estimated for each sub-block SBLK. Specifically, for example, the USBD value of a certain sub-block SBLK is estimated based on the count value of the counter 25 corresponding to that sub-block SBLK. The USBD value can also be the count value of the counter 25 itself. The USBD value can also be managed by the control circuit 21 as a value based on the count value of the counter 25.

[0132] Figure 10 This is a flowchart illustrating an example of a reliability determination process based on USBD quantities in a memory system according to the first embodiment.

[0133] If a sub-block unit erase or write operation has been performed on the target sub-block SBLK, then control circuit 21 determines the block BLK containing the target sub-block SBLK (S10). Alternatively, the start condition for step S10 can also be that a sub-block unit erase operation has been performed on the target sub-block SBLK. Or, the start condition for step S10 can also be that a sub-block unit write operation has been performed on the target sub-block SBLK.

[0134] For the block BLK determined in step S10, control circuit 21 performs a loop process based on variable x (S20). Variable x is an integer greater than or equal to 0. The loop process in step S20 begins when variable x is 0. During the loop process in step S20, variable x is incremented by 1 each time a repetition unit is executed. The loop process in step S20 ends when variable x exceeds m. The loop process in S20 includes steps S21 to S26 as repetition units.

[0135] Control circuit 21 determines whether the sub-block SBLKx within block BLK determined in step S10 is the target sub-block SBLK (S21).

[0136] If sub-block SBLKx is the target sub-block SBLK (S21: Yes), the control circuit 21 determines whether the process performed on the target sub-block SBLK when the reliability determination process begins is an erase process (S22).

[0137] If the process performed on the target sub-block SBLK during the reliability determination process is an erase process (S22: Yes), the control circuit 21 resets the USBD quantity corresponding to the sub-block SBLKx (S23). Specifically, the control circuit 21 resets the count value of the counter 25 corresponding to the sub-block SBLKx to its initial value. If the counter 25 is an incrementing counter, the control circuit 21 can also set the count value of the counter 25 to 0. If the counter 25 is a decrementing counter, the control circuit 21 can also set the count value of the counter 25 to the threshold Th1.

[0138] If sub-block SBLKx is not the target sub-block SBLK (S21: No), control circuit 21 increments the USBD value corresponding to sub-block SBLKx (S24). Specifically, if counter 25 is an incrementing counter, control circuit 21 increments the count value of counter 25 corresponding to sub-block SBLKx. If counter 25 is a decrementing counter, control circuit 21 decrements the count value of counter 25 corresponding to sub-block SBLKx.

[0139] Furthermore, the increment of the USBD quantity can also vary depending on whether the processing performed on the object subblock SBLK at the start of the reliability determination process is an erase or a write operation. For example, when the increment of the USBD quantity corresponding to the erase operation and the write operation are set to α and β respectively, it can be α > β. The relationship between α and β is not limited to the above example; it can also be β > α or α = β.

[0140] Furthermore, the increment of the USBD quantity corresponding to the write operation can also vary depending on the write mode. For example, when the write modes are SLC, MLC, TLC, and QLC, the increment of the USBD quantity can be set to β_S, β_M, β_T, and β_Q, respectively, which can be β_S < β_M < β_T < β_Q. The relationship between β_S, β_M, β_T, and β_Q is not limited to the above example; it can also be β_S > β_M > β_T > β_Q, or β_S = β_M = β_T = β_Q.

[0141] After step S24, control circuit 21 determines whether the USBD quantity corresponding to sub-block SBLKx is above threshold Th1 (S25). Furthermore, threshold Th1 can vary depending on the write mode applied to sub-block SBLKx. For example, when the write mode applied to sub-block SBLKx is SLC mode, MLC mode, TLC mode, and QLC mode, the threshold for the USBD quantity is set to Th1_S, Th1_M, Th1_T, and Th1_Q respectively, it can also be set to Th1_S > Th1_M > Th1_T > Th1_Q.

[0142] If the USBD quantity corresponding to sub-block SBLKx is above the threshold Th1 (S25: Yes), the control circuit 21 determines that the fault bit in the data stored in sub-block SBLKx is of a high degree. Specifically, the control circuit 21 schedules the refresh process of sub-block SBLKx (S26).

[0143] A refresh process is, for example, the process of restoring the data written to sub-block SBLKx from a state containing fault bits to a state where the fault bits have been corrected. As an example of a refresh process, the data written to sub-block SBLKx can be rewritten to the sub-block SBLKx whose data containing fault bits has been erased after being corrected by ECC circuit 23. Alternatively, as another example of a refresh process, the data written to sub-block SBLKx can also be written to other sub-blocks SBLK after being corrected by ECC circuit 23.

[0144] Furthermore, when counter 25 is an incrementing counter, control circuit 21 can also determine whether the count value of counter 25 is greater than or equal to threshold Th1 in the determination process of step S25, thereby determining whether the USBD quantity is greater than or equal to threshold Th1. When counter 25 is a decrementing counter, control circuit 21 can also determine whether the USBD quantity is greater than or equal to threshold Th1 by determining whether the count value of counter 25 is 0 in the determination process of step S25.

[0145] If the process performed on the object sub-block SBLK at the start of the reliability determination process is not an erase process (i.e., a write process) (S22: No), after the processing in step S26, or if the USBD quantity corresponding to the selected sub-block SBLK is less than the threshold Th1 (S25: No), the repetition unit of the loop processing in step S20 ends. Then, after incrementing the variable x, the control circuit 21 determines whether the variable x exceeds m. If the variable x is less than m, the repetition unit of the loop processing in step S20 is executed. If the variable x exceeds m, the loop processing in step S20 ends.

[0146] If the loop processing in step S20 ends, the reliability determination process ends (end).

[0147] Furthermore, after the reliability determination process, the memory controller 20 performs a refresh process on the sub-block SBLK that has been scheduled for refresh processing, for example, at a predetermined time interval. This refresh process can be performed synchronously with the reliability determination process or asynchronously.

[0148] 1.3 Effects of the first implementation method

[0149] According to the first embodiment, when the USBD quantity corresponding to sub-block SBLKx reaches the threshold Th1, the control circuit 21 schedules the refresh process for sub-block SBLKx. Therefore, through subsequent refresh processing, the data written to sub-block SBLKx can be restored to a state where the fault bits have been corrected. Thus, the reduction in the reliability of sub-block SBLKx can be suppressed.

[0150] Furthermore, the control circuit 21 resets the USBD value corresponding to the target sub-block SBLK based on the erase process of the target sub-block SBLK. This allows the reduction of fault bits in the target sub-block SBLK through the erase process to be reflected in the USBD value corresponding to the target sub-block SBLK.

[0151] Furthermore, the control circuit 21 increments the USBD value corresponding to the non-object sub-block SBLK within the block BLK containing the object sub-block SBLK based on the erase or write operation performed on the object sub-block SBLK. This allows the increase of the fault bit in the non-object sub-block SBLK due to the erase or write operation of the object sub-block SBLK to be reflected in the USBD value corresponding to that non-object sub-block SBLK.

[0152] Furthermore, when counter 25 is an incrementing counter, control circuit 21 schedules the refresh process of the sub-block SBLK corresponding to the count value when the count value reaches the threshold Th1. When counter 25 is a decrementing counter, control circuit 21 schedules the refresh process of the sub-block SBLK corresponding to the count value when the count value reaches 0. Therefore, regardless of whether counter 25 is an incrementing or decrementing counter, the USBD quantity can be evaluated based on the count value of counter 25.

[0153] 2. Second Implementation Method

[0154] Next, the memory system of the second embodiment will be described. The second embodiment differs from the first embodiment in suppressing the decrease in reliability caused by uneven fatigue among sub-blocks SBLK within the same BLK. Hereinafter, the configuration and operation that differ from the first embodiment will be mainly described. Configurations and operations that are equivalent to those of the first embodiment will be omitted as appropriate.

[0155] 2.1 Reliability Judgment Processing

[0156] The cycle of write and erase operations performed on the target sub-block SBLK causes fatigue in the target sub-block SBLK. Accumulated fatigue can lead to failure of the target sub-block SBLK. In the event of a failure of the target sub-block SBLK, non-target sub-block SBLKs within the block BLK containing the target sub-block SBLK may become unusable. Therefore, from the viewpoint of suppressing the degradation of the reliability of the non-volatile memory 10, it is desirable to reduce the unevenness of fatigue among sub-block SBLKs within the same block BLK. For example, fatigue level is used as an indicator to estimate the degree of accumulated fatigue of the target sub-block SBLK caused by the cycle of write and erase operations.

[0157] Fatigue level represents the irreversible degradation of the data retention capability of the non-volatile memory 10. Therefore, unlike USBD level, fatigue level, once increased, cannot be decreased. Fatigue level is estimated per sub-block SBLK. Specifically, for example, the fatigue level of a certain sub-block SBLK is estimated based on the count value of the counter 25 corresponding to that sub-block SBLK. The fatigue level can also be the count value of counter 25 itself. The fatigue level can also be managed by the control circuit 21 as a value based on the count value of counter 25.

[0158] Figure 11 This is a flowchart illustrating an example of reliability determination processing in a memory system according to the second embodiment.

[0159] If an erase process (start) is performed on the target sub-block SBLK, the control circuit 21 increments the fatigue value corresponding to the target sub-block SBLK (S30). Specifically, when the counter 25 is an incrementing counter, the control circuit 21 increments the count value of the counter 25 corresponding to the target sub-block SBLK. When the counter 25 is a decrementing counter, the control circuit 21 decrements the count value of the counter 25 corresponding to the target sub-block SBLK.

[0160] Control circuit 21 determines the block BLK (S31) that contains the object sub-block.

[0161] Control circuit 21 detects a representative value of the fatigue amount of sub-block SBLK within block BLK, determined in step S31 (S32). The representative value can be the maximum value of the fatigue amount of sub-block SBLK within block BLK, determined in step S31. Alternatively, the representative value can be the average value of the fatigue amount of sub-block SBLK within block BLK, determined in step S31. Furthermore, when counter 25 is an incrementing counter, the maximum fatigue amount corresponds to the maximum count value. When counter 25 is a decrementing counter, the maximum fatigue amount corresponds to the minimum count value.

[0162] Control circuit 21 performs a loop process (S40) based on variable x for the block BLK determined in process S31. Variable x is an integer greater than or equal to 0. The loop process in step S40 begins when variable x is 0. During the loop process in step S40, variable x is incremented by 1 each time a repetition unit is executed. The loop process in step S40 ends when variable x exceeds m. The loop process in S40 includes steps S41 and S42 as repetition units.

[0163] Control circuit 21 determines whether the difference between the representative value of the fatigue amount detected in step S32 and the fatigue amount corresponding to sub-block SBLKx is greater than or equal to threshold Th2 (S41). Threshold Th2 is, for example, a positive real number.

[0164] If the difference between the representative value of the fatigue amount and the fatigue amount corresponding to the sub-block SBLKx is greater than or equal to the threshold Th2 (S41: Yes), the control circuit 21 schedules the wear leveling process for the sub-block SBLKx (S42). The wear leveling process is, for example, the process of transferring the data written to the sub-block SBLKx to other sub-blocks SBLK.

[0165] As an example of lossy leveling, control circuit 21 can schedule compression processing that uses sub-block SBLKx as the compression source. Compression processing that uses sub-block SBLKx as the compression source is, for example, the process of writing data written to sub-block SBLKx to other sub-blocks SBLK that become compression destinations. Other sub-blocks SBLK are, for example, sub-blocks SBLK within a block BLK that contains the sub-block SBLKx that serves as the compression source. Other sub-blocks SBLK can also be sub-blocks SBLK within a block BLK that is different from the block BLK containing sub-block SBLKx.

[0166] Additionally, as another example of wear leveling, control circuit 21 can also exchange data written to sub-block SBLKx with data written to sub-block SBLK with a larger fatigue amount. For example, control circuit 21 can also designate sub-block SBLK with a fatigue amount that is the maximum value of the fatigue amount detected in step S32, or sub-block SBLK with a fatigue amount that is greater than or equal to the average value of the fatigue amounts detected in step S32, as sub-block SBLK with a larger fatigue amount.

[0167] After the processing in step S42, or if the difference between the representative value of the fatigue amount and the fatigue amount corresponding to the selected sub-block SBLK is less than the threshold Th2 (S41: No), the repetition unit of the loop processing in step S40 ends. Then, after incrementing the variable x, the control circuit 21 determines whether the variable x exceeds m. If the variable x is less than m, the repetition unit of the loop processing in step S40 is executed. If the variable x exceeds m, the loop processing in step S40 ends.

[0168] If the loop processing in step S40 ends, the reliability determination process ends (end).

[0169] In addition, after the reliability determination process, the memory controller 20 performs wear leveling processing, for example, at a predetermined time interval. This wear leveling processing can be performed synchronously with the reliability determination process or asynchronously.

[0170] 2.2 Effects of the Second Implementation Method

[0171] According to the second embodiment, when the difference between the fatigue value corresponding to the selected sub-block SBLK and the representative value among the fatigue values ​​of each sub-block SBLK within the block BLK containing sub-block SBLKx reaches a threshold Th2, the control circuit 21 schedules wear leveling processing for sub-block SBLKx. Therefore, through subsequent wear leveling processing, the frequency variation of the write and erase cycles performed on sub-block SBLKx can be reduced. Thus, the decrease in reliability of sub-block SBLKs with large fatigue values ​​can be suppressed.

[0172] In addition, it can be inferred that data with a longer retention period from writing to erasure is written to sub-blocks SBLK with lower fatigue levels. During wear leveling, this data with a longer retention period is transferred from the sub-blocks SBLK with lower fatigue levels to other sub-blocks SBLK. This allows for the writing of data with shorter retention periods to sub-blocks SBLK with lower fatigue levels. Therefore, it is expected to reduce the difference in fatigue levels between sub-blocks SBLK with lower fatigue levels and sub-blocks SBLK with higher fatigue levels. Consequently, it is possible to suppress the decrease in reliability of sub-blocks SBLK with higher fatigue levels.

[0173] Furthermore, the control circuit 21 increases the fatigue amount corresponding to the object sub-block SBLK according to the cycle of erasing and writing processes. Therefore, the fatigue effect of the erasing and writing processes on the object sub-block SBLK can be reflected in the fatigue amount corresponding to that object sub-block SBLK.

[0174] 3. Third Implementation Method

[0175] Next, the memory system according to the third embodiment will be described. In the third embodiment, the reliability reduction caused by uneven fatigue among sub-blocks SBLK contained in different block BLKs differs from that of the second embodiment. Hereinafter, the configuration and operation that differ from the second embodiment will be mainly described. Configurations and operations that are equivalent to those of the second embodiment will be omitted as appropriate.

[0176] 3.1 Reliability Assessment Processing

[0177] In the event of a failure in a target subblock SBLK, the number of subblock SBLKs within user area 12 used to store write data from host 2 decreases. Consequently, the number of erase and write cycles performed on each subblock SBLK may increase. Therefore, from the viewpoint of suppressing a decrease in the reliability of the non-volatile memory 10, it is desirable to reduce the unevenness of fatigue among subblock SBLKs contained in different block BLKs.

[0178] Figure 12This is a flowchart illustrating an example of reliability determination processing in a memory system according to the third embodiment.

[0179] If an erasure process (start) is performed on the object sub-block SBLK, the control circuit 21 increases the fatigue amount corresponding to the object sub-block SBLK (S50).

[0180] Control circuit 21 detects a representative value of the fatigue amount of sub-block SBLK in non-volatile memory 10 (S51). The representative value can be the maximum value of the fatigue amount of sub-block SBLK in non-volatile memory 10. The representative value can also be the average value of the fatigue amount of sub-block SBLK in non-volatile memory 10.

[0181] Control circuit 21 executes a first loop process (S60A) based on variable y for non-volatile memory 10. Variable y is an integer greater than or equal to 0. The first loop process in step S60A begins when variable y is 0. During the first loop process in step S60A, variable y is incremented by 1 each time a repetition unit is executed. The first loop process in step S60A ends when variable y exceeds n. The first loop process in step S60A includes a second loop process (S60B) based on variable x as a repetition unit. Variable x is an integer greater than or equal to 0. The second loop process in step S60B begins when variable x is 0. During the second loop process in step S60B, variable x is incremented by 1 each time a repetition unit is executed. The second loop process in step S60B ends when variable x exceeds m. The second loop process in step S60B includes steps S61 and S62 as repetition units.

[0182] Control circuit 21 determines whether the difference between the representative value of the fatigue amount detected in step S51 and the fatigue amount corresponding to the sub-block SBLKx within block BLKy is greater than or equal to the threshold Th2 (S61).

[0183] If the difference between the representative value of fatigue and the fatigue value corresponding to the sub-block SBLKx within block BLKy is greater than or equal to the threshold Th2 (S61: Yes), the control circuit 21 schedules the wear leveling process for the sub-block SBLKx within block BLKy (S62).

[0184] As an example of loss leveling, control circuit 21 can schedule compression processing where sub-blocks SBLKx within block BLKy are the compression source. In this case, other sub-blocks SBLK that become the compression destination are, for example, sub-blocks SBLK within a block BLK that is different from the block BLKy that serves as the compression source. These other sub-blocks SBLK can also be sub-blocks SBLK within block BLKy.

[0185] Additionally, as another example of wear leveling, control circuit 21 can also exchange data from sub-block SBLKx within the write block BLKy with data from sub-block SBLK with a larger fatigue amount. For example, control circuit 21 can also designate sub-block SBLK with a fatigue amount equal to the maximum value of the fatigue amount detected in step S51, or sub-block SBLK with a fatigue amount greater than or equal to the average value of the fatigue amounts detected in step S51, as sub-block SBLK with a larger fatigue amount.

[0186] After the processing in step S62, or if the difference between the representative value of the fatigue amount and the fatigue amount corresponding to the sub-block SBLKx within block BLKy is less than the threshold Th2 (S61: No), the repeating unit of the second loop processing in step S60B ends. Then, after incrementing the variable x, the control circuit 21 determines whether the variable x exceeds m. If the variable x is less than m, the repeating unit of the second loop processing in step S60B is repeated. If the variable x exceeds m, the second loop processing in step S60B (i.e., the repeating unit of the first loop processing in step S60A) ends. Then, after incrementing the variable y, the control circuit 21 determines whether the variable y exceeds n. If the variable y is less than n, the repeating unit of the first loop processing in step S60A is executed. If the variable y exceeds n, the first loop processing in step S60A ends.

[0187] If the first cycle of step S60A is completed, the reliability determination process ends (end).

[0188] In addition, after the reliability determination process, the memory controller 20 performs wear leveling processing, for example, at a predetermined time interval. This wear leveling processing can be performed synchronously with the reliability determination process or asynchronously.

[0189] 3.2 Effects of the Third Implementation Method

[0190] According to the third embodiment, when the difference between the fatigue value corresponding to the sub-block SBLKx within block BLKy and the representative value among the fatigue values ​​corresponding to each sub-block SBLK in the non-volatile memory 10 reaches a threshold Th2, the control circuit 21 schedules wear leveling processing for the sub-block SBLKx within block BLKy. Therefore, through subsequent wear leveling processing, the frequency variation of the write and erase cycles performed on the sub-block SBLKx within block BLKy can be reduced. Thus, the decrease in reliability of sub-block SBLKs with large fatigue values ​​can be suppressed.

[0191] 4. Variations, etc.

[0192] The first, second, and third embodiments described above can be adapted in various ways.

[0193] In the first, second, and third embodiments described above, the lower LMP and upper UMP of the memory column MP are described as corresponding to sub-blocks SBLK0 and SBLK1, respectively, but this is not a limitation. For example, sub-blocks SBLK0 and SBLK1 may not correspond to the lower LMP and upper UMP of the memory column MP. Specifically, a block BLK containing memory columns MP that are not divided into lower LMP and upper UMP may also be divided into sub-blocks SBLK0 and SBLK1. Furthermore, when the memory column MP is divided into lower LMP and upper UMP, at a boundary different from the boundary of the lower LMP and upper UMP, the block BLK may also be divided into sub-blocks SBLK0 and SBLK1. Additionally, for example, sub-blocks SBLK0 and SBLK1 may correspond to portions of mutually different memory columns MP that are connected in parallel to the same bit line BL.

[0194] Furthermore, while the second and third embodiments described above illustrate an increase in fatigue amount based on the increase in the count value of counter 25, this is not a limitation. The increase in fatigue amount can also be calculated based on the temperature of the non-volatile memory 10 during the write and erase cycles. For example, the increase in fatigue amount when the temperature of the non-volatile memory 10 is higher during the write and erase cycles may be smaller than the increase in fatigue amount when the temperature of the non-volatile memory 10 is lower during the write and erase cycles.

[0195] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims.

Claims

1. A memory system, characterized in that, have: A non-volatile memory comprising multiple blocks, each block comprising multiple sub-blocks, and each sub-block comprising multiple memory cells; and The memory controller performs sub-block unit erase operations on the data stored in the non-volatile memory; The first block of the plurality of blocks comprises: a first sub-block containing a first memory unit; And a second sub-block containing a second memory cell, which is connected in series with the first memory cell or connected in parallel with the first memory cell on the same bit line; The memory controller is configured to write data stored in the first sub-block into a third sub-block other than the first sub-block when the difference between a fifth value representing the fatigue amount of the first sub-block and a sixth value representing the maximum fatigue amount of the sub-blocks among the plurality of blocks reaches a third threshold.

2. The memory system according to claim 1, characterized in that, The third sub-block is the sub-block in which the data has been erased.

3. The memory system according to claim 1, characterized in that, The third sub-block is the sub-block corresponding to the sixth value. The memory controller is configured to exchange data stored in the first sub-block and data stored in the third sub-block between the first sub-block and the third sub-block.

4. The memory system according to claim 1, characterized in that, The non-volatile memory includes: A first conductor layer and a second conductor layer arranged separately in a first direction; and The memory pillar intersects the first conductor layer and the second conductor layer in the first direction; The portion of the memory column that intersects with the first conductor layer functions as the first memory cell. The portion of the memory column that intersects with the second conductor layer functions as the second memory cell.

5. The memory system according to claim 4, characterized in that, The memory column comprises: a first portion, including a portion intersecting with the first conductive layer; and a second portion, including a portion intersecting with the second conductive layer; The extension lines of the side surface of the first portion and the side surface of the second portion are offset within a plane including the first direction.

6. The memory system according to claim 1, characterized in that, The third sub-block is a second block that is different from the first block among the plurality of blocks.

7. The memory system according to claim 1, characterized in that, The third sub-block is contained within the first block.

8. The memory system according to claim 1, characterized in that, The memory controller is configured to detect the sixth value based on the fatigue level of a sub-block among the plurality of blocks.

9. The memory system according to claim 1, characterized in that, The memory controller includes a first incrementing counter for managing the fifth value. The memory controller is configured to increment the value of the first incrementing counter according to the erasure process of the data stored in the first sub-block.

10. The memory system according to claim 9, characterized in that, The increment of the first increment counter when the temperature during the erase process of the data stored in the first sub-block is a first temperature is less than the increment of the first increment counter when the temperature during the erase process of the data stored in the first sub-block is a second temperature lower than the first temperature.

11. The memory system according to claim 9, characterized in that, The memory controller is configured to increment the value of the first incrementing counter according to the data writing process to the first sub-block.

12. The memory system according to claim 11, characterized in that, The increment of the first increment counter when the temperature during the write process of data to the first sub-block is a first temperature is less than the increment of the first increment counter when the temperature during the write process of data to the first sub-block is a second temperature lower than the first temperature.

13. The memory system according to claim 1, characterized in that, The memory controller includes a first decrementing counter for managing the fifth value. The memory controller is configured to decrement the value of the first decrementing counter according to the erasure process of the data stored in the first sub-block.

14. The memory system according to claim 13, characterized in that, The memory controller is configured to decrement the value of the first decrementing counter by performing data writing processing on the first sub-block.

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