A method and apparatus for unifying clock frequencies

Abstract

The application provides a method and device for unifying clock frequency, relates to the technical field of chips, and can unify the frequency of SerDes and DRAM when DRAM is expanded by using a serial interface, so that the system works in a synchronous clock domain and low delay is achieved. The scheme is that the clock of a first phase-locked loop coupled with a serial interface in a main chip and the clock of a second phase-locked loop coupled with a serial interface in a cache chip are homologous, a dual in-line memory module interface in the cache chip and the serial interface in the cache chip are coupled with the second phase-locked loop. The main chip and the cache chip perform first rate negotiation to determine a first target rate; the main chip initializes the cache chip at the first target rate to determine a second target rate supported by the dual in-line memory module interface between the cache chip and a memory chip; the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are both configured as a clock frequency corresponding to the second target rate, and second rate negotiation is completed. The embodiment of the application is used for a serial interface to expand a DRAM system.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method and apparatus for unifying clock frequencies. Background Technology

[0002] Currently, the speed upgrade of Double Data Rate (DDR) systems is slow. The industry typically uses serial interfaces, namely serializers and deserializers (SerDes), to extend RRD modules or other memory media to increase memory bandwidth.

[0003] In schemes that expand memory using SerDes to extend Dynamic Random-access Memory (DRAM), the typical components include a main Central Processing Unit (CPU) chip, a cache chip, and a DRAM chip. The CPU chip and the cache chip communicate via a SerDes serial interface, while the cache chip and the DRAM chip communicate via a Dual-Inline-Memory-Modules (DIMM) interface. SerDes and DRAM operate on separate and unrelated frequency bands.

[0004] Specifically, because DRAM DIMM interfaces operate at multiple transmission frequencies in various application scenarios, the system can only determine the operating frequency of the DRAM chip after a DIMM chip is inserted into the DRAM slot. Then, the system configures the clock frequencies of the phase-locked loop (PLL) 3 in the cache chip and the DDR clock (clk_ddr) to the specified frequencies corresponding to that frequency. On the SerDes interface side, the current serial protocol also typically operates at a fixed frequency. Therefore, in current technology, the clock (clk_sds) on the SerDes serial interface side of the cache chip and the DDR clock (clk_ddr) are usually asynchronous clocks, requiring asynchronous processing of data across clock domains in both the transmit (TX) and receive (RX) directions. Furthermore, the system bus clock (clk_bus) in the main CPU chip and the operating clock (clk_sds) of the SerDes serial interface are also typically asynchronous clocks, requiring asynchronous processing of data in both the TX and RX directions as well. Thus, a data stream needs to cross four asynchronous clock domains in the TX and RX directions. Moreover, if the main CPU chip and the cache chip do not share the same clock source, a data stream needs to cross six asynchronous clock domains, resulting in significant latency due to the data stream crossing asynchronous clock domains. Summary of the Invention

[0005] This application provides a method and apparatus for unifying clock frequencies, which can unify the frequencies of SerDes and DRAM when using a serial interface to expand memory, so that the entire system operates in the synchronous clock domain, reducing the number of times the data stream crosses asynchronous clocks, and ultimately achieving the goal of low latency.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a method for unifying clock frequencies is provided, applied to a system that expands memory via a serial interface. The system includes a main chip, a cache chip, and at least one memory chip coupled to the cache chip. A first phase-locked loop coupled to the serial interface in the main chip and a second phase-locked loop coupled to the serial interface in the cache chip share the same clock source. Both the dual in-line memory (DIM) module interface in the cache chip and the serial interface in the cache chip are coupled to the second phase-locked loop. The method includes:

[0008] After the system control main chip and cache chip complete the serial interface initialization, the first rate negotiation between the main chip and cache chip is performed to determine the first target rate for the main chip to access the cache chip. After the system control main chip initializes the cache chip at the first target rate, the second target rate supported by the dual in-line memory module interface between the cache chip and the memory chip is determined. The system configures the clock frequency of the first phase-locked loop in the main chip and the clock frequency of the second phase-locked loop in the cache chip to the clock frequency corresponding to the second target rate, and controls the main chip and cache chip to complete the second rate negotiation.

[0009] Among them, the serial interface can be understood as SerDes, the phase-locked loop can be a PLL, and the dual in-line package (DIMM) memory module can be a DIMM.

[0010] Therefore, in systems using serial interfaces to expand memory, all SerDes in this application use the same source reference clock, and the DRAM's operating clock comes from the same PLL as the SerDes. This means that the DRAM and SerDes clocks are essentially from the same source.

[0011] Based on the modification of the same clock source, this application employs a two-stage rate negotiation during system startup to achieve frequency unification between DRAM and SerDes. In the first rate negotiation, the main chip and cache chip negotiate a low-frequency rate, i.e., the first target rate. At this rate, the main chip initializes the cache chip and obtains its information, i.e., the rate of the memory chip inserted into the cache chip. Upon obtaining the cache chip information, the main chip determines the frequency point at which DRAM and SerDes operate together, which corresponds to the highest rate of the DIMM interface when the memory chip is inserted into the slot. Then, the main chip initializes the frequency points of the PLL in both the main chip and the cache chip to match the frequency points corresponding to the memory chip's rate. Based on the initialized PLL frequency points, the main chip and cache chip perform a second rate negotiation. Upon successful negotiation, DRAM and SerDes reach a unified target rate, i.e., the second target rate. After completing both rate negotiations, service transmission can begin between the main chip, cache chip, and memory chip.

[0012] In this way, the main chip and cache chip use a common reference clock, and the maximum speed of the main chip and cache chip is related to the maximum speed supported by the memory chip with the DIMM interface on the cache chip. When the maximum speed supported by the memory chip with the DIMM interface is different, the transmission rate of the serial interface SerDes of the main chip and cache chip will also change synchronously. In this way, when data crosses multiple chips, it still operates in the synchronous clock domain, without the latency consumption of asynchronous processing, which can reduce the additional latency added to the system by asynchronous clocks.

[0013] In one possible design, after the main chip and cache chip complete serial interface initialization, the first rate negotiation between the main chip and cache chip is performed to determine the first target rate for the main chip to access the cache chip. This includes: controlling the first phase-locked loop in the main chip and the second phase-locked loop in the cache chip to perform frequency multiplication based on a common reference clock to obtain the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop, which are the same; determining the transmission rate of the serial interface in the main chip based on the clock frequency of the first phase-locked loop, and determining the transmission rate of the serial interface in the cache chip based on the clock frequency of the second phase-locked loop; performing the first rate negotiation between the main chip and cache chip based on the transmission rates of the serial interface in the main chip and the serial interface in the cache chip, and determining the transmission rates of the serial interface in the main chip and the serial interface in the cache chip as the first target rate for the main chip to access the cache chip when the negotiation is successful.

[0014] It's important to understand that after the main chip and cache chip power on and complete the serial interface initialization, the clock frequencies in the first phase-locked loop (PLL) of the main chip and the second PLL of the cache chip are determined based on a common reference clock frequency. This effectively determines the transmission rates of the main chip and the cache chip, ensuring they are identical. Therefore, when the main chip successfully negotiates a rate with the cache chip based on this determined transmission rate, it establishes the first target rate at which the main chip can access the cache chip. In other words, the main chip and the cache chip negotiate a low-frequency rate through which the main chip can access the cache chip.

[0015] In one possible design, after the main control chip initializes the cache chip at a first target rate, determining the second target rate supported by the dual in-line memory (DIM) interface between the cache chip and the memory chip includes: controlling the main control chip's serial interface to access the cache chip's registers at the first target rate to initialize the cache chip's registers; controlling the cache chip to access the memory chip connected to the cache chip through the DIM interface to determine the highest rate supported by the DIM interface, and using the highest frequency supported by the DIM interface as the second target rate; and controlling the cache chip to record the second target rate in the cache chip's registers.

[0016] Considering that the memory chips inserted into the block DIMM interface of the cache chip may support different access rates, when the master chip can access the cache chip, the cache chip can record the access rate supported by the currently inserted memory chip in the cache chip's register. In this way, the master chip can determine the highest supported rate (second target rate) of the memory chip from this register, and adjust the clock frequencies of the master chip and the cache chip to match this highest rate, thus avoiding cross-asynchronous clock domains and reducing data transmission latency.

[0017] In one possible design, configuring the clock frequency of the first phase-locked loop in the main chip and the clock frequency of the second phase-locked loop in the cache chip to a clock frequency corresponding to the second target rate, and controlling the main chip and the cache chip to complete the second rate negotiation includes: controlling the main chip to read the second target rate from the register of the cache chip; controlling the main chip to initialize the clock frequencies of the first and second phase-locked loops according to the second target rate, so that the clock frequencies of the first and second phase-locked loops are clock frequencies corresponding to the second target rate; and controlling the serial interface of the main chip and the serial interface of the cache chip to perform the second rate negotiation at the second target rate.

[0018] In this way, the SerDes in the main chip and cache chip, and the DRAM between the cache chip and the memory chip will operate at a unified clock frequency (frequency point / second target rate). With the first PLL and the second PLL having the same clock source, and the clock in the cache chip and the serial interface also having the same clock source, the main chip will avoid crossing asynchronous clock domains when accessing the memory chip through the cache chip, thus reducing data transmission latency.

[0019] In one possible design, the serial interfaces of the main chip and the cache chip can negotiate rates at any specified integer rate. That is, the serial interfaces of the main chip and the cache chip are not limited to negotiating at certain fixed frequencies (e.g., 8Gbps or 16Gbps for PCIe). This two-stage rate negotiation process allows for negotiation at any specified integer rate.

[0020] Secondly, a system for expanding memory via a serial interface is provided. The system includes a main chip, a cache chip, and at least one memory chip coupled to the cache chip. The clocks of a first phase-locked loop coupled to the serial interface in the main chip and a second phase-locked loop coupled to the serial interface in the cache chip are from the same source. Both the dual in-line memory module interface in the cache chip and the serial interface in the cache chip are coupled to the second phase-locked loop, wherein:

[0021] The main chip is used to complete the serial interface initialization with the cache chip, and then to complete the first rate negotiation with the cache chip to determine the first target rate for the main chip to access the cache chip. After the cache chip is initialized at the first target rate, the second target rate supported by the dual in-line memory module interface between the cache chip and the memory chip is determined. The clock frequency of the first phase-locked loop in the main chip is configured to the clock frequency corresponding to the second target rate. The cache chip is used to configure the clock frequency of the second phase-locked loop in the cache chip to the clock frequency corresponding to the second target rate. The main chip is also used to complete the second rate negotiation with the cache chip.

[0022] For the second aspect and the beneficial effects of any possible design of the second aspect, please refer to the description of the first aspect.

[0023] In one possible design, the main chip controls the first phase-locked loop (PLL) L to perform frequency multiplication based on a common reference clock to obtain the operating clock frequency of the first PLL; the cache chip controls the second PLL to perform frequency multiplication based on a common reference clock to obtain the operating clock frequency of the second PLL, the operating clock frequencies of the first and second PLLs being the same; the main chip determines the transmission rate of its serial interface based on the operating clock frequency of the first PLL; the cache chip determines the transmission rate of its serial interface based on the operating clock frequency of the second PLL; the main chip performs a first rate negotiation between itself and the cache chip based on the transmission rates of their serial interfaces; upon successful negotiation, the transmission rate of the serial interface in the main chip is determined as the first target rate for the main chip to access the cache chip; the cache chip, upon successful negotiation, determines the transmission rate of its serial interface as the first target rate for the main chip to access the cache chip.

[0024] In one possible design, the main chip controls the serial interface of the main chip to access the registers of the cache chip at a first target rate to initialize the registers of the cache chip; the cache chip accesses the memory chip that is connected to the cache chip through the dual in-line memory module interface, determines the highest rate supported by the dual in-line memory module interface, and takes the highest frequency supported by the dual in-line memory module interface as the second target rate; the second target rate is recorded in the registers of the cache chip.

[0025] In one possible design, the main chip is used to read the second target rate from the register of the cache chip; initialize the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop according to the second target rate, so that the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are clock frequencies corresponding to the second target rate; and control the serial interface of the main chip and the serial interface of the cache chip to perform a second rate negotiation at the second target rate.

[0026] In one possible design, the serial interface of the main chip and the serial interface of the cache chip can negotiate rates to support any specified integer rate.

[0027] Thirdly, a frequency control device is provided, applied to a system that expands memory via a serial interface. The system includes a main chip, a cache chip, and at least one memory chip coupled to the cache chip. The clocks of a first phase-locked loop coupled to the serial interface in the main chip and a second phase-locked loop coupled to the serial interface in the cache chip are from the same source. Both the dual in-line memory module interface in the cache chip and the serial interface in the cache chip are coupled to the second phase-locked loop. The frequency control device includes:

[0028] The rate negotiation unit is used to control the main chip and the cache chip to perform the first rate negotiation after the serial interface initialization is completed, so as to determine the first target rate for the main chip to access the cache chip; the rate acquisition unit is used to control the main chip to determine the second target rate supported by the DIMM interface between the cache chip and the memory chip after the cache chip is initialized at the first target rate; the rate negotiation unit is also used to configure the clock frequency of the first PLL in the main chip and the clock frequency of the second PLL in the cache chip to the clock frequency corresponding to the second target rate, and control the main chip and the cache chip to complete the second rate negotiation.

[0029] For the third aspect and the beneficial effects of any possible design of the third aspect, please refer to the description of the first aspect.

[0030] In one possible design, the rate negotiation unit is used to: control the first phase-locked loop in the main chip and the second phase-locked loop in the cache chip to perform frequency multiplication based on a common reference clock to obtain the operating clock frequency of the first phase-locked loop and the operating clock frequency of the second phase-locked loop, wherein the operating clock frequency of the first phase-locked loop and the operating clock frequency of the second phase-locked loop are the same; determine the transmission rate of the serial interface in the main chip based on the operating clock frequency of the first phase-locked loop, and determine the transmission rate of the serial interface in the cache chip based on the operating clock frequency of the second phase-locked loop; perform the first rate negotiation between the main chip and the cache chip based on the transmission rate of the serial interface in the main chip and the transmission rate of the serial interface in the cache chip, and determine the transmission rate of the serial interface in the main chip and the transmission rate of the serial interface in the cache chip as the first target rate for the main chip to access the cache chip when the negotiation is successful.

[0031] In one possible design, the rate acquisition unit is used to: control the serial interface of the main chip to access the registers of the cache chip at a first target rate to initialize the registers of the cache chip; control the cache chip to access the memory chip that is connected to the cache chip through the dual in-line memory module interface to determine the highest rate supported by the dual in-line memory module interface, and take the highest frequency supported by the dual in-line memory module interface as the second target rate; and control the cache chip to record the second target rate in the registers of the cache chip.

[0032] In one possible design, the rate negotiation unit is used to: control the main chip to read the second target rate from the register of the cache chip; control the main chip to initialize the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop according to the second target rate, so that the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are clock frequencies corresponding to the second target rate; and control the serial interface of the main chip and the serial interface of the cache chip to perform a second rate negotiation at the second target rate.

[0033] In one possible design, the serial interface of the main chip and the serial interface of the cache chip can negotiate rates to support any specified integer rate.

[0034] Fourthly, a frequency control device is provided, comprising at least one processor connected to a memory, the at least one processor being configured to read and execute a program stored in the memory, such that the device performs the method as described in the first aspect or any one thereof.

[0035] Fifthly, a frequency control device is provided, comprising a main chip, a cache chip, and a memory chip, wherein the main chip is coupled to the memory and is used to read and execute program instructions stored in the memory to implement the method described in the first aspect or any one thereof.

[0036] Sixthly, a frequency control device is provided, which is included in an electronic device and has the function of implementing the behavior of the electronic device in any of the above aspects and any possible implementations. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above functions. For example, a rate negotiation module or unit and a rate acquisition module or unit, etc.

[0037] A seventh aspect provides a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the method described in the first aspect and any possible design of the first aspect.

[0038] Eighthly, a computer program product is provided that, when run on a computer or processor, causes the computer or processor to perform the methods described in the first aspect and any possible implementation thereof.

[0039] It is understood that any of the frequency control devices, computer-readable storage media, or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0040] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0041] Figure 1 A schematic diagram illustrating a scheme for using SerDes extended DRAM provided in an embodiment of this application;

[0042] Figure 2 This application provides a schematic diagram of a serial interface extended DRAM system network.

[0043] Figure 3 This application provides a schematic diagram of a system network structure.

[0044] Figure 4 This is a schematic flowchart of a method for unifying clock frequency provided in an embodiment of this application;

[0045] Figure 5 This is a schematic flowchart of a method for unifying clock frequency provided in an embodiment of this application;

[0046] Figure 6 This application provides a schematic diagram of a system architecture for expanding memory via a serial interface, as illustrated in an embodiment of the present application.

[0047] Figure 7 This application provides a schematic diagram of a system architecture for expanding memory via a serial interface, as illustrated in an embodiment of the present application.

[0048] Figure 8 This is a schematic diagram of a system architecture for a serial interface extended memory provided in an embodiment of this application. Detailed Implementation

[0049] For ease of understanding, the examples provide explanations of some concepts related to the embodiments of this application for reference. As shown below:

[0050] DRAM: Dynamic Random Access Memory, is the most common type of system memory. DRAM can retain data for a very short time. To retain data, DRAM uses capacitors for storage and needs to be refreshed periodically. If the memory cells in DRAM are not refreshed, the stored information will be lost; for example, data will be lost when the power is turned off.

[0051] DDR: Double Data Rate. Currently, DDR1-DDR5 refer to memory generations. Different generations of memory have different transfer rates. Theoretically, DDR1 represents one generation. DDR2's transfer rate is twice that of DDR1, and DDR5's transfer rate is twice that of DDR3.

[0052] DIMM: This can be understood as a memory module inserted into a slot on a DRAM, which can provide a 64-bit data channel.

[0053] SerDes is a mainstream time-division multiplexing, point-to-point serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through the transmission medium, and finally converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology fully utilizes the channel capacity of the transmission medium, reduces the required transmission channels and the number of device pins, increases signal transmission speed, and thus significantly reduces communication costs.

[0054] Asynchronous clocks: When the phase relationship between two clocks is fixed, these two clocks can be called synchronous clocks. Generally, clocks from the same source, such as those generated by the same Mixed Mode Clock Manager (MMCM) or Phase Locked Loop (PLL), can be called synchronous clocks. Therefore, the master clock and its corresponding derived clocks can be constrained into the same clock group. When the phase relationship between two clocks cannot be determined, these two clocks can be called asynchronous clocks. Two clocks from different crystal oscillators are definitely asynchronous clocks. Typically, different master clocks in a design are definitely asynchronous clocks; therefore, these two master clocks and their derived clocks can be constrained into different clock groups.

[0055] PLL: A PLL uses an externally input reference signal to control the frequency and phase of the internal oscillation signal. Because a PLL can automatically track the frequency of the output signal to the frequency of the input signal, it is commonly used in closed-loop tracking circuits.

[0056] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0057] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0058] In a computer system, memory is arguably the key factor determining overall performance. Even with a fast CPU, without a good memory system to complement it, even the best CPU performance cannot be fully realized. Currently, the number of server CPU cores (from 8 to 126) has increased 16-fold, while the number of pins and memory channels (from 4 to 8) has only increased 2-fold. This shows that the development rate of memory bandwidth is not keeping pace with the development speed of CPU cores, and the average DRAM memory bandwidth per core is showing a continuous downward trend.

[0059] Standard DDR modules typically employ a 64-bit architecture, transmitting 64 bits of binary data at a time, corresponding to a 64-bit parallel memory bus. However, due to inherent limitations, parallel buses struggle to achieve significant performance improvements. First, parallel buses are prone to mutual interference, leading to unstable transmission signals and hindering rapid frequency increases. The gradual, step-by-step improvement in memory specifications is not solely driven by market considerations but also by technological realities. Second, the parallel data sent by the memory module must arrive at the receiving end synchronously within the same transmission cycle. This necessitates strictly consistent lengths across the 64 traces on the printed circuit board (PCB), placing stringent demands on PCB design. As memory frequencies continue to increase, the allowable trace length error decreases, ultimately making circuit design a major challenge. From this perspective, the development space for parallel memory is limited, ultimately leading to narrower bit widths and serialization. Third, also due to wiring constraints, the DDR system can only achieve a maximum of dual-channel operation, requiring 128 data lines and occupying a significant amount of PCB space. Even for quad-channel operation, the motherboard lacks sufficient PCB space, further complicating data synchronization issues. Various defects have resulted in slow speed upgrades for the DDR system, so the industry has begun to try using serial interfaces to expand DDR modules or other memory media.

[0060] Currently, Open Memory Interface (OMI) technology can be used to improve system memory bandwidth and capacity. For the DDR architecture, it aims to address these near-memory challenges in two ways: migrating to SerDes and using a DIMM controller. Specifically, the SerDes connection replaces the current DDR-style interface, providing higher speeds with fewer signals. Furthermore, OMI essentially removes the memory controller from the host, integrating it onto the memory DIMM, simplifying processor design. Moreover, this controller can connect to many different types of memory, acting as a bridge between the memory and the processor.

[0061] like Figure 1 As shown, in the SerDes DRAM expansion scheme, chip 1 is the main chip (main CPU chip), chip 2 is the cache chip, and chip 3 is the memory chip. Multiple chips 3 can be coupled to one chip 2 to achieve memory expansion. The interface between chip 1 and chip 2 is a SerDes serial interface, and the interface between chip 2 and chip 3 is a DIMM parallel interface.

[0062] In the existing scheme, the operating frequency of SerDes and the operating frequency of DRAM are not related. Chip 1 includes a bus clock (clk_bus) and a logic clock (clk_logic). The reference clock for the operating clock (clk_sds1) of PLL1 on the SerDes1 (serial interface 1) interface side is REF_CLK1. The reference clock for the operating clock (clk_sds2) of PLL2 on the SerDes2 (serial interface 2) interface side in chip 2 is REF_CLK2. The operating clock (clk_ddr) of PLL3 coupled to the DIMM interface in chip 2, which triggers the DDR physical interface (PHY) 2, shares the same reference clock source as clk_sds2, both being REF_CLK2.

[0063] In application scenarios, DIMM interfaces have multiple frequency points corresponding to different transmission rates. For example, DDR5 transmission rates include 4.8GT / s, 5.200GT / s, 6.800GT / s, and 8.400GT / s. Only after a DIMM memory module (DDRPHY3) is inserted into the DRAM slot can chip 1 determine the operating frequency of the DRAM. Chip 1 can then configure the PLL3 in chip 2 to trigger the DDR PHY2's operating clock, clk_ddr, according to the DRAM's operating frequency. On the SerDes2 interface side of chip 2, current serial protocols typically operate at fixed frequencies. For example, the data rate of the high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) protocol usually has multiple fixed frequency transmission rates, such as 2.5GT / s, 5GT / s, 8GT / s, 16GT / s, and 32GT / s.

[0064] Therefore, the operating frequencies of DRAM and SerDes are not the same. In other words, in current solutions using SerDes to extend DRAM, clk_sds2 and clk_ddr in chip 2 are typically asynchronous clocks, requiring the data flow to cross clock domains in both the TX and RX directions. Figure 1 The data stream shown needs to be processed asynchronously when passing through the TX direction indicated by ③ and the RX direction indicated by ④. Furthermore, typically, the system bus clock clk_bus in chip 1 and the operating clock clk_sds1 of the serial interface SerDes1 in chip 1 are also asynchronous clocks, and the data stream... Figure 1 The TX direction indicated by ① and the RX direction indicated by ⑥ also need to be processed asynchronously.

[0065] Furthermore, if SerDes1 in chip 1 and SerDes2 in chip 2 share a reference clock, and the frequencies of clk_sds1 and clk_sds2 are the same, the data stream does not need to undergo asynchronous processing when passing through the TX direction indicated by ② and the RX direction indicated by ⑤. If SerDes1 in chip 1 and SerDes2 in chip 2 do not share a reference clock (PLL1 uses REF_CLK1, PLL2 uses REF_CLK2), the data stream needs to undergo asynchronous processing when passing through the TX direction indicated by ② and the RX direction indicated by ⑤.

[0066] Therefore, without a unified operating frequency for DRAM and SerDes, if chip 1 and chip 2 use the same clock source, the data flow needs to cross 4 asynchronous clock domains. If chip 1 and chip 2 do not use the same clock source, the data flow needs to cross 6 asynchronous clock domains. In both cases, additional latency will be added, making it virtually impossible to achieve a latency of less than 10ns.

[0067] Therefore, this application provides a method and apparatus for unifying clock frequencies, which can solve the problem of unifying the frequencies of DRAM and SerDes when using serial interfaces to expand memory, so that the entire system operates in the synchronous clock domain, reducing the number of times the data stream crosses asynchronous clocks, and ultimately achieving the goal of low latency.

[0068] In systems using serial interfaces to expand memory, all SerDes in this application use the same source reference clock, and the DRAM's operating clock comes from the same PLL as the SerDes. This means the DRAM and SerDes clocks are essentially from the same source.

[0069] Based on the modification of the same clock source, this application employs a two-stage rate negotiation during system startup to achieve frequency unification between DRAM and SerDes. In the first rate negotiation, the main chip and cache chip negotiate a low-frequency rate. At this rate, the main chip initializes the cache chip and obtains its information, specifically the rate of the memory chip inserted into it. Upon obtaining this information, the main chip determines the common operating frequency for DRAM and SerDes, which corresponds to the highest rate of the DIMM interface when the memory chip is inserted into the slot. Then, the main chip initializes the frequency of its PLL and the PLL in the cache chip to match the frequency of the memory chip's rate. Based on the initialized PLL frequency, the main chip and cache chip perform a second rate negotiation. Successful negotiation ensures that DRAM and SerDes have reached a unified target rate. After both rate negotiations are completed, service transmission can begin between the main chip, cache chip, and memory chip.

[0070] In this way, the main chip and cache chip use a common reference clock, and the maximum speed of the main chip and cache chip is related to the maximum speed supported by the memory chip with the DIMM interface on the cache chip. When the maximum speed supported by the memory chip with the DIMM interface is different, the transmission rate of the serial interface SerDes of the main chip and cache chip will also change synchronously. In this way, when data crosses multiple chips, it still operates in the synchronous clock domain, without the latency consumption of asynchronous processing, which can reduce the additional latency added to the system by asynchronous clocks.

[0071] It's important to note that there's typically a multiple relationship between transmission rate and transmission frequency (frequency point). For example, the "quad pumped" technology used in Front Side Bus (FSB) has been improved, where data is transmitted four times per bus clock cycle. This means the bus's data transfer rate is equal to four times the bus clock frequency. For instance, if the bus clock frequency is 333MHz, the data transfer rate is 1332MT / s, or 1.332GT / s.

[0072] When this application determines that the transmission rate of SerDes is consistent with the transmission rate of the DIMM interface, it is equivalent to determining that the clock frequencies of PLL1 and PLL2 are consistent. Combined with the fact that PLL1 and PLL2 are from the same source reference clock, data does not need to be processed across clock domains when it is transmitted across the main chip, cache chip and memory chip.

[0073] The unified clock frequency method provided in this application can be applied to serial interface extended DRAM system networking. This networking structure can be as follows: Figure 2 As shown, it includes three types of chips. Chip 1 is the main chip, or main CPU chip; chip 2 is a cache chip; and chip 3 is a DRAM memory chip, including... Figure 2 The diagram illustrates chips 3_0, 3_1, 3_2, and 3_3. Chip 1 is located on the motherboard, while chips 2 and 3 are located on the backplate. Of course, Figure 2 The network shown is a schematic configuration; chip 2 and chip 3 can also be directly installed on the motherboard.

[0074] The interface between chip 1 and chip 2 is a serial interface (SerDes), while the interface between chip 2 and chip 3 is a DIMM interface (DIMM parallel interface). Chip 1 can be expanded with more DIMM interfaces through chip 2, meaning the number of chips 3 is not limited. Figure 2The four shown are examples. This method of expanding DRAM via a serial interface allows for the addition of more DIMM interfaces in chip 2, thereby increasing DRAM capacity. When the bandwidth of the serial interface is greater than the bandwidth of the directly connected DIMM interfaces, the number of chips 3 coupled to chip 2 can be increased, allowing chip 1 to obtain a greater DRAM access bandwidth.

[0075] In this configuration, chip 2 serves as a cache chip, its function being to expand memory so that chip 1 can access more of chip 3. In some embodiments, chip 1 may also have at least two serial interfaces, with one serial interface coupled to chip 2 to achieve a larger DRAM capacity.

[0076] In this application Figure 2 Based on the provided system networking approach, the specific system networking structure of this application can be found by referring to... Figure 3 The architecture is shown below. Here, clk_bus is the bus clock in chip 1; PLL1 is a phase-locked loop (PLL) for the clock frequency of the serial interface SerDes1 in chip 1, and clk_sds1 is the clock for transmitting and receiving data on the serial interface SerDes1 in chip 1; PLL2 is a PLL for the clock frequency of the serial interface SerDes2 in chip 2, and clk_sds2 is the clock for transmitting and receiving data on the serial interface SerDes2 in chip 2; clk_ddr is the clock for the DDR PHY2 in chip 2, or in other words, the clock for the DIMM interface in chip 2.

[0077] It should be understood that the purpose of unifying the SerDes and DRAM clock frequencies in this application is to reduce the latency of the entire system. The key to reducing latency lies in minimizing the number of data paths crossing asynchronous clock domains. The rate unification method in this application achieves frequency unification, enabling the interface logic circuits of chip 1, chip 2, and chip 3 to operate in the synchronous clock domain, thereby avoiding the crossing of asynchronous clock domains.

[0078] refer to Figure 3In this application, the serial interfaces SerDes1 and SerDes2 of chip 1 and chip 2 use a common reference clock REF_CLK. This application allows software to configure the clock sources of PLL1 and PLL2 to the same reference clock REF_CLK. When PLL1 and PLL2 share the same clock source, SerDes1 in chip 1 and SerDes2 in chip 2 operate at the same frequency, effectively locking PLL1 and PLL2 to the same frequency. This clock configuration process can be implemented through chip 1. Since PLL1 and PLL2 share a reference clock, clk_sds1 and clk_sds2 have the same frequency, differing only in phase. Therefore, when the data output from SerDes1 of chip 1 is sampled on SerDes2 of chip 2, only phase sampling needs to be adjusted; asynchronous processing across clock domains is not required.

[0079] Furthermore, the clocks for clk_sds2 and clk_ddr in chip 2 both originate from PLL2. clk_sds2 and clk_ddr have the same frequency relationship or a multiplication relationship; in short, clk_sds2 and clk_ddr are in the same clock domain. Therefore, the serial interface controller ( Figure 3 The digital logic (not shown in the diagram) and the digital logic of the DDR controller are in the synchronous clock domain and do not require asynchronous processing across clocks.

[0080] Therefore, the data flow from chip 1 through chip 2 to chip 3 does not need to undergo cross-clock domain processing, which can reduce latency.

[0081] The method for unifying the clock frequency in this application is described below, for reference. Figure 4 This method is applied to a system that expands memory via a serial interface, the system including a main chip, a cache chip, and at least one memory chip coupled to the cache chip. A first PLL coupled to the serial interface in the main chip and a second PLL coupled to the serial interface in the cache chip share the same clock source. Both the DIMM interface in the cache chip and the serial interface in the cache chip are coupled to the second PLL. The method includes:

[0082] 401. After the system control main chip and cache chip complete the serial interface initialization, the first rate negotiation between the main chip and cache chip is performed to determine the first target rate for the main chip to access the cache chip.

[0083] Figure 4 The main chip in the middle is equivalent to Figure 2 and Figure 3 Chip 1 in the middle, Figure 4 The cache chip in the middle is equivalent to Figure 2 and Figure 3 Chip 2 in the middle, Figure 4 The memory chip in the middle is equivalent to Figure 2 and Figure 3 Chip 3 in the middle. Figure 4 The first PLL in the middle is equivalent to Figure 3 PLL1 in Figure 4 The second PLL in the middle is equivalent to Figure 3 PLL2 in the middle.

[0084] In some embodiments, after the system powers on, the main chip can control the main chip and the cache chip to complete the initialization of the serial interface. During the initialization process, the main chip can control the first PLL and the second PLL to configure their clock frequencies according to a common reference clock REF_CLK. After configuration, the clock frequencies of the first PLL and the second PLL are the same, thereby making the rates of the main chip's serial interface SerDes1 and the cache chip's serial interface SerDes2 the same, both at the first target rate. At this time, the main chip can control the main chip's serial interface SerDes1 and the cache chip's serial interface SerDes2 to start rate negotiation and perform the first rate negotiation. If the negotiation is successful, the main chip determines that the rate at which the main chip accesses the cache chip is the first target rate.

[0085] 402. After the system control main chip initializes the cache chip at the first target rate, it determines the second target rate supported by the dual in-line memory module interface between the cache chip and the memory chip.

[0086] The main chip can access the registers in the cache chip via serial interfaces SerDes1 and SerDes2 to initialize them, making them accessible for read, write, and modify operations. Furthermore, the main chip can initialize the DIMM interface in the cache chip to determine the maximum speed supported by the memory chips inserted into the DIMM interface, and record this maximum speed in the cache chip's registers. This maximum speed supported by the memory chips is denoted as the second target speed.

[0087] 403. The system configures the clock frequency of the first phase-locked loop in the main chip and the clock frequency of the second phase-locked loop in the cache chip to the clock frequency corresponding to the second target rate, and controls the main chip and the cache chip to complete the second rate negotiation.

[0088] The main chip can access the registers of the cache chip to obtain the second target rate, and configure the clock frequencies of the first and second PLLs to correspond to the second target rate. Based on the second target rate, the main chip's serial interface SerDes1 and the cache chip's serial interface SerDes2 perform a second rate negotiation. Once the negotiation is successful, the frequency unification process ends. The SerDes core DRAM in the system operates at the unified frequency.

[0089] Therefore, in a system that extends DDR through the SerDes interface, this application can use the first PLL and the second PLL in the main chip as the same clock source, and the DRAM clock is coupled to the second PLL. Through two rate negotiations, the clock frequencies of the first PLL, the second PLL and the DRAM can be unified. When data is transmitted across chips in this system, it still works in the synchronous clock domain, which can reduce system latency.

[0090] exist Figure 4 Based on the system shown, the method for unifying clock frequency provided in this application will be further described below.

[0091] This application provides a method for unifying clock frequencies, such as... Figure 5 As shown, the method includes:

[0092] 501. The system determines that the main chip, cache chip and at least one memory chip are powered on.

[0093] For example, in a terminal device, when a user powers on the terminal device, the main chip, cache chip, and at least one memory chip on the motherboard are also powered on after the motherboard is powered on.

[0094] 502. The system control main chip and cache chip complete the serial interface initialization.

[0095] In some embodiments, the main chip controls the first PLL in the main chip and the second PLL in the cache chip to perform frequency multiplication based on a common reference clock to obtain the clock frequency of the first PLL and the clock frequency of the second PLL, and the clock frequency of the first PLL and the clock frequency of the second PLL are the same.

[0096] The transmission rate of serial interface 1 (SerDes1) in the main chip is determined based on the clock frequency of the first PLL, and the transmission rate of serial interface 2 (SerDes2) in the cache chip is determined based on the clock frequency of the second PLL.

[0097] For example, refer to Figure 6The main chip includes logic controller 1, and the cache chip includes logic controller 2. When the logic controller determines that the main chip is powered on according to the bus clock clk_bus, logic controller 1 can send a clock frequency configuration instruction to PLL1 in serial interface 1. PLL1 can perform frequency multiplication based on the reference clock frequency REF_CLK to obtain the operating clock frequency of PLL1. Logic controller 1 can also send a clock frequency configuration instruction to PLL2 in serial interface 2 through serial interface 1. PLL2 performs frequency multiplication based on the reference clock frequency REF_CLK to obtain the operating clock frequency of PLL2.

[0098] Based on the clock frequencies of PLL1 and PLL2, serial interface 1 can determine the transmission rate based on the clock frequency of PLL1, and serial interface 2 can determine the transmission rate of serial interface 1 based on the clock frequency of PLL2.

[0099] For example, if the reference clock REF_CLK provides a clock frequency of 500MHz, both PLL1 and PLL2 can be multiplied by 4, resulting in clock frequencies of 2000MHz for both PLL1 and PLL2. Assuming the default serial interface transmission rate is four times the PLL clock frequency, then the transmission rates of serial interface 1 and serial interface 2 are 8000MT / s, or 8GT / s for both.

[0100] 503. The system control main chip and cache chip complete the first rate negotiation to determine the first target rate for the main chip to access the cache chip.

[0101] After the transmission rates of serial interface 1 and serial interface 2 are determined, the main chip can perform the first rate negotiation between the main chip and the cache chip based on the transmission rate of serial interface 1 of the main chip and the transmission rate of serial interface 2 in the cache chip. When the negotiation is successful, the transmission rates of the serial interfaces in the main chip and the serial interfaces in the cache chip are determined as the first target rate for the main chip to access the cache chip.

[0102] The rate negotiation process can be similar to existing rate negotiation processes. For example, logic controller 1 in the main chip controls serial interface 1 to send a message to serial interface 2 in the cache chip at a transmission rate of 8GT / s. If serial interface 2 receives the message at a transmission rate of 8GT / s and sends a message indicating successful message reception to serial interface 1, the first rate negotiation is successful. The main chip can determine that the first target rate for serial interface 1 to access the cache chip is 8GT / s. The main chip can then begin accessing the cache chip based on this first target rate, such as performing read, write, or modify operations on the memory chip through the cache chip. In this case, the first target rate can be understood as a low-frequency rate, and the main chip and the cache chip complete a low-speed negotiation process.

[0103] 504. The system control main chip accesses the registers of the cache chip at the first target rate and initializes the registers of the cache chip.

[0104] At the first target rate, the main chip can access the registers in the cache chip through serial interface 1 and serial interface 2 to initialize the registers in the cache chip and put them into a working state. For example, the main chip can send a register configuration initialization instruction to the logic controller 2 through serial interface 1 and serial interface 2, and the logic controller 2 initializes the registers in the cache chip according to the instruction.

[0105] In some embodiments, the cache chip is a buffer chip, and typically, the cache chip may not have a CPU. Therefore, at the first target speed, the CPU in the main chip needs to configure the registers in the cache chip to make the registers in the cache chip operational. Therefore, in this application, a custom message can be used to support the main chip's access to the registers in the cache chip.

[0106] 505. After the initialization of each DIMM interface in the system control cache chip is completed, the highest speed supported by the DIMM interface between the cache chip and the memory chip is obtained and recorded as the second target speed. The system then controls the cache chip to record the second target speed in the cache chip's register.

[0107] After initializing each register in the cache chip, in some embodiments, controlling the initialization of each DIMM interface in the cache chip can be understood as controlling the cache chip to access the memory chip that is connected to the cache chip through the DIMM interface in order to determine the highest rate supported by the DIMM interface and take the highest frequency supported by the DIMM interface as the second target rate.

[0108] Specifically, refer to Figure 6 The logic controller 2 in the cache chip controls the communication between the DIMM interface DDRPHY2 in the cache chip and the DIMM interface DDR PHY3 of the memory chip (i.e., chip 3). This allows the logic controller 2 to determine the type of chip 3 inserted into the DDR PHY2 slot and the maximum speed supported by that type. The logic controller 2 records this maximum speed in a register of the cache chip. This register, for example, is named REG.max_dimm_rate, and is used to store the transfer rate.

[0109] 506. The system control main chip reads the second target rate from the register of the cache chip.

[0110] When the cache chip stores the highest rate supported by the DIMM interface, it can notify the main chip via serial interface 2 that the highest rate determination is complete. The logic controller 1 in the main chip then accesses the registers of the cache chip again via serial interface 1 and serial interface 2, for example, accessing REG.max_dimm_rate mentioned above, reads the highest rate supported by the DIMM interface stored in the registers of the cache chip, and determines this highest rate as the second target rate.

[0111] It should be understood that the second target rate is usually greater than the first target rate. The first target rate is determined to achieve low-speed startup negotiation between the main chip and the cache chip, while the second target rate is the rate that the main chip will negotiate with the serial interface after startup for accessing the memory chip through the cache chip.

[0112] 507. The system control main chip initializes the clock frequency of the first PLL and the clock frequency of the second PLL according to the second target rate, so that the clock frequency of the first PLL and the clock frequency of the second PLL are the clock frequencies corresponding to the second target rate.

[0113] When the main chip obtains the second target rate, logic controller 1 can reinitialize PLL1 according to the second target rate, and logic controller 2 can reinitialize PLL2 according to the second target rate, that is, redetermine the clock frequency of PLL1 and PLL2.

[0114] For example, if the second target rate is 32GT / s, that is, the highest frequency supported by the DIMM interface is 32GT / s, and assuming that the transmission rate of the serial interface and the clock frequency of the PLL are 4 times, logic controller 1 can determine that the clock frequency of PLL1 after reinitialization is 8000MHz, and logic controller 2 can determine that the clock frequency of PLL2 after reinitialization is 8000MHz.

[0115] 508. The serial interface of the system control main chip and the serial interface of the cache chip perform a second rate negotiation at the second target rate.

[0116] According to the example in step 507, when the clock frequencies of PLL1 and PLL2 are reinitialized to 8000MHz, the transmission rate of serial interface 1 and serial interface 2 are both the second target rate of 32GT / s. At this time, logic controller 1 can control serial interface 1 and serial interface 2 to perform a second rate negotiation.

[0117] For example, logic controller 1 controls serial interface 1 to send a message to serial interface 2 at a transmission rate of 32GT / s. Serial interface 2 receives the message at a transmission rate of 32GT / s. If the message is successfully received, serial interface 2 sends a successful negotiation response message to serial interface 1.

[0118] In this way, the SerDes in the main chip and cache chip, and the DRAM between the cache chip and the memory chip will operate on a unified clock frequency (frequency point). With PLL1 and PLL2 being from the same source clock, and clk_ddr and clk_sds2 also being from the same source clock, the main chip will avoid crossing asynchronous clock domains when accessing the memory chip through the cache chip, thus reducing data transmission latency.

[0119] In some embodiments, when the serial interface of the main chip and the serial interface of the cache chip negotiate the rate, they can negotiate any specified integer rate, and are not limited to supporting a few fixed rates. For example, they are not limited to GT / s and 16GT / s supported by PCIe.

[0120] In some embodiments, after analysis, the operating frequency of DARM and the operating frequency of SerDes can be unified. Taking DDR5 as an example, the transmission parameters of DDR5 and SerDes can be found in Table 1.

[0121] Table 1

[0122]

[0123] In Table 1, DDR TYPE indicates that the DRAM type is DDR5, DDR Data Rate indicates the data transfer rate of DDR5 in MT / s, DDR PHY CLK indicates the clock frequency of the DDR5 DIMM interface, DDRC CLK indicates the clock frequency of the DDR5 DDR controller, and SerDes data CLK indicates the clock frequency of SerDes data transfer. It can be seen that the clock frequency of DDR PHY CLK is twice the clock frequency of SerDes data CLK. Assuming that the first target rate in the first rate negotiation is 2100MT / s in SerDes data CLK to achieve low-speed startup, the clock frequency of DDR PHY CLK can be obtained through the second rate negotiation, thus obtaining the second target rate, for example, 4200MT / s. Therefore, this application can unify the clock frequency of SerDes data CLK to the clock frequency of DDR PHY CLK, 4200MT / s, achieving clock frequency unification between SerDes and DRAM.

[0124] 509. The system controls the main chip, cache chip and memory chip to transmit services.

[0125] This application establishes a common reference clock (REF_CLK) for both the main chip and the cache chip, ensuring that the clock domains of the cache chip's DIMM interface and its serial interface (SerDes) are aligned. The highest speed ultimately selected by the main chip and the cache chip, i.e., the second target speed, is related to the highest speed supported by the memory chip with the DIMM interface inserted into the cache chip. When the highest speeds supported by the memory chips with the DIMM interface differ, the transmission rate of the serial interface (SerDes) will also change synchronously, effectively unifying the clock frequencies of SerDes and DRAM. When the main chip accesses the memory chip through the cache chip, i.e., when the data stream crosses multiple chips, the data stream is transmitted in a synchronous clock domain, eliminating asynchronous processing latency and reducing data transmission delay. Analysis shows that with careful design, the additional latency added to the entire system can be controlled to within 10ns.

[0126] It should be noted that the rate unification process, or frequency unification process, of this application occurs during the system's power-on startup process, but is not limited to execution only during startup. It can also be performed during normal system communication by capturing packets. For example, the main chip and the cache chip can perform a first and a second rate negotiation during data packet transmission to complete rate unification.

[0127] Furthermore, in scenarios where SerDes is used to extend other components, not limited to memory extension, the method flow of this application can also be used to achieve frequency uniformity and reduce latency.

[0128] It is understood that, in order to achieve the above functions, a system that expands memory via a serial interface includes hardware and / or software modules corresponding to perform each function. Based on the algorithmic steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementations should not be considered beyond the scope of this application.

[0129] This embodiment can divide the system for expanding memory via a serial interface into functional modules based on the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0130] When dividing each function into modules according to its corresponding function. Figure 7 This diagram illustrates a possible configuration of a system 70 for expanding memory via a serial interface, as described in the above embodiments. Figure 7 As shown, the system 70 for expanding memory via a serial interface may include: a rate negotiation unit 701, a rate acquisition unit 702, and an initialization unit 703.

[0131] The rate negotiation unit 701 can be used to support the system 70, which expands memory via a serial interface, in performing the above steps 401, 403, 503, 508, 509, etc., and / or other processes used in the technology described herein.

[0132] The rate acquisition unit 702 can be used to support the system 70, which expands memory via a serial interface, in performing the above steps 402, 505, 506, etc., and / or other processes used in the techniques described herein.

[0133] The initialization unit 703 can be used to support the system 70, which expands memory via a serial interface, in executing steps 501, 502, 504, 507, etc., and / or other processes used in the techniques described herein.

[0134] It should be noted that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0135] The system 70 provided in this embodiment, which expands memory via a serial interface, is used to execute the above-described method of unifying clock frequency, and thus can achieve the same effect as the above-described implementation method.

[0136] In the case of using integrated units, the system 70, which expands memory via a serial interface, can also... Figure 8 The system 80 shown, which expands memory via a serial interface, includes a processing module and a storage module. The processing module can be used to control and manage the operation of the system 70, for example, it can support the system 70 in executing the steps performed by the rate negotiation unit 701, the rate acquisition unit 702, and the initialization unit 703. The storage module can support the system 70 in storing program code and data.

[0137] The processing module can be a processor or a controller. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory.

[0138] In one embodiment, when the processing module is a processor and the storage module is a memory, the processing module may be a processor / controller / control circuit in the main chip of this application, and / or a processor / controller / control circuit in the cache chip. The storage module may be the memory in the main chip and / or the memory in the cache chip. The system for expanding memory via a serial interface involved in this embodiment can be a system with... Figure 2 The system with the structure shown.

[0139] This application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, including computer instructions. When the one or more processors execute the computer instructions, the electronic device performs the aforementioned method steps to implement the unified clock frequency method in the above embodiments.

[0140] Embodiments of this application also provide a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the method for a unified clock frequency in the above embodiments.

[0141] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the method for a unified clock frequency executed by the electronic device in the above embodiments.

[0142] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the method of the electronic device executing the unified clock frequency in the above method embodiments.

[0143] In this embodiment, the system, electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding methods provided above, and will not be repeated here.

[0144] Another embodiment of this application provides a system that may include the aforementioned main chip, cache chip, and multiple memory chips, and can be used to implement the aforementioned method of unified clock frequency.

[0145] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0149] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for unifying clock frequencies, characterized in that, A system for expanding memory via a serial interface, the system comprising a main chip, a cache chip, and at least one memory chip coupled to the cache chip, wherein a first phase-locked loop coupled to the serial interface in the main chip and a second phase-locked loop coupled to the serial interface in the cache chip share the same clock source, and both the dual in-line memory module interface in the cache chip and the serial interface in the cache chip are coupled to the second phase-locked loop, the method comprising: After the system controls the main chip and the cache chip to complete the serial interface initialization, it performs the first rate negotiation between the main chip and the cache chip to determine the first target rate for the main chip to access the cache chip. After the system controls the main chip to initialize the cache chip at the first target rate, it determines the second target rate supported by the dual in-line memory module interface between the cache chip and the memory chip. The system configures the clock frequency of the first phase-locked loop in the main chip and the clock frequency of the second phase-locked loop in the cache chip to a clock frequency corresponding to the second target rate, and controls the main chip and the cache chip to complete a second rate negotiation.

2. The method according to claim 1, characterized in that, After the main chip and the cache chip complete the serial interface initialization, the first rate negotiation between the main chip and the cache chip is performed to determine the first target rate for the main chip to access the cache chip, including: The first phase-locked loop in the main chip and the second phase-locked loop in the cache chip are controlled to perform frequency multiplication based on the same reference clock to obtain the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop. The clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are the same. The transmission rate of the serial interface in the main chip is determined based on the clock frequency of the first phase-locked loop, and the transmission rate of the serial interface in the cache chip is determined based on the clock frequency of the second phase-locked loop. The first rate negotiation between the main chip and the cache chip is performed based on the transmission rate of the serial interface of the main chip and the transmission rate of the serial interface in the cache chip. If the negotiation is successful, the transmission rate of the serial interface in the main chip and the transmission rate of the serial interface in the cache chip are determined as the first target rate for the main chip to access the cache chip.

3. The method according to claim 1 or 2, characterized in that, After the main chip initializes the cache chip at the first target rate, the second target rate supported by the dual in-line memory (DIM) interface between the cache chip and the memory chip is determined to include: The serial interface of the main chip is controlled to access the registers of the cache chip at the first target rate to initialize the registers of the cache chip; The cache chip is controlled to access the memory chip that is connected to the cache chip through the dual in-line memory module interface, the highest speed supported by the dual in-line memory module interface is determined, and the highest frequency supported by the dual in-line memory module interface is taken as the second target speed. The cache chip is controlled to record the second target rate in the register of the cache chip.

4. The method according to claim 3, characterized in that, The step of configuring the clock frequency of the first phase-locked loop in the main chip and the clock frequency of the second phase-locked loop in the cache chip to clock frequencies corresponding to the second target rate, and controlling the main chip and the cache chip to complete the second rate negotiation includes: The main chip is controlled to read the second target rate from the register of the cache chip; The main chip is controlled to initialize the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop according to the second target rate, so that the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are clock frequencies corresponding to the second target rate. The serial interface of the main chip and the serial interface of the cache chip are controlled to perform the second rate negotiation at the second target rate.

5. The method according to claim 1 or 2, characterized in that, When the serial interface of the main chip and the serial interface of the cache chip negotiate the rate, they can support any specified integer rate.

6. A system for expanding memory via a serial interface, the system comprising a main chip, a cache chip, and at least one memory chip coupled to the cache chip, characterized in that, The first phase-locked loop coupled to the serial interface in the main chip and the second phase-locked loop coupled to the serial interface in the cache chip share the same clock source. Both the dual in-line memory (DIM) module interface and the serial interface in the cache chip are coupled to the second phase-locked loop. Wherein: The main chip is used to complete the serial interface initialization with the cache chip and complete the first rate negotiation with the cache chip to determine the first target rate for the main chip to access the cache chip. After initializing the cache chip at the first target rate, determine the second target rate supported by the dual in-line memory module interface between the cache chip and the memory chip; Configure the clock frequency of the first phase-locked loop in the main chip to a clock frequency corresponding to the second target rate; The cache chip is configured to set the clock frequency of the second phase-locked loop in the cache chip to a clock frequency corresponding to the second target rate. The main chip is also used to complete a second rate negotiation with the cache chip.

7. The system according to claim 6, characterized in that, The main chip is used to control the first phase-locked loop to perform frequency multiplication based on a reference clock of the same origin, so as to obtain the clock frequency at which the first phase-locked loop operates. The cache chip is used to control the second phase-locked loop to perform frequency multiplication based on a reference clock of the same origin to obtain the clock frequency at which the second phase-locked loop operates. The clock frequency at which the first phase-locked loop operates is the same as the clock frequency at which the second phase-locked loop operates. The main chip is used to determine the transmission rate of the serial interface in the main chip based on the clock frequency of the first phase-locked loop. The cache chip is used to determine the transmission rate of the serial interface in the cache chip based on the clock frequency of the second phase-locked loop. The main chip is used to perform the first rate negotiation between the main chip and the cache chip based on the transmission rate of the serial interface of the main chip and the transmission rate of the serial interface in the cache chip. When the negotiation is successful, the transmission rate of the serial interface in the main chip is determined to be the first target rate for the main chip to access the cache chip; The cache chip is configured to determine, upon successful negotiation, that the transmission rate of the serial interface in the cache chip is the first target rate at which the main chip accesses the cache chip.

8. The system according to claim 6 or 7, characterized in that, The main chip is used to control the serial interface of the main chip to access the registers of the cache chip at the first target rate, so as to initialize the registers of the cache chip; The cache chip is used to access the memory chip that is connected to the cache chip through the dual in-line memory module interface, determine the highest speed supported by the dual in-line memory module interface, and take the highest frequency supported by the dual in-line memory module interface as the second target speed. The second target rate is recorded in the register of the cache chip.

9. The system according to claim 8, characterized in that, The main chip is used to read the second target rate from the register of the cache chip; The clock frequencies of the first phase-locked loop and the second phase-locked loop are initialized according to the second target rate, so that the clock frequencies of the first phase-locked loop and the second phase-locked loop are clock frequencies corresponding to the second target rate. The serial interface of the main chip and the serial interface of the cache chip are controlled to perform the second rate negotiation at the second target rate.

10. The system according to claim 6 or 7, characterized in that, When the serial interface of the main chip and the serial interface of the cache chip negotiate the rate, they can support any specified integer rate.

11. A frequency control device, characterized in that, The frequency control device is applied to a system that expands memory via a serial interface. The system includes a main chip, a cache chip, and at least one memory chip coupled to the cache chip. The clocks of a first phase-locked loop (PLL) coupled to the serial interface in the main chip and a second PLL coupled to the serial interface in the cache chip are from the same source. Both the dual in-line memory (DIM) interface and the serial interface in the cache chip are coupled to the second PLL. The frequency control device includes: A rate negotiation unit is used to control the main chip and the cache chip to perform the first rate negotiation between the main chip and the cache chip after the serial interface initialization is completed, so as to determine the first target rate for the main chip to access the cache chip; A rate acquisition unit is used to control the main chip to initialize the cache chip at the first target rate, and then determine the second target rate supported by the interface between the cache chip and the memory chip. The rate negotiation unit is further configured to configure the clock frequency of the first phase-locked loop in the main chip and the clock frequency of the second phase-locked loop in the cache chip to clock frequencies corresponding to the second target rate, and control the main chip and the cache chip to complete the second rate negotiation.

12. The frequency control device according to claim 11, characterized in that, The rate negotiation unit is used for: The first phase-locked loop in the main chip and the second phase-locked loop in the cache chip are controlled to perform frequency multiplication based on the same reference clock to obtain the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop. The clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are the same. The transmission rate of the serial interface in the main chip is determined based on the clock frequency of the first phase-locked loop, and the transmission rate of the serial interface in the cache chip is determined based on the clock frequency of the second phase-locked loop. The first rate negotiation between the main chip and the cache chip is performed based on the transmission rate of the serial interface of the main chip and the transmission rate of the serial interface in the cache chip. If the negotiation is successful, the transmission rate of the serial interface in the main chip and the transmission rate of the serial interface in the cache chip are determined as the first target rate for the main chip to access the cache chip.

13. The frequency control device according to claim 11 or 12, characterized in that, The rate acquisition unit is used for: The serial interface of the main chip is controlled to access the registers of the cache chip at the first target rate to initialize the registers of the cache chip; The cache chip is controlled to access the memory chip that is connected to the cache chip through the dual in-line memory module interface, the highest speed supported by the dual in-line memory module interface is determined, and the highest frequency supported by the dual in-line memory module interface is taken as the second target speed. The cache chip is controlled to record the second target rate in the register of the cache chip.

14. The frequency control device according to claim 13, characterized in that, The rate negotiation unit is used for: The main chip is controlled to read the second target rate from the register of the cache chip; The main chip is controlled to initialize the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop according to the second target rate, so that the clock frequency of the first phase-locked loop and the clock frequency of the second phase-locked loop are clock frequencies corresponding to the second target rate. The serial interface of the main chip and the serial interface of the cache chip are controlled to perform the second rate negotiation at the second target rate.

15. The frequency control device according to claim 11 or 12, characterized in that, When the serial interface of the main chip and the serial interface of the cache chip negotiate the rate, they can support any specified integer rate.

16. A computer-readable storage medium, characterized in that, Includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method described in any one of claims 1-5.

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