An SRAM PUF security chip

Abstract

The application discloses an SRAM PUF security chip and relates to the field of integrated circuits.The SRAM PUF security chip comprises an SRAM unit, a first tri-state gate, a second tri-state gate, a third tri-state gate and a first NOT gate.The input ends of the first tri-state gate, the second tri-state gate and the third tri-state gate are connected with the power supply of the security chip.The control ends of the first tri-state gate and the second tri-state gate are connected with a pre-charge enable signal.The input end of the first NOT gate is connected with the pre-charge enable signal.The output end of the first NOT gate is connected with the control end of the third tri-state gate.The output end of the first tri-state gate is connected with the bit line of the SRAM unit.The output end of the second tri-state gate is connected with the negation bit line of the SRAM unit.The output end of the third tri-state gate is connected with the power supply of the SRAM unit.The application can generate twice the number of stimulus-response relationships under the condition of equivalent hardware resources, and expand the application scenarios of the SRAM PUF.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an SRAM PUF security chip. Background Technology

[0002] Cryptography is the fundamental support for ensuring information security. Traditional cryptography uses non-volatile memory to store keys, which is relatively vulnerable. There are many feasible physical attack methods available, such as micro-probes and side-channel attacks, making the stored keys susceptible to theft and tampering.

[0003] To address the aforementioned issues, Physically Unclonable Functions (PUFs) are considered an effective means to improve computer system security and resist physical attacks. PUF security chips utilize unavoidable random process variations during integrated circuit manufacturing to generate a unique chip identifier, serving as a "physical fingerprint." Since process variations during manufacturing are generally uncontrollable, the "physical fingerprint" of a PUF chip is unpredictable and difficult to clone. Furthermore, the "physical fingerprint" of a PUF chip is readable upon power-on and lost upon power-off, further enhancing its security. Finally, the "physical fingerprint" of a PUF chip relies entirely on the physical characteristics of the chip itself, thus eliminating the need for additional memory to store identity information. This gives PUF chips the advantage of low hardware cost, making them suitable for lightweight security protection in resource-scarce application scenarios. These advantages enable PUF chips to provide an inherent and unique root of trust in applications such as identity authentication, information encryption, and chip watermarking, showing broad development prospects in hardware security and IoT security.

[0004] Currently, SRAM PUFs, with Static Random Access Memory (SRAM) as their core circuitry, are a typical type of PUF security chip. SRAM PUFs utilize the randomness of data storage in SRAM cells upon power-up and use the initial power-up value of a specific memory cell as a random response by setting an stimulus. SRAM PUFs exhibit high reliability, providing relatively stable response outputs under the influence of factors such as temperature and supply voltage. However, the number of stimulus-response relationships supported by SRAM PUFs is limited; the number of stimulus-response relationships increases only linearly with the number of SRAM cells, restricting the application scenarios of SRAM PUFs. Summary of the Invention

[0005] Based on this, embodiments of the present invention provide an SRAM PUF security chip that can generate twice the number of stimulus-response relationships under the same hardware resources, thereby expanding the application scenarios of SRAM PUF.

[0006] To achieve the above objectives, embodiments of the present invention provide the following solutions:

[0007] An SRAM PUF security chip includes: an SRAM cell and a first precharge control circuit; the first precharge control circuit includes: a first tri-state gate, a second tri-state gate, a third tri-state gate and a first NOT gate;

[0008] The input terminals of the first tri-state gate, the second tri-state gate, and the third tri-state gate are all connected to a first power supply; the control terminals of the first and second tri-state gates are both connected to a precharge enable signal; the input terminal of the first NOT gate is connected to the precharge enable signal; the output terminal of the first NOT gate is connected to the control terminal of the third tri-state gate; the output terminal of the first tri-state gate is connected to the bit line of the SRAM cell; the output terminal of the second tri-state gate is connected to the inverted bit line of the SRAM cell; the output terminal of the third tri-state gate is connected to a second power supply; the first power supply serves as the power supply for the security chip; and the second power supply serves as the power supply for the SRAM cell.

[0009] Optionally, the SRAM cell includes: a latch cell, a first transfer transistor, and a second transfer transistor;

[0010] The gates of the first and second transmission transistors are both connected to the word line; the drain of the first transmission transistor is connected to the bit line; and the drain of the second transmission transistor is connected to the inverted bit line.

[0011] The first input terminal of the latch unit is connected to the second power supply; the second input terminal of the latch unit is connected to the source of the first transmission transistor; the third input terminal of the latch unit is connected to the source of the second transmission transistor; the logic voltage values ​​of the second input terminal and the third input terminal are opposite.

[0012] Optionally, the latch unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0013] The first transistor and the third transistor are connected to form a second NOT gate; the second transistor and the fourth transistor are connected to form a third NOT gate; the input terminal of the second NOT gate is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the output terminal of the second NOT gate; the input terminal of the second NOT gate serves as the second input terminal of the latch unit; the input terminal of the third NOT gate serves as the third input terminal of the latch unit; both the second NOT gate and the third NOT gate are connected to the second power supply.

[0014] The present invention also provides an SRAM PUF security chip, comprising: an SRAM array and a second precharge circuit; the SRAM array comprising: 2 m The SRAM cells are arranged in rows and n columns; the second precharge circuit includes: n tri-state gate cells, a fourth tri-state gate, and a fourth NOT gate;

[0015] The tri-state gate unit includes: a fifth tri-state gate and a sixth tri-state gate; one column of SRAM cells is connected to one tri-state gate unit;

[0016] For the Mth row and Mth column of the SRAM array, the word line connections of all SRAM cells form a single word line connection terminal; 1 ≤ M ≤ 2 m ;

[0017] For the Nth column of the SRAM array, the bit lines of all SRAM cells in the Nth column are connected to form a bit line connection terminal, and the bit lines of all SRAM cells in the Nth column are connected to form a bit line connection terminal; the control terminals of the fifth and sixth tri-state gates in the Nth tri-state gate cell are both connected to the precharge enable signal; the input terminals of the fifth and sixth tri-state gates in the Nth tri-state gate cell are both connected to the first power supply; the output terminal of the fifth tri-state gate in the Nth tri-state gate cell is connected to the bit line connection terminal; the output terminal of the sixth tri-state gate in the Nth tri-state gate cell is connected to the bit line connection terminal; 1≤N≤n;

[0018] The input terminal of the fourth NOT gate is connected to the precharge enable signal; the output terminal of the fourth NOT gate is connected to the control terminal of the fourth tri-state gate; the input terminal of the fourth tri-state gate is connected to the first power supply; the output terminal of the fourth tri-state gate is connected to the second power supply; the first power supply serves as the power supply for the security chip; and the second power supply serves as the power supply for the SRAM cell.

[0019] Optionally, the SRAM PUF security chip further includes: an m-bit address decoder;

[0020] The output of the address decoder is connected to all word line connectors.

[0021] Optionally, the SRAM PUF security chip further includes: a data controller;

[0022] The data controller includes: n bidirectional input / output interfaces; each bidirectional input / output interface is connected to a tri-state gate unit.

[0023] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0024] The SRAM PUF security chip proposed in this invention adds a pre-charge control circuit to the chip, thereby generating variable stimulus-response relationships by pre-charging the SRAM cells when the chip is powered on, increasing the number of stimulus-response relationships. This invention utilizes pre-charging of SRAM cells before power-on to generate variable stimulus-response relationships. Compared to traditional SRAM PUF security chips, it can generate twice the number of stimulus-response relationships with the same hardware resources, thereby expanding the application scenarios of SRAM PUF. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 The circuit schematic diagram of the SRAM PUF security chip provided in Embodiment 1 of the present invention;

[0027] Figure 2 The circuit schematic diagram of the SRAM cell provided in Embodiment 1 of the present invention;

[0028] Figure 3 This is a waveform diagram illustrating the changes in control signals and initial power-on values ​​of the SRAM cell provided in Embodiment 1 of the present invention under two conditions: no pre-charging and pre-charging.

[0029] Figure 4 This is a circuit schematic diagram of the SRAM PUF security chip provided in Embodiment 2 of the present invention;

[0030] Figure 5 This is a distribution diagram of the power-on initial value changes of the SRAM array provided in Embodiment 2 of the present invention under two conditions: no pre-charging and pre-charging.

[0031] Figure 6 A schematic diagram of the pin configuration of the SRAM PUF security chip (capacity 1KB) provided in Embodiment 2 of the present invention. Detailed Implementation

[0032] The technical solutions of the present invention will now be described with reference to the accompanying drawings in the embodiments of the present invention.

[0033] To address the limited number of stimulus-response relationships in SRAM PUF chips, this invention proposes incorporating a pre-charge control circuit into the SRAM PUF security chip. Upon chip power-up, a pre-charge operation is performed on the SRAM cells, modifying circuit parameters such as the transistor drive current within the SRAM cells to reconstruct the chip. This allows for different response outputs based on the same SRAM PUF chip and receiving the same stimulus input, depending on whether pre-charging is performed or not. The output of the pre-charge control circuit is connected to the data input terminals of all SRAM cells; one input terminal of the pre-charge control circuit is connected to the chip's power input pin, and the other input terminal is connected to an additional signal input pin of the chip, used to control whether pre-charging of the SRAM cells is performed.

[0034] Therefore, the purpose of this invention is to provide an SRAM PUF security chip that generates variable stimulus-response relationships by adding a precharge control circuit to the chip, thereby generating twice the number of stimulus-response relationships under the same hardware resources, thus expanding the application scenarios of SRAM PUF.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] See Figure 1 The SRAM PUF security chip in this embodiment includes: an SRAM cell 100 and a first precharge control circuit; the first precharge control circuit includes: a first tri-state gate 101, a second tri-state gate 102, a third tri-state gate 103 and a first NOT gate 104.

[0038] The input terminals of the first tri-state gate 101, the second tri-state gate 102, and the third tri-state gate 103 are all connected to the first power supply VDD; the control terminals of the first tri-state gate 101 and the second tri-state gate 102 are both connected to the precharge enable signal ENB; the input terminal of the first NOT gate 104 is connected to the precharge enable signal; the output terminal of the first NOT gate 104 is connected to the control terminal of the third tri-state gate 103; the output terminal of the first tri-state gate 101 is connected to the bit line BL of the SRAM cell 100; the output terminal of the second tri-state gate 102 is connected to the inverted bit line BL of the SRAM cell 100; and the output terminal of the third tri-state gate 103 is connected to the second power supply VDD. SRAM The connection is as follows: the first power supply serves as the power supply for the security chip; the second power supply serves as the power supply for the SRAM unit 100; the SRAM unit 100 is also connected to the word line WL.

[0039] In one example, see Figure 2 The SRAM cell 100 includes: a latch cell, a first transmission transistor T5, and a second transmission transistor T6.

[0040] The gates of the first transmission transistor T5 and the second transmission transistor T6 are both connected to the word line WL; the drain of the first transmission transistor T5 is connected to the bit line BL; the drain of the second transmission transistor T6 is connected to the inverted bit line. connect.

[0041] The first input terminal of the latch unit is connected to the second power supply VDD. SRAM The latch unit is connected to the source of the first transmission transistor T5; the latch unit is connected to the source of the second transmission transistor T6; the logic voltage values ​​of the second input and the third input are opposite.

[0042] The latch unit will be described below.

[0043] Please see again Figure 2 The latch unit includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0044] The first transistor T1 and the third transistor T3 are connected to form a second NOT gate; the second transistor T2 and the fourth transistor T4 are connected to form a third NOT gate; the input terminal of the second NOT gate is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the output terminal of the second NOT gate; the input terminal of the second NOT gate serves as the second input terminal a (also called node a) of the latch unit; the input terminal of the third NOT gate serves as the third input terminal b (also called node b) of the latch unit; both the second NOT gate and the third NOT gate are connected to the second power supply VDD. SRAM connect.

[0045] In this example, the SRAM cell 100 includes six transistors; the first transistor T1 and the third transistor T3 form a NOT gate, and the second transistor T2 and the fourth transistor T4 form another NOT gate. The output of one NOT gate is connected to the input of the other NOT gate to form a latch cell, so that nodes a and b have opposite logic voltage values.

[0046] The first transmission transistor T5 and the second transmission transistor T6 are controlled by the word line signal WL, respectively connecting node a to the bit line BL and node b to the inverted bit line. Bit line BL and inverted bit line It connects to a bidirectional input / output interface. Data reading or writing to SRAM cell 100 is performed via bit line BL. To achieve this.

[0047] When SRAM cell 100 is powered on, the power input terminal VDD of SRAM cell 100... SRAM The second power supply supplies power to the cell, and the initial logic voltage values ​​of node a and node b are the initial power-on values ​​of the SRAM cell 100. Different SRAM cells 100 have different initial power-on values. This is because the initial power-on value is determined by the driving capability of each transistor (T1, T2, T3, and T4) in the SRAM cell 100, which is affected by random process deviations during circuit manufacturing.

[0048] The first pre-charge control circuit includes three tri-state gates and one NOT gate.

[0049] The first tri-state gate 101 and the second tri-state gate 102 are controlled by the precharge enable signal ENB, and only when ENB=1, the bit line BL and the inverted bit line BL of the SRAM cell 100 are connected to the chip power input terminal VDD (i.e., the first power supply).

[0050] The first NOT gate 104 inverts the precharge enable signal ENB and controls the third tri-state gate 103: only when ENB = 0, it connects the chip power input terminal VDD to the SRAM cell 100 power input terminal VDD. SRAM Connect to supply power to SRAM cell 100.

[0051] The changes in control signals and initial power-on values ​​of SRAM cell 100 under two conditions: no pre-charging and pre-charging. Figure 3 As shown.

[0052] See Figure 3 In part (a), when no precharge is performed, the precharge enable signal ENB = 0, and the bit line BL and the inverted bit line of SRAM cell 100 are... The chip is not connected to the chip power input terminal VDD, and the word line signal WL = 0, thus disconnecting nodes a and b from the two bit lines. After the chip is powered on, the chip power input terminal VDD is connected to the SRAM cell 100 power input terminal VDD. SRAM Power is supplied to the SRAM cell 100. The initial power-on value of the SRAM cell 100 is then determined by the driving capabilities of transistors T1, T2, T3, and T4. In this example, the initial power-on values ​​of node a and node b without pre-charging are logic 0 and logic 1, respectively.

[0053] See Figure 3In part (b), during pre-charging, both the pre-charge enable signal ENB and the word line signal WL are initially set to 1. During this period, the chip power input terminal VDD is connected to node a and node b via two bit lines BL and BL' respectively, and pre-charging is performed on nodes a and b after the chip is powered on. Simultaneously, the SRAM cell 100 power input terminal VDD... SRAM Disconnected from the chip's power input terminal VDD, therefore VDD SRAM During pre-charge, the voltage values ​​of nodes a and b are not affected. Because the driving capabilities of the first transmission transistor T5 and the second transmission transistor T6 in SRAM cell 100 are affected by random process variations during circuit manufacturing and are therefore random, random voltage differences will exist between nodes a and b within the same pre-charge time. After pre-charge is complete, the pre-charge enable signal ENB = 0, and the word line signal WL = 0. At this time, the chip power input VDD begins to flow through the SRAM cell 100 power input VDD. SRAM Power is supplied to the SRAM cell 100. However, the voltage difference between node a and node b due to precharging may change the original power-on initial values ​​of these two nodes. In this example, the power-on initial values ​​of node a and node b during precharging are logic 1 and logic 0, respectively, which are the opposite of those without precharging.

[0054] Example 2

[0055] See Figure 4 The SRAM PUF security chip provided in this embodiment includes: an SRAM array and a second pre-charge circuit; the SRAM array includes: 2 m The SRAM cells 100 are arranged in rows and n columns; the second precharge circuit includes: n tri-state gate cells, a fourth tri-state gate 403 and a fourth NOT gate 404.

[0056] The tri-state gate unit includes: a fifth tri-state gate 401 and a sixth tri-state gate 402; a column of SRAM cells 100 is connected to a tri-state gate unit.

[0057] For the Mth row and Mth column of the SRAM array, the word line connections of all SRAM cells 100 form a single word line connection terminal; 1 ≤ M ≤ 2 m .

[0058] For the Nth column of the SRAM array, the bit line connections of all SRAM cells 100 in the Nth column form a bit line connection terminal, and the bit line inversion connections of all SRAM cells 100 in the Nth column form a bit line inversion connection terminal; the control terminals of the fifth tri-state gate 401 and the sixth tri-state gate 402 in the Nth tri-state gate cell are both connected to the precharge enable signal; the input terminals of the fifth tri-state gate 401 and the sixth tri-state gate 402 in the Nth tri-state gate cell are both connected to the first power supply; the output terminal of the fifth tri-state gate 401 in the Nth tri-state gate cell is connected to the bit line connection terminal; the output terminal of the sixth tri-state gate 402 in the Nth tri-state gate cell is connected to the bit line inversion connection terminal; 1≤N≤n.

[0059] The input terminal of the fourth NOT gate 404 is connected to the precharge enable signal; the output terminal of the fourth NOT gate 404 is connected to the control terminal of the fourth tri-state gate 403; the input terminal of the fourth tri-state gate 403 is connected to the first power supply; the output terminal of the fourth tri-state gate 403 is connected to the second power supply; the first power supply serves as the power supply for the security chip; and the second power supply serves as the power supply for the SRAM cell 100.

[0060] In this example, please still refer to Figure 4 The SRAM PUF security chip further includes: an m-bit address decoder 405 (A0...A...). m-1 ) and data controller 406.

[0061] The output of the address decoder 405 is connected to all word line connection terminals.

[0062] The data controller 406 includes: n bidirectional input / output interfaces (corresponding to D0...D1). n-1 One of the input / output bidirectional interfaces is connected to a tri-state gate unit.

[0063] Address decoder 405 enables the word line signal WL of a specific row in the array by decoding the received address. A maximum of 2 m-bit addresses can control 2 m Row-oriented SRAM array.

[0064] Each column of SRAM cells 100 shares two bit lines BL and Therefore, two tri-state gates (the fifth tri-state gate 401 and the sixth tri-state gate 402) are used to uniformly precharge all SRAM cells 100 in each column. All SRAM cells 100 in the array share the same power input terminal VDD. SRAM Therefore, a fourth tri-state gate 403 and a fourth NOT gate 404 are used to control the power input terminals of all SRAM cells 100.

[0065] The data controller 406 has n bidirectional input / output interfaces, enabling the reading and writing of n-bit binary numbers. Each bidirectional input / output interface connects to the bit lines BL of a specific column in the SRAM array. This system enables data reading and writing. Other input signals include the chip select signal CS, the read enable signal OE, and the write enable signal WE. The SRAM array can only perform read and write operations when the chip select signal CS is enabled. For data reading operations, OE must be enabled and WE must be disabled; for data writing operations, WE must be enabled and OE must be disabled. Both n and n can be greater than 1; the values ​​of m and n are independent and have no fixed relationship.

[0066] The changes in initial power-on values ​​of the SRAM array under two conditions: no pre-charge and pre-charge. Figure 5 As shown, Figure 5 Part (a) shows the change in initial power-on values ​​without pre-charging. Figure 5 Section (b) illustrates the change in initial power-on values ​​under pre-charging conditions. In this example, approximately 40% of the SRAM cells 100 have different initial power-on values ​​in both the case of no pre-charging and the case of pre-charging. The distribution of SRAM cells 100 with changing initial power-on values ​​is random and unpredictable. Pre-charging enables the reconstruction of the original stimulus-response relationship of the SRAM PUF.

[0067] SRAM PUF security chip pin configuration as follows Figure 6 As shown, in this example, the SRAM PUF contains 1KB of SRAM cells 100, capable of reading or writing 8-bit binary numbers at a time. Therefore, the chip has a total of One pin (pins 1 to 10) provides address input, and eight pins (pins 16 to 23) serve as bidirectional data input / output interfaces. Pins 11, 12, 14, 15, and 24 interface to the chip select signal CS, power ground GND, read enable signal OE, write enable signal WE, and chip power input VDD, respectively. Pin 13 is an additional pin that needs to be connected to the precharge enable signal ENB.

[0068] This embodiment mainly introduces the differences from Embodiment 1. For the similarities, please refer to Embodiment 1, and will not be repeated here.

[0069] In existing SRAM PUF security chips, each SRAM cell has a specific power-on initial value, thus generating only a single response output. The SRAM PUF security chips of all the embodiments described above are reconfigurable SRAM PUF security chips, offering the advantage of low cost. Specifically, the SRAM PUF security chip of this invention, by incorporating a pre-charge control circuit, enables some SRAM cells to generate different power-on initial values ​​when pre-charging is performed and when not pre-charging. Furthermore, the distribution of SRAM cells with changing power-on initial values ​​is random and unpredictable. Therefore, with the same number of SRAM cells, compared to existing SRAM PUF security chips, the SRAM PUF security chip proposed in this application can reconfigure the circuit through pre-charging, thereby generating twice the number of stimulus-response relationships. In other words, to achieve the same number of stimulus-response relationships, compared to existing SRAM PUF security chips, the SRAM PUF security chip proposed in this application only needs to include half the number of SRAM cells, thus offering the advantage of low cost.

[0070] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0071] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An SRAM PUF security chip, characterized in that, include: SRAM cell and first precharge control circuit; The first pre-charge control circuit includes: a first tri-state gate, a second tri-state gate, a third tri-state gate, and a first NOT gate; The input terminals of the first tri-state gate, the second tri-state gate, and the third tri-state gate are all connected to a first power supply; the control terminals of the first and second tri-state gates are both connected to a precharge enable signal; the input terminal of the first NOT gate is connected to the precharge enable signal; the output terminal of the first NOT gate is connected to the control terminal of the third tri-state gate; the output terminal of the first tri-state gate is connected to the bit line of the SRAM cell; the output terminal of the second tri-state gate is connected to the inverted bit line of the SRAM cell; the output terminal of the third tri-state gate is connected to a second power supply; the first power supply serves as the power supply for the security chip; the second power supply serves as the power supply for the SRAM cell. The SRAM cell includes: a latch cell, a first transfer transistor, and a second transfer transistor; The gates of the first and second transmission transistors are both connected to the word line; the drain of the first transmission transistor is connected to the bit line; and the drain of the second transmission transistor is connected to the inverted bit line. The first input terminal of the latch unit is connected to the second power supply; the second input terminal of the latch unit is connected to the source of the first transmission transistor; the third input terminal of the latch unit is connected to the source of the second transmission transistor; the logic voltage values ​​of the second input terminal and the third input terminal are opposite; the second input terminal of the latch unit is node a, and the third input terminal of the latch unit is node b; When precharge is not performed, the precharge enable signal ENB=0, and the bit line BL and the inverted bit line of the SRAM cell are... The chip is not connected to the chip power input terminal VDD, and the word line signal WL=0, thus disconnecting nodes a and b from the two bit lines; after the chip is powered on, the chip power input terminal VDD is connected to the SRAM cell power input terminal VDD. SRAM Power is supplied to the SRAM cell; the initial power-on values ​​of node a and node b without pre-charging are logic 0 and logic 1, respectively. During pre-charging, both the pre-charge enable signal ENB and the word line signal WL are initially set to 1. During this period, the chip's power input VDD will be connected via two bit lines BL and... It is connected to nodes a and b respectively, and pre-charges nodes a and b after the chip is powered on; simultaneously, the SRAM cell power input terminal VDD... SRAM Disconnected from the chip's power input terminal VDD, therefore VDD SRAM During pre-charge, the voltage values ​​of nodes a and b are not affected. However, due to the random process variations in the first and second transfer transistors within the SRAM cell, a random voltage difference will exist between nodes a and b within the same pre-charge time. After pre-charge, the pre-charge enable signal ENB = 0, and the word line signal WL = 0. At this point, the chip power input VDD begins to flow through the SRAM cell power input VDD. SRAM Power is supplied to the SRAM cell; the initial power-on values ​​of nodes a and b during precharging are logic 1 and logic 0, respectively, which are the opposite of those during non-precharging.

2. The SRAM PUF security chip according to claim 1, characterized in that, The latch unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The first transistor and the third transistor are connected to form a second NOT gate; the second transistor and the fourth transistor are connected to form a third NOT gate; the input terminal of the second NOT gate is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the output terminal of the second NOT gate; the input terminal of the second NOT gate serves as the second input terminal of the latch unit; the input terminal of the third NOT gate serves as the third input terminal of the latch unit; both the second NOT gate and the third NOT gate are connected to the second power supply.

3. An SRAM PUF security chip, characterized in that, include: SRAM array and second precharge circuit; The SRAM array includes: 2 m The SRAM cells are arranged in rows and n columns; the second precharge circuit includes: n tri-state gate cells, a fourth tri-state gate, and a fourth NOT gate; The tri-state gate unit includes: a fifth tri-state gate and a sixth tri-state gate; one column of SRAM cells is connected to one tri-state gate unit; For the Mth row and Mth column of the SRAM array, the word line connections of all SRAM cells form a single word line connection terminal; 1 ≤ M ≤ 2 m ; For the Nth column of the SRAM array, the bit lines of all SRAM cells in the Nth column are connected to form a bit line connection terminal, and the inverted bit lines of all SRAM cells in the Nth column are connected to form an inverted bit line connection terminal; the control terminals of the fifth and sixth tri-state gates in the Nth tri-state gate unit are both connected to the precharge enable signal; the input terminals of the fifth and sixth tri-state gates in the Nth tri-state gate unit are both connected to the first power supply; the output terminal of the fifth tri-state gate in the Nth tri-state gate unit is connected to the bit line connection terminal; the output terminal of the sixth tri-state gate in the Nth tri-state gate unit is connected to the inverted bit line connection terminal; 1≤N≤n; The input terminal of the fourth NOT gate is connected to the precharge enable signal; the output terminal of the fourth NOT gate is connected to the control terminal of the fourth tri-state gate; the input terminal of the fourth tri-state gate is connected to the first power supply; the output terminal of the fourth tri-state gate is connected to the second power supply; the first power supply serves as the power supply for the security chip; the second power supply serves as the power supply for the SRAM cell. The SRAM cell includes: a latch cell, a first transfer transistor, and a second transfer transistor; The gates of the first and second transmission transistors are both connected to the word line; the drain of the first transmission transistor is connected to the bit line; and the drain of the second transmission transistor is connected to the inverted bit line. The first input terminal of the latch unit is connected to the second power supply; the second input terminal of the latch unit is connected to the source of the first transmission transistor; the third input terminal of the latch unit is connected to the source of the second transmission transistor; the logic voltage values ​​of the second input terminal and the third input terminal are opposite; the second input terminal of the latch unit is node a, and the third input terminal of the latch unit is node b; When precharge is not performed, the precharge enable signal ENB=0, and the bit line BL and the inverted bit line of the SRAM cell are... The chip is not connected to the chip power input terminal VDD, and the word line signal WL=0, thus disconnecting nodes a and b from the two bit lines; after the chip is powered on, the chip power input terminal VDD is connected to the SRAM cell power input terminal VDD. SRAM Power is supplied to the SRAM cell; the initial power-on values ​​of node a and node b without pre-charging are logic 0 and logic 1, respectively. During pre-charging, both the pre-charge enable signal ENB and the word line signal WL are initially set to 1. During this period, the chip's power input VDD will be connected via two bit lines BL and... It is connected to nodes a and b respectively, and pre-charges nodes a and b after the chip is powered on; simultaneously, the SRAM cell power input terminal VDD... SRAM Disconnected from the chip's power input terminal VDD, therefore VDD SRAM During pre-charge, the voltage values ​​of nodes a and b are not affected. However, due to the random process variations in the first and second transfer transistors within the SRAM cell, a random voltage difference will exist between nodes a and b within the same pre-charge time. After pre-charge, the pre-charge enable signal ENB = 0, and the word line signal WL = 0. At this point, the chip power input VDD begins to flow through the SRAM cell power input VDD. SRAM Power is supplied to the SRAM cell; the initial power-on values ​​of nodes a and b during precharging are logic 1 and logic 0, respectively, which are the opposite of those during non-precharging.

4. The SRAM PUF security chip according to claim 3, characterized in that, Also includes: m-bit address decoder; The output of the address decoder is connected to all word line connectors.

5. The SRAM PUF security chip according to claim 3, characterized in that, Also includes: Data controller; The data controller includes: n bidirectional input / output interfaces; One of the aforementioned bidirectional input / output interfaces is connected to a tri-state gate unit.

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