Graphics processing unit instantiation control

Abstract

Embodiments of the present disclosure relate to graphics processing unit instantiation control. Graphics processing unit instantiation control techniques are described that overcome conventional challenges to extend functionality provided via graphics processing units. In one example, these techniques support ordering primitives within respective instances of a single draw call made to a graphics processing unit. This is performed by ordering primitives within respective instances corresponding to polygons for rendering. The ordering of primitives overcomes limitations of conventional techniques and reduces visual artifacts by supporting correct overlap and z ordering of instances.

Description

Background Technology

[0001] Digital images rendered by computing devices comprise various types of digital objects, examples of which include raster objects and vector objects. A raster object is defined as a matrix (i.e., a grid) of pixels with corresponding color values. However, because raster objects are pixel-based, they are resolution-dependent. Thus, changes in scaling levels result in corresponding changes in the size of the pixels used to form the raster object, which in practice leads to visual artifacts such as blurring and pixelation. Furthermore, storing raster objects consumes significant memory resources of computing devices to define each pixel and store these pixel-specific color values.

[0002] To address this issue, mathematically defined vector objects were developed, allowing them to be scaled to different resolutions without loss of quality or the introduction of visual artifacts. However, some of the features offered by traditional graphics processing units (GPUs) that improve the efficiency of digital image rendering are unavailable for vector objects. For example, some functions are performed in pixel space and are therefore unavailable in vector space. Consequently, employing conventional techniques for overcoming this challenge in the central processing unit (CPU) instead of the GPU offsets the performance advantages that could be gained by using a GPU. Summary of the Invention

[0003] This paper describes graphics processing unit (GPU) instantiation control techniques that overcome conventional challenges to extend the functionality offered by the GPU. In one example, these techniques support the sorting of primitives within the corresponding instance of a single draw call to the GPU. This is performed by sorting the primitives within the corresponding instance that correspond to the polygons used for rendering. Primitive sorting overcomes the limitations of conventional techniques and reduces visual artifacts by supporting correct overlap and z-ordering.

[0004] This invention summary presents some concepts in a simplified form, which will be further described in the detailed implementations below. Therefore, this summary is not intended to identify essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter. Attached Figure Description

[0005] Figure 1 A digital media environment configured to perform instantiation control of a graphics processing unit is described.

[0006] Figure 2 It is depicted in more detail. Figure 1 This is an example of how the browser's rendering engine operates.

[0007] Figure 3 It is depicted in more detail. Figure 1 The system that operates the graphics processing unit.

[0008] Figure 4 It is a flowchart depicting the process in an example implementation of graphics processing unit instantiation control.

[0009] Figure 5 An example implementation is described, demonstrating the effect of rendering resolution-dependent and resolution-independent regions of the geometry of a vector object.

[0010] Figure 6 An example implementation of a simple ellipse tessellated output is described.

[0011] Figure 7 An example implementation of how data generated by tessellation of digital objects is organized and transferred to the graphics processing unit memory is described.

[0012] Figure 8 An example implementation of geometric scaling for generating antialiasing spread is described.

[0013] Figure 9 An example implementation is described, in which a single draw call is used to invoke two instances of a sample triangle from the tessellation output on the central processing unit.

[0014] Figure 10 An example of an existing technique for batch rendering is described, which uses a conventional instantiation technique for rendering additional triangles using a first instance and a second instance.

[0015] Figure 11 An example is described to determine the processing order of primitives in a given instance.

[0016] Figure 12 This describes an example of a graphics processing unit rendering primitives for a given instance to a frame buffer, following a processing order defined by the instantiation control module.

[0017] Figure 13 It describes the processing order compared to that calculated by the instantiation control module, following... Figure 10 Examples of existing technology processing sequences that lead to visual artifacts.

[0018] Figure 14 An example implementation of vertex buffer layout in an array buffer for vertex buffers is described.

[0019] Figure 15 This describes an example implementation of the mapping from vertex data to vertex shader calls.

[0020] Figure 16 An example implementation of generating anti-aliasing extensions through geometric expansion is described.

[0021] Figure 17 Depicting as Figure 16 This is part of a geometric extension shown, illustrating an example implementation of calculating the position coordinates for each vertex.

[0022] Figure 18 Examples of rendering results depicting a comparison between traditional techniques and the current techniques described in this article.

[0023] Figure 19 The illustration shows an example system including an example computing device, which represents one or more computing systems and / or devices that implement the various technologies described herein.

[0024] Specific embodiments are described with reference to the accompanying drawings. Entities shown in the drawings indicate one or more entities, and therefore the single or plural forms of entities may be used interchangeably in the discussion.

[0025] Specific implementation method

[0026] Overview

[0027] A graphics processing unit (GPU) is configured to extend the capabilities offered by a computing device, such as for creating and rendering digital content, artificial intelligence, and machine learning. GPUs are typically used in conjunction with central processing units (CPUs) as part of parallel processing to extend the functionality and speed of the features offered by the computing device. For example, a CPU is configured to support the general processing capabilities of a computing device. On the other hand, a GPU supports specific task-specific capabilities that are accelerated by GPU-based hardware designs. However, the specific capabilities of a GPU may be unavailable in certain situations, thus reducing the operational efficiency of the computing device.

[0028] Consider the example of a browser executed by a central processing unit. The browser is implemented as a set of operations specified in software executed by a processing device to access the World Wide Web. For example, a browser can be executed by a client device to access a service provider's system, thereby accessing digital services offered over the network. As the World Wide Web expands, the functionality and complexity of digital content offered via digital services also increase.

[0029] In digital services involving the creation and editing of digital content, for example, the complexity of digital objects contained within the content directly impacts the ability of computing devices to render that content. One example of this involves the rendering of vector objects, also known as vector graphics. However, traditional techniques for rendering vector objects are limited by the capabilities available to browsers, thus requiring the use of a central processing unit (CPU) to address these limitations. This is computationally inefficient and hinders the operation of computing devices.

[0030] For example, in antialiasing techniques for vector objects, an antialiasing spread is calculated at the boundaries of the vector object to reduce visual artifacts and provide a “smooth” appearance. However, conventional techniques for generating the antialiasing spread are performed at the central processing unit on a per-resolution basis. This negates any potential performance benefits provided by the graphics processing unit by rendering vector objects to “zoom in” or “zoom out” the view of digital objects.

[0031] Therefore, techniques for improving and extending the operation of computing devices are described. In one example, these techniques are configured to generate resolution-dependent anti-aliasing extensions as part of rendering vector objects using a graphics processing unit (GPU), which is impossible using conventional techniques. These techniques achieve full-resolution independent rendering by generating anti-aliasing extensions on-the-fly and in real time on the GPU. Furthermore, these techniques can be used to extend the functionality available to browsers (i.e., web interfaces) to enable them to perform advanced digital content editing, which is impossible using conventional techniques.

[0032] This is performed by sorting primitives within the corresponding instances in the drawing calls made by the graphics processing unit (GPU), in a way that reduces communication between the central processing unit (CPU) and the GPU, and enables the GPU to react to changes in resolution as part of rendering vector objects on the GPU itself. Although these techniques are described in the examples discussed below as being used with a browser, the processing efficiency and functionality they offer are also applicable to other examples of rendering digital content.

[0033] In one example, the browser receives a digital image, which is then rendered by a display device using a rendering engine for display. The digital image comprises polygons configured as vector objects. Because the graphics processing unit (GPU) is limited to understanding primitives (also called geometric primitives, such as lines, triangles, and points), the rendering engine converts the vector objects into a form that the GPU can understand. In this example, this is done by tessellizing the vector objects to form polygons (e.g., triangles). These polygons are then used as the basis for forming anti-aliasing extensions, for example, through geometric scaling, where at least two primitives are formed for each polygon to undergo anti-aliasing.

[0034] Instantiation is a rendering technique used to render multiple copies of a geometry. In an example where a digital image includes multiple digital objects configured as a blade of grass, multiple copies are rendered using a single mesh that defines the blade of grass, and variations are provided by using a transformation matrix applied to that single mesh. As a result, instantiation can be used to support a single communication from the central processing unit to invoke the graphics pipeline of the graphics processing unit to produce these multiple copies. However, in traditional instantiation techniques, a draw call is made to render one instance of “N” triangles. Because the traditional processing order of instances is defined using instance IDs, this results in the first instance for each shape being rendered, followed by the second instance for each shape (e.g., a transformed copy of the first instance), and so on. This in practice leads to errors in overlapping areas and incorrect z-ordering.

[0035] However, in the techniques described herein, the browser's rendering engine is configured to sort the primitives within the corresponding instances to overcome these conventional errors. Therefore, instead of rendering one instance of "N" triangles, draw calls are sorted to render "N" instances of each triangle sequentially. In other words, instances are formed such that the primitives corresponding to the respective input polygons are included together in a single corresponding instance. This allows primitives for a specific polygon (e.g., representing vector objects and their corresponding anti-aliasing extensions) to be rendered together sequentially, thus maintaining a z-order with correct overlap. These techniques can be used to support a variety of functions, including rendering vector objects using a browser via in-processing on the graphics processing unit, which is not possible using conventional techniques. Further discussion of these and other examples is included in the following sections and illustrated in the corresponding figures.

[0036] In the following discussion, an example environment employing the techniques described herein is described. Example procedures that can be executed in the example environment as well as in other environments are also described. Therefore, the execution of the example procedures is not limited to the example environment, and the example environment is not limited to the execution of the example procedures.

[0037] Example Environment

[0038] Figure 1 This illustration shows a digital media environment 100 that can be used in an example implementation employing the techniques described herein. The illustrated environment 100 includes a computing device 102, which can be configured in various ways.

[0039] Computing device 102, for example, may be configured as a desktop computer, laptop computer, mobile device (e.g., assumed handheld configuration, such as the illustrated tablet or mobile phone), etc. Therefore, the range of computing device 102 extends from full-resource devices with abundant memory and processor resources (e.g., personal computers, game consoles) to low-resource devices with limited memory and / or processing resources (e.g., mobile devices). Furthermore, although a single computing device 102 is shown, computing device 102 also represents multiple different devices, such as those used by enterprises to perform tasks such as… Figure 19 The “cloud-based” operation described herein can be used to implement multiple servers of the service provider system 112.

[0040] The computing device 102 includes a central processing unit 104, a graphics processing unit 106, and an example memory illustrated as a storage device 108. The central processing unit 104 is configured to execute general-purpose instructions to perform operations. For example, the central processing unit 104 includes an arithmetic logic unit (ALU) that performs logical operations, registers that provide operations to the ALU and receive the results of these operations, and a control unit that manages the fetching, decoding, and execution of instructions.

[0041] On the other hand, the graphics processing unit 106 is implemented using dedicated hardware, designed to improve efficiency through the use of a parallel architecture. This enables the graphics processing unit 106 to achieve improved efficiency by processing data blocks in parallel, for example, for image rendering, machine learning, artificial intelligence, etc. The graphics processing unit 106 is coupled to the central processing unit 104, for example, via a bus.

[0042] In this example, browser 110 (e.g., a web browser, a web interface) is illustrated to execute on central processing unit 104. Browser 110 is configured to support access to service provider system 112 via network 114 (i.e., the Internet or the World Wide Web using Uniform Resource Locators (URLs)). For example, browser 110 is configured to obtain data (e.g., a digital image 116 having a digital object 118) from a digital service performed by service provider system 112. This data is then rendered by rendering engine 120 for display on user interface 122 by display device 124.

[0043] An example of this is illustrated by executing an editing module 126 at a central processing unit 104 that communicates with an editing application 128 implemented at a digital service provider system 112. For example, the editing module 126 includes locally executable instructions described in data received from the editing application 128 via a network 114. The editing module 126 is configured to edit digital images 116, such as digital objects 118 configured as raster objects, vector objects, etc. This can be performed using operations such as editing pixels, mathematical representations, and the use of filters.

[0044] The rendering engine 120 of browser 110 is configured to call the application programming interface 130 of graphics pipeline 132. This results in the execution of shader 134 at graphics processing unit 106 to perform rendering, such as rendering to a frame buffer. Shader 134 is a set of instructions that are compiled at rendering engine 120 at central processing unit 104 and then sent to graphics processing unit 106 for execution. In one example, rendering engine 120 implements a library that executes on central processing unit 104 to compile instructions that are then sent to graphics processing unit 106, for example, using a shading language.

[0045] As described above, traditional browser implementations do not support features available in other software implementations. An example of this is geometry shaders in anti-aliased scenes, which execute to generate anti-aliasing extensions. Therefore, traditional browser implementations rely on the processing power of the central processing unit, which negates any potential efficiency gains from including a graphics processing unit on a computing device.

[0046] Therefore, the rendering engine 120 includes an instantiation control module 136, which is configured to generate a processing sequence 138 to overcome the challenges of conventional techniques. In this way, the functionality of the graphics processing unit 106 can be used in the browser 110, which is impossible in conventional techniques. Furthermore, the instantiation control module 136 overcomes the challenges of conventional techniques that lead to visual artifacts.

[0047] Instantiation is a technique for batch rendering of primitives. However, conventional techniques used for instantiation can lead to rendering problems. In a first conventional example 140, the first rectangle 142, the second rectangle 144, and the third rectangle 146 involve rendering the corresponding instance of a single triangle twice for each rectangle using a single draw call. This results in a first overlap 148 and a second overlap 150 as visual artifacts. This is because conventional rendering techniques render triangles based on instance IDs, so the first instance for each shape is rendered first, then the second instance, and so on.

[0048] On the other hand, by using the instantiation control module 136 in the technique described herein, a processing order 138 is generated to correctly render instances without visual artifacts. An example 152 of this is illustrated as a first rectangle 154, a second rectangle 156, and a third rectangle 158 rendered in the correct z-order. In this way, the operation of the central processing unit 104, the graphics processing unit 106, the browser 110, and the computing device 102 as a whole is improved. Further discussion of these and other examples is included in the following sections and is shown in the corresponding figures.

[0049] Generally, the example processes described in this section are used in the context of functions, features, and concepts related to the examples above and below. Furthermore, the functions, features, and concepts described with respect to the different figures and examples in this document are interchangeable and are not limited to implementation within the context of a particular figure or process. Moreover, the boxes associated with different representative processes and the corresponding figures herein can be applied and / or combined in different ways. Therefore, the various functions, features, and concepts described herein with respect to different example environments, devices, components, figures, and processes can be used in any suitable combination and are not limited to the specific combinations represented by the examples listed in this specification.

[0050] Graphics processing unit instantiation control

[0051] The following discussion describes techniques that can be implemented using the systems and devices described above. Aspects of each process are implemented in hardware, firmware, software, or a combination thereof. These processes are shown as a set of boxes specifying operations performed by one or more devices, and are not necessarily limited to the order in which the operations are performed by the respective boxes as shown. References will be made to the following sections of the discussion. Figures 1-19 Also refer to the examples describing graphics processing unit instantiation control techniques. Figure 4 The process is 400.

[0052] Figure 2 The example depicts System 200, which shows more details. Figure 1 The operation of the rendering engine of browser 110. First, browser 110 receives a digital object 118 (box 402). In this example, the digital object 118 is configured as a vector object. As mentioned above, graphics processing unit 106 is compatible with a defined set of basic primitives (e.g., lines, triangles, and points). Therefore, in this example, in order to render the vector object, tessellation module 202 is configured to form polygons 204 (e.g., triangles) by tessell vector objects (box 404).

[0053] In one example, vector objects are tessellated as triangles at a fixed resolution, and these triangles are rendered by the graphics processing unit 106 using a transformation matrix at different resolutions corresponding to different scaling levels. However, in conventional implementations, other image functions involving further processing of these triangles are unavailable to the browser 110's rendering engine 120. One example of this is anti-aliasing, which is typically performed in pixel space to generate anti-aliasing extensions for "smoothing" transitions between triangles. Conventional techniques generate anti-aliasing extensions at each resolution, which reduces or even eliminates the performance advantages available via the graphics processing unit.

[0054] Figure 5 Example implementation 500 is depicted, showing the effect of rendering resolution-dependent and resolution-independent regions of a vector object's geometry. The same vector object is illustrated at the first scaling level 502, the second scaling level 504, and the third scaling level 506. For each scaling level, the vector object includes resolution-independent path geometries 508, 510, and 512, which are configured to automatically scale based on the scaling level. Resolution-dependent geometries 514, 516, and 518 are also defined at the boundaries (e.g., dividing lines) of the object, including anti-aliasing extensions. As depicted, resolution-dependent geometries 514, 516, and 518 involve a thin fill that exhibits visual artifacts that can be viewed as irregular boundaries.

[0055] Figure 6 An example implementation 600 of a simple ellipse tessellation output is depicted. The ellipse includes a resolution-independent tessellation output 602 for white inner triangles and a resolution-dependent tessellation output 604 for gray control triangles. For example, a path object of an ellipse defined by a cubic Bézier curve is tessellated into a set of triangles by a tessellation module 202 on a central processing unit 104. The cubic Bézier curve is segmented into monotonic quadratic Bézier curve segments. Control triangles are generated for each quadratic Bézier curve, and the inner triangles of the geometry are triangulated into inner triangles, for example, using the Vatti algorithm.

[0056] Therefore, in this example, the control triangle undergoes anti-aliasing scaling, while the inner triangle does not. Thus, in one implementation, the rendering engine 120 is configured to detect whether the polygon 204 formed by tessellated digit objects 118 is an inner triangle or a control triangle of the digit objects 118. Anti-aliasing is then implemented for the control triangles but not the inner triangles, as further described below.

[0057] Figure 7An example implementation 700 is depicted, which organizes the output of digital object tessellation and transmits it to the memory of the graphics processing unit 106. Curve 702 "P1" is tessellated by the tessellation module 202 into a first triangle 704, a second triangle 706, and a third triangle 708 in a vertex buffer 710. In the illustrated example, the first triangle 704, the second triangle 706, and the third triangle 708 have vertices "ABC", "ADC", and "CBE". The vertex buffer 710 is accessible to the graphics processing unit 106 and, more specifically, can be accessed by the shader 134 of the graphics processing unit 106.

[0058] The output data from the tessellation (e.g., polygon 204) is organized in the vertex buffer 710 and contains the following information for each vertex:

[0059] • Coordinate position (x, y);

[0060] • Color (d); and

[0061] • Anti-aliasing properties (u, v).

[0062] In vertex buffer 710, an anti-aliasing attribute is added for each vertex, where the value "u" represents the primitive type and the anti-aliased surface. Examples of "u" values ​​include:

[0063] • Inner triangle;

[0064] • An outer triangle with convex side antialiasing;

[0065] • An outer triangle with concave side antialiasing;

[0066] • Lines with anticlockwise side antialiasing; and

[0067] • Lines with clockwise side antialiasing.

[0068] The value "v" represents the stroke width of the path object when the path object is an instance of a stroke.

[0069] Figure 8An example implementation 800 for generating anti-aliasing extensions of geometry is depicted. In the illustrated first example 802 and second example 804, a primitive definition module 206 is used to extend polygon 204 to define multiple primitives (box 406) as anti-aliasing extensions for each polygon in the polygon. The first example 802 describes convex edge anti-aliasing, and the second example 804 describes concave edge anti-aliasing.

[0070] Continuing the previous discussion of control triangles and interior triangles, for each control triangle in vertex buffer 710 (i.e., polygons detected as control triangles, and therefore not interior triangles), primitive definition module 206 uses geometry extension module 210 to generate at least two primitives, such as triangles. The left side of the figure depicts the first input curve 806 and the second input curve 808, along with the corresponding vertices and polygons 204 (e.g., first triangle 810 and second triangle 812), which are the inputs to geometry extension module 210. The first extension 814 and the second extension 816 generated by geometry extension module 210 for implementing anti-aliasing are depicted using corresponding dashed lines, which are performed in opposite directions for convex and concave curves, respectively.

[0071] The right side of the accompanying figure depicts primitives 208 formed by the geometry expansion module 210, including a first primitive 818 and a second primitive 820 based on a first triangle 810, and a first primitive 822 and a second primitive 824 based on a second triangle 812. In this way, the geometry expansion module 210 is configured to define multiple primitives to include anti-aliasing expansion of control triangles for vector objects.

[0072] Return again Figure 2 The primitives 208, based on and corresponding to the respective polygons 204, are received as input by the instantiation control module 136 and organized in the vertex buffer 710. In this example, instead of maintaining additional primitives as placeholder geometry for anti-aliasing, a mechanism is described to invoke the graphics pipeline 132 for multiple primitives, for example, via a single draw call. The rendering engine 120 employs the operation invocation module 214 to invoke a single draw call 216 (box 412) using multiple instances arranged according to the processing order 138, i.e., "perform a single draw call".

[0073] Figure 9 An example implementation 900 is depicted, in which a single draw call 216 is used to retrieve two instances from a sample triangle tessellation output on the central processing unit 104. For example, the first triangle 902 "T1" undergoes an instantiation operation to generate a first instance 904 "T1". 1 "and the second example 906"T1 2In the example of the first triangle 902 "T1", which is the control triangle, the first instance 904 "T1" is... 1 "and the second example 906"T1 1 "Transformed to generate such as" Figure 7 The extended rectangular region of the extended geometry shown.

[0074] This extended region includes the area controlling the geometry of the triangle, as well as the anti-aliasing extension for Bézier curves and line segments as part of the anti-aliasing operation. For internal triangles, the anti-aliasing extension is not computed in this example. Instead, the vertex position of an instance in the first shader is transformed such that the transformed vertex position falls outside the viewport (i.e., the viewport dimension) and is culled before rasterization in the graphics pipeline 132, for example, by vertex shader 302. However, in conventional techniques, this practice fails when attempting to render multiple polygons 204 in batches (e.g., from corresponding digital objects 118), i.e., rendering more than a single object in a single draw call for a vector object.

[0075] Figure 10 An example 1000 of prior art rendering is depicted, using conventional instantiation techniques for rendering additional triangles with a first instance 1002 and a second instance 1004. The illustrated example is used to draw a first triangle "P1", a second triangle "P2", and a third triangle "P3", which overlap and will be rendered as a batch in a single draw call. Figure 1 Example 152 depicts the target of this rendering, in which a first rectangle 154 is overlapped by a second rectangle 156, and the second rectangle 156 is overlapped by a third rectangle 158. However, in practice, a first conventional example 140 is implemented, which includes visual artifacts caused by inappropriate overlaps 148 and 150.

[0076] This is because traditional rendering techniques process instances sequentially based on their instance IDs. Therefore, the first instance is 1002, and the primitive "T1" is... 1 "1006, "T2 1 "1008 and "T3" 1 "1010 is rendered together into, for example, a frame buffer. After the second draw instance 1004, the rendering of copies of these instances continues, which is illustrated as primitive "T1". 2 "1012, "T2 2 "1014 and "T3" 2 "1016. This results in overlaps of 148 and 150 as visual artifacts that deviate from the rendering expectations, making instantiation unusable in conventional techniques due to these inaccuracies."

[0077] However, in the technique described herein, the instantiation control module 136 is configured to determine the processing order 138 (box 408) for the plurality of instances 212(1)-212(N). To this end, the instantiation control module 136 groups the corresponding primitives 208(1)-208(N) corresponding to the corresponding polygons 204 together in the corresponding instances 212(1)-212(N) (box 410).

[0078] Figure 11 Example 1100 describes the processing order of primitives in corresponding instances. For this purpose, the instantiation control module 136 configures a processing order 138, wherein instead of rendering a single triangle of “N” instances as performed in conventional techniques, “N” instances of a single triangle are rendered. Here, “N” instances represent “N” input triangles, for example, formed from tessellation of vector objects, where each triangle represents a virtual shape that does not actually exist but serves as a medium for defining primitive types, and is used to define “N” instances for rendering by the graphics processing unit 106. Tessellation data (e.g., from vertex buffer 710) of each of the “N” instances is mapped to the “N” instances of that virtual shape to generate “N” output shapes.

[0079] The virtual shape demonstrates the mechanism by which the execution order of primitives is controlled by the graphics pipeline 132. In this example, a multiplier factor is used to define the number of triangles. This multiplier factor is the factor by which the number of polygons in the tessellation output of the tessellation module 202 is increased by the primitive definition module 206 to form the primitive 208. For example, the extensions for controlling triangles and anti-aliasing are as follows:

[0080] T v =T GPU / T CPU

[0081] Among them, "T" v "T" indicates the number of triangles in the virtual shape. GPU "" indicates the number of triangles rendered by the graphics processing unit 106, while "T" indicates the number of triangles rendered by the graphics processing unit 106. CPU " indicates the number of triangles in the tessellation output, which is, for example, polygon 204, followed by primitive 208 formed based on polygon 204 for anti-aliasing expansion.

[0082] For example, in Figure 11 In the middle, consider "T" v =2” and “T” CPU=N". Virtual shape triangles "T1" 1102 and "T2" 1104 are rendered as a single draw call 216 by the graphics pipeline 132 of the graphics processing unit 106 to render "2N" triangles. Here, the total set of triangles "2N" is obtained by generating "N" instances of the two input triangles "T1" 1102 and "T2" 1104. The factor "2" is based on the intended use of the instance to generate a second triangle to complete the corresponding rectangle. Therefore, the pair of triangles represents the virtual shape in this instance.

[0083] The instantiation control module 136 is then configured to generate a processing sequence 138, in which primitives 208(1)-208(N) are assigned to corresponding instances 212(1)-212(N). Therefore, in Figure 11 In this process, firstly, a first instance 1106, a second instance 1108, ... and an "Nth" instance 1010 are formed such that the primitives corresponding to the respective polygons are rendered together. Therefore, the first instance 1106 includes the primitive "T1". 1 "1112 and "T2" 1 "1114, the second instance 1108 includes the graphic element "T1" 2 "1116 and "T2" 2 "1118, the Nth instance 1110 includes the primitive "T1" N "1120 and "T2" N 1122.

[0084] Figure 12 Example 1200 depicts the graphics processing unit 106 rendering primitives for corresponding instances to the frame buffer, following the processing order 138 defined by the instantiation control module 136. Similar to... Figure 10 In the previous example, the three rectangles “P1”, “P2”, and “P3” will be rendered as being formed by a total of “2*N=6” primitives (e.g., triangles). The triangle count on the central processing unit 104 is equal to the number of triangles in the virtual shape “2(T1, T2)” with an instance count of “N=3”. The output of the instantiation control module 136 is the primitive count “2*N=6(T1)” for the graphics processing unit 106. 1 T2 1 T1 2 T2 1 T1 3 T1 3 )".

[0085] In the first instance 1202, the element "T1" 1 "1208 and "T2" 1 "1210 is rendered. In the second instance 1204, primitive "T1" is rendered." 2 "1212 and "T2"2 "1214 is rendered, and then at the third instance 1206, primitive "T1" is rendered." 3 "1216 and "T2" 3 "1218 is rendered. Therefore, the first instance 1202 renders the primitive for "P1", the second instance 1204 renders the primitive for "P2", and the third instance 1206 renders the primitive for "P3". Thus, with..." Figure 10 Compared to existing technologies, it prevents visual artifacts. Figure 13 Example 1300 is depicted, which shows the process order 138 compared to the processing order calculated by the instantiation control module 136, following Figure 10 The example of prior art processing sequence 1302 that leads to visual artifacts.

[0086] Figure 3 A more detailed description is provided. Figure 1 The system 300 operates the graphics processing unit 106. The graphics processing unit 106 includes an application programming interface 130 through which a drawing call 216 is received. A single drawing call 216 invokes primitives 208(1)-208(N) arranged in corresponding instances 2121(1)-212(N) in a processing order 138 as described above.

[0087] The graphics pipeline 132 is configured to render multiple primitives in processing sequence 138 to frame buffer 310 (box 414). For this purpose, vertex shader 302 is used to generate rasterization 304, followed by fragment shader 306 to define the color and other attributes 308 of the corresponding pixels. Once completed, the data from frame buffer 310 is displayed by display device 124 (box 416).

[0088] Therefore, the above technique uses a single draw call 216 to render "N" instances of the virtual shape, where "N" is the number of triangles in the tessellation output of the object to be drawn. This results in "6*N" vertex shader 302 calls for each draw call. The multiplier "6" is calculated based on the determination that two triangles (i.e., primitives) will be rendered for each virtual shape, hence six vertices. Compared to conventional techniques, the "6*N" vertex shader 302 calls save on the storage cost of vertex data for these vertices and reduce the performance cost of geometry shader execution. The following discussion describes an example of how to program the vertex shader 302 and fragment shader 306 to perform anti-aliasing by rendering an anti-aliasing extension.

[0089] Figure 14 An example implementation 1400 depicts the vertex buffer layout in an array buffer for vertex buffer 710. (See also: Regarding...) Figure 7The vertex data is organized in a vertex buffer 710 (e.g., a linear vertex buffer) and transferred to the memory of the graphics processing unit 106. For a batch of paths “P1” 1402, “P2” 1404, “P3” 1406 to “PN” 1408 with “Ti” triangles, the vertices are arranged in the drawing order of the paths in the batch and in the drawing order of the triangles in the paths.

[0090] Each vertex shader call involves accessing three vertices of a triangle to which the current vertex belongs. Because the input drawing shape (e.g., a dummy shape) is separate from the data present in the vertex buffer 710, as... Figure 15 As shown in Example 1500, a mapping is established between each vertex of the vertex data 1502 for “N” primitives and the corresponding “6N” vertex shading 1504 for the first instance 1506, the second instance 1508 to the “N”th instance 1510.

[0091] In this implementation, the technique does not use a uniform buffer object that allows raw access to the buffer to read data. This is because using a uniform buffer object would limit performance. An array buffer is used to store vertex data. Vertex array attributes are then defined such that for every six vertices, the index to the array attribute advances one triangle of data in the vertex buffer 710. Typically, each vertex fetch results in the index to the vertex array attribute advancing multiple bytes in one vertex data. Using the technique described herein, the vertex array attribute index is advanced by three vertices (one triangle) of data, and this is also true after every six vertex shader fetches.

[0092] Figure 16 An example implementation 1600 of generating anti-aliasing extensions via geometric extension 1602 is described. In this example, the vertex shader 302 stage of the graphics pipeline 132 on the graphics processing unit 106 calculates the rectangle that completely encloses the control triangle, and then extends the sides of the rectangle in a direction based on the convexity of the curve, as shown in the figure. Figure 8 As described.

[0093] The extension distance for each curve is the same and predefined in pixel space. This distance is variable, based on the desired rendering fidelity and the resolution of the rendering device. Although these points are located in pixel space, there are multiple mechanisms to place them to cover the entire area of ​​the input triangle, with additional pixels around the triangle for proper anti-aliasing in any direction.

[0094] For each vertex shader call, vertex shader 302 obtains data defining the three vertices of the input triangle, given the following input:

[0095] A triangle with vertices A, B, and C

[0096] • The matrix that transforms the input vertices to pixel space: M

[0097] • Offset distance: D (in pixels)

[0098] For primitive "T1" i "1606 and "T2" i For instance 1608, each vertex shader call of 1604 calculates the geometric extension 1602 "Ti(A, B, C), D, M" for the position coordinates of each vertex "S1" 1610, "R1" 1612, "P1" 1616, and "Q1" 1618, and then selectively picks vertex coordinates based on vertex ID.

[0099] Figure 17 An example implementation of calculating the position coordinates of each vertex is described in 1700, as... Figure 16 This is part of the geometric extension shown. The vertex shader is also configured to compute additional information for each vertex, such as barycenter coordinates, convexity properties, texture coordinates, and primitive classifiers (such as line vs. degenerate curve classification). Once the anti-aliasing extension has been computed for the vector path, the fragment shader 306 processes the rasterization 304. The fragment shader 306, for example, computes the signed distance of each fragment in the rasterization 304 to the boundary Bézier / curve, and performs alpha modulation on the curve's color based on the signed distance.

[0100] Figure 18 Example 1800 depicts a comparison between the rendering results of conventional technique 1802 and the current technique 1804 described herein. In this way, the techniques described herein achieve full resolution independence without compromising performance or memory usage. Due to optimization of the vertex buffer storage, these techniques result in lower memory usage, and subsequently, reduced data transfer time between the central processing unit 104 and the graphics processing unit 106. Furthermore, these techniques are configured for use with a browser, which is impossible in conventional techniques.

[0101] Example systems and devices

[0102] Figure 19 An example system is generally illustrated at 1900, which includes an example computing device 1902, representing one or more computing systems and / or devices implementing the various technologies described herein. This is illustrated by including an instantiated control module 136. The computing device 1902 may be configured as, for example, a server of a service provider, a device associated with a client (e.g., a client device), a system-on-a-chip, and / or any other suitable computing device or computing system.

[0103] The illustrated example computing device 1902 includes a processing device 1904 communicatively coupled to each other, one or more computer-readable media 1906, and one or more I / O interfaces 1908. Although not shown, the computing device 1902 also includes a system bus or other data and command transfer system that couples the various components to each other. The system bus may include any one or a combination of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of a variety of bus architectures. Various other examples, such as control lines and data lines, are also considered.

[0104] Processing device 1904 represents a function that performs one or more operations using hardware. Therefore, processing device 1904 is illustrated as including hardware elements 1910 that can be configured as processors, function blocks, etc. This includes hardware implementations as application-specific integrated circuits (ASICs) or other logic devices formed using one or more semiconductors. Hardware elements 1910 are not limited by the materials forming them or the processing mechanisms employed therein. For example, a processor can be configured as one or more semiconductors and / or transistors (e.g., an electronic integrated circuit (IC)). In this case, the processor-executable instructions are electronically executable instructions.

[0105] The illustrated computer-readable storage medium 1906 includes a memory / storage device 1912. The memory / storage device 1912 represents a memory / storage device associated with one or more computer-readable media. The memory / storage device 1912 includes volatile media (such as random access memory (RAM)) and / or non-volatile media (such as read-only memory (ROM), flash memory, optical disk, magnetic disk, etc.). The memory / storage device 1912 includes fixed media (e.g., RAM, ROM, fixed hard disk drive, etc.) and removable media (e.g., flash memory, removable hard disk drive, optical disk, etc.). As further described below, the computer-readable medium 1906 may be configured in various other ways.

[0106] Multiple input / output interfaces 1908 represent functions that allow users to input commands and information into the computing device 1902, and also allow information to be presented to the user and / or other components or devices using various input / output devices. Examples of input devices include keyboards, cursor control devices (e.g., mice), microphones, scanners, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), cameras (e.g., using visible or invisible wavelengths such as infrared frequencies to recognize movement as gestures not involving touch), etc. Examples of output devices include display devices (e.g., monitors or projectors), speakers, printers, network interface cards, haptic-responsive devices, etc. Therefore, the computing device 1902 can be configured in various ways, as further described below, to support user interaction.

[0107] This paper describes various technologies within the general context of software, hardware components, or program modules. Typically, these modules include routines, programs, objects, elements, components, data structures, etc., that perform specific tasks or implement specific abstract data types. The terms “module,” “function,” and “component” used in this paper generally refer to software, firmware, hardware, or a combination thereof. The technologies described in this paper are characterized by platform independence, meaning that these technologies can be configured on a wide range of commercial computing platforms with various processors.

[0108] The implementations of the described modules and technologies are stored on or transmitted through some form of computer-readable medium. Computer-readable media include various media accessed by the computing device 1902. By way of example and not limitation, computer-readable media include "computer-readable storage media" and "computer-readable signal media".

[0109] "Computer-readable storage medium" means a medium and / or device that enables the persistent and / or non-transitory storage of information (e.g., instructions executable by a processing device stored thereon) compared to mere signal transmission, carrier waves, or signals themselves. Therefore, computer-readable storage medium refers to a non-signal-bearing medium. Computer-readable storage media include hardware such as volatile and non-volatile, removable and non-removable media and / or storage devices implemented with methods or techniques suitable for storing information such as computer-readable instructions, data structures, program modules, logic elements / circuits, or other data. Examples of computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, digital versatile disc (DVD) or other optical storage devices, hard disks, magnetic tape cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or other storage devices, tangible media, or articles of art suitable for storing desired information and accessible by a computer.

[0110] "Computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions to the hardware of computing device 1902, for example, via a network. Signal media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals, such as carrier waves, data signals, or other transmission mechanisms. Signal media also includes any information delivery medium. The term "modulated data signal" refers to a signal whose one or more characteristics are set or altered in a manner that encodes information in the signal. By way of example and not limitation, communication media include wired media, such as wired networks or direct-line connections, and wireless media, such as acoustic, RF, infrared, and other wireless media.

[0111] As described above, hardware element 1910 and computer-readable medium 1906 represent modules, programmable device logic, and / or fixed device logic implemented in hardware form. These modules, programmable device logic, and / or fixed device logic are used in some embodiments to implement at least some aspects of the techniques described herein, such as executing one or more instructions. The hardware includes components of integrated circuits or systems-on-a-chip, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other implementations in silicon or other hardware. In this context, the hardware operates as a processing device that performs program tasks defined by instructions and / or logic implemented by the hardware and hardware for storing the instructions for execution, such as the previously described computer-readable storage medium.

[0112] The foregoing combinations can also be used to implement the various techniques described herein. Therefore, software, hardware, or executable modules are implemented as one or more instructions and / or logic embodied on some form of computer-readable storage medium and / or implemented by one or more hardware elements 1910. Computing device 1902 is configured to implement specific instructions and / or functions corresponding to software and / or hardware modules. Therefore, the implementation of a module that can be executed as software by computing device 1902 is at least partially implemented in hardware, for example, by using computer-readable storage media and / or hardware elements 1910 of processing device 1904. Instructions and / or functions can be executed / operated by one or more articles of art (e.g., one or more computing devices 1902 and / or processing devices 1904) to implement the techniques, modules, and examples described herein.

[0113] The techniques described herein are supported by various configurations of computing device 1902, and are not limited to specific examples of the techniques described herein. This functionality can also be implemented, in whole or in part, using distributed systems, such as on “cloud” 1914 via platform 1916 as described below.

[0114] Cloud 1914 includes and / or represents platform 1916, which represents resource 1918. Platform 1916 abstracts the underlying functionality of the hardware (e.g., servers) and software resources of cloud 1914. Resource 1918 includes applications and / or data that can be utilized when performing computer processing on a server located remotely from computing device 1902. Resource 1918 may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks.

[0115] Platform 1916 abstracts resources and functions to connect computing device 1902 to other computing devices. Platform 1916 also abstracts resource scaling to provide appropriate levels of scaling to any demand on resource 1918 implemented via platform 1916. Therefore, in the interconnect device embodiment, the implementation of the functions described herein can be distributed throughout system 1900. For example, the function can be implemented partially on computing device 1902 or via platform 1916, which abstracts the functions of cloud 1914.

[0116] in conclusion

[0117] Although the invention has been described in language specific to structural features and / or methodological actions, it should be understood that the invention as defined in the appended claims is not necessarily limited to the specific features or actions described. Rather, these specific features and actions are disclosed as exemplary forms of implementing the claimed invention.

Claims

1. A method comprising: A processing device forms polygons by tessell digital objects to render the digital objects at a second resolution corresponding to a second scaling level, the second resolution being different from the first resolution of the digital objects corresponding to a first scaling level; The processing device defines multiple primitives for each polygon in the polygon; The processing device determines the processing order for multiple instances, the forming including: grouping the corresponding primitives corresponding to the corresponding polygons together in the corresponding instances; as well as The processing device retrieves the plurality of instances arranged according to the processing order to cause the graphics processing unit to render the plurality of primitives such that a first polygon, a second polygon, and a third polygon are rendered in Z order, the second polygon overlapping the first polygon, and the third polygon overlapping the second polygon. The first polygon, the second polygon, and the third polygon correspond to the first instance, the second instance, and the third instance of the plurality of instances arranged according to the processing order, respectively. The polygons including the first polygon, the second polygon, and the third polygon form at least a portion of the digital object at a second resolution corresponding to the second scaling level, the second resolution being different from the first resolution of the digital object corresponding to the first scaling level.

2. The method of claim 1, wherein the definition forms an anti-aliasing extension of the polygon for the digital object.

3. The method of claim 1, wherein the definition includes expanding each polygon in the polygons formed as triangles into the plurality of primitives formed as triangles by geometrical enlargement.

4. The method of claim 1, wherein the digital object is a Bézier curve or a vector object.

5. The method of claim 1, wherein the definition uses coordinate positions and corresponding colors in a vertex buffer to define the plurality of primitives.

6. The method of claim 5, wherein the vertex buffer is accessible to the graphics processing unit.

7. The method according to claim 1, further comprising: Detecting whether the polygon formed from the mosaic of the digital object is an internal triangle of the digital object or a control triangle, wherein the forming is performed on the polygon that is a control triangle.

8. The method of claim 1, wherein the fetch is performed using a single draw call as a batch including the plurality of instances.

9. The method of claim 1, wherein the rendering is performed by the graphics processing unit to the frame buffer.

10. A system comprising: The central processing unit is configured to perform operations for rendering a digital object at a second resolution corresponding to a second scaling level, the second resolution being different from a first resolution of the digital object corresponding to a first scaling level, the operations including: By grouping primitives corresponding to the respective polygons together in corresponding instances, the processing order for multiple instances is determined; and Retrieval includes a single draw call of the plurality of instances arranged according to the processing order; A graphics processing unit is configured to render the primitives to a frame buffer in response to the single draw call, according to the processing order for the plurality of instances, such that a first polygon, a second polygon, and a third polygon are rendered in Z-order, the second polygon overlapping the first polygon, and the third polygon overlapping the second polygon, the first polygon, the second polygon, and the third polygon respectively corresponding to a first instance, a second instance, and a third instance of the plurality of instances arranged according to the processing order, the polygons including the first polygon, the second polygon, and the third polygon forming at least a portion of the digital object at a second resolution corresponding to a second scaling level, the second resolution being different from the first resolution of the digital object corresponding to the first scaling level; and The frame buffer.

11. The system of claim 10, wherein the determination and the retrieval are performed as part of the browser being executed by the central processing unit.

12. The system of claim 10, wherein the central processing unit is further configured to perform operations including forming the respective polygons by tessell digital objects and defining the primitives for each polygon in the respective polygons.

13. The system of claim 12, wherein the definition forms an anti-aliasing extension for the corresponding polygon of the digital object.

14. The system of claim 12, wherein the definition includes expanding the corresponding polygon formed as a triangle into the plurality of primitives formed as triangles by geometrical enlargement.

15. The system of claim 10, wherein the central processing unit is further configured to form the corresponding polygon by tessell digital objects.

16. The system of claim 15, wherein the digital object is a Bézier curve or a vector object.

17. The system of claim 15, wherein the graphics processing unit is configured to render the primitives using a vertex shader and a fragment shader.

18. One or more computer-readable storage media storing instructions that, in response to execution by a processing device, cause the processing device to perform an operation, the operation comprising: Polygons are formed by tessell vector objects to render the vector objects at a second resolution corresponding to a second scaling level, the second resolution being different from the first resolution of the vector objects corresponding to a first scaling level; Anti-aliasing extensions are generated by defining multiple primitives for each polygon in the polygon; The processing order is determined by grouping the primitives corresponding to the respective polygons together in corresponding instances of multiple instances; and A single draw call to a graphics processing unit is invoked to render the vector object. The single draw call includes the plurality of instances arranged according to the processing order, such that a first polygon, a second polygon, and a third polygon are rendered in Z-order, the second polygon overlapping the first polygon, and the third polygon overlapping the second polygon. The first polygon, the second polygon, and the third polygon correspond to the first instance, the second instance, and the third instance of the plurality of instances arranged according to the processing order, respectively. The polygons including the first polygon, the second polygon, and the third polygon form at least a portion of the vector object at a second resolution corresponding to a second scaling level, the second resolution being different from the first resolution of the vector object corresponding to the first scaling level.

19. One or more computer-readable storage media according to claim 18, wherein the operations are executable using a browser.

20. The one or more computer-readable storage media of claim 18, wherein the operation further includes detecting whether the polygon formed from the tessellation of the vector object is an internal triangle or a control triangle, and wherein the generation is performed for the polygon that is a control triangle.

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