A ruggedized system for FPGA block RAM against single-event multiple-bit flips

Abstract

This invention discloses a hardening system for FPGA block RAM against single-event multiple-bit flip (SEM) errors. The system includes: several anti-MBU controllers, each corresponding to a user RAM module, and the user RAM module comprising one or more FPGA block RAMs; each anti-MBU controller includes: a control register group for controlling and recording the status of the anti-MBU controller; an ECC encoding module for ECC encoding; an interleaving module for interleaving the ECC-encoded data; a user-side read / write control module for inputting the interleaved data into the block RAM through port A for block storage, and also for reading data through port A to enter the deinterleaving module; a self-refresh control module for self-refreshing and read / write collision control when the block RAM is idle; a deinterleaving module for deinterleaving; and an ECC decoding module for ECC decoding of the deinterleaved data.

Description

Technical Field

[0001] The present invention relates to the technical field of aeronautical and aerospace data processing, in particular to a hardening system against single-event multiple-bit upset for FPGA block RAM. Background Art

[0002] FPGA has the advantages of programmable logic operation, high performance, reconfigurability and high integration, and has become a core component of spaceborne data systems. However, the logic states of FPGA internal resources such as memories and registers are prone to single-event effects in the space radiation environment, which leads to changes in circuit logic and functions and is an important factor affecting satellite safety and mission completion.

[0003] As complex space missions put increasingly higher requirements on on-orbit data processing and computing capabilities, higher-performance FPGAs are required, such as XILINX's 7-series FPGAs. Such devices with process nodes below 90nm are more sensitive to space single-event effects. Due to the geometric reduction of the FPGA manufacturing process size, such as 65nm, 28nm and 16nm processes, when a single-event upset occurs in the highly dense storage component block RAM inside FPGA, it is mostly dominated by Multi Bit Upset (MBU for short). MBU is a key problem that needs to be solved for the on-orbit application of high-performance FPGAs.

[0004] According to research findings, MBU caused by a single radiation is not uniformly distributed in each word, but has a certain error pattern. When the number of errors is large, MBU will affect two vertically adjacent words, and is mainly dominated by the pattern containing a "checkerboard (Chinese character 'tian') shape"; when the number of errors is small, the patterns are mainly "L" shape and "checkerboard" shape, and the error patterns are as Figure 1 shown. Summary of the Invention

[0005] In view of the disadvantages of the prior art such as complex multiple-bit error correction code algorithm with high delay and insufficient reliability of pure data interleaving, the purpose of the present invention is to overcome the defects of the prior art and provide a hardening method against single-event multiple-bit upset for FPGA block RAM.

[0006] To achieve the above objective, the present invention provides a hardening system against single-event multiple-bit upset for FPGA block RAM, which is used for detecting and correcting multiple-bit upset in spaceborne FPGA block RAM. The system comprises:

[0007] a plurality of MBU-resistant controllers, each MBU-resistant controller corresponds to a user RAM module, and the user RAM module comprises one or more FPGA block RAMs; the MBU-resistant controller comprises a control register group, an ECC encoding module, an interleaving module, a user-side read-write control module, a self-refresh control module, a de-interleaving module and an ECC decoding module, wherein

[0008] The control register group is used for the control and status recording of the anti-MBU controller;

[0009] The ECC encoding module is used to perform ECC encoding based on the bit width of the data to be stored by the user;

[0010] The interleaving module is used to interleave the ECC-encoded data;

[0011] The user-side read / write control module is used to input the interleaved data into the block RAM through the A port of the block RAM for block storage, and is also used to read the data through the A port of the block RAM and enter the deinterleaving module.

[0012] The self-refresh control module is used to perform self-refresh through the B port of the block RAM when the block RAM is idle; it is also used to perform read / write collision control on the block RAM.

[0013] The deinterleaving module is used to deinterleave data;

[0014] The ECC decoding module is used to perform ECC decoding on the deinterleaved data.

[0015] As an improvement to the above system, both port A and port B of the block RAM are read / write ports, with port A having a higher priority than port B.

[0016] As an improvement to the above system, the control register group includes: a configuration register, an interrupt enable register, an error count register, an ECC error address register, an ECC error type register, an ECC status clear register, and an ECC error data register.

[0017] As an improvement to the above system, the processing procedure of the ECC encoding module includes:

[0018] Based on the bit width of the data to be stored by the user, 8-bit data is encoded using Hamming code (8,5), 16-bit data is encoded using Hamming code (16,6), 32-bit data is encoded using Hamming code (32,7), and 64-bit data is encoded using Hamming code (64,8).

[0019] As an improvement to the above system, the processing procedure of the interleaving module specifically includes:

[0020] The method of interleaving four data is adopted. The four ECC-encoded data are stored in the order of low address 0-3. The even-numbered bits at address 0 and 1 are swapped with the even-numbered bits at address 2 and 3. Then, the data is written to the block RAM through the A port of the block RAM for block storage.

[0021] As an improvement to the above system, the block RAM's block storage specifically includes:

[0022] For the bit width of the data to be stored by the user:

[0023] The 8-bit data, after ECC encoding and interleaving, is stored in a 16-bit wide block RAM.

[0024] The 16-bit data, after ECC encoding and interleaving, is stored in a 16-bit wide block RAM, divided into high and low address storage.

[0025] The 32-bit data, after ECC encoding and interleaving, uses a 32-bit wide block RAM to store the valid bits and an 8-bit wide block RAM to store the encoded bits.

[0026] The 64-bit data, after ECC encoding and interleaving, is stored in two 36-bit wide blocks of RAM.

[0027] As an improvement to the above system, the read / write operations of the block RAM specifically include:

[0028] Step S1) After power-on, the block RAM is automatically initialized, and all blocks RAM are written to 0;

[0029] Step S2) When the user read / write enable signal is valid, the user-side read / write control module reads data from port A of the block RAM according to the address, the deinterleaving module performs deinterleaving, and then the ECC decoding module performs ECC decoding.

[0030] Step S3) If the ECC decoding is correct, if it is a read operation, the data is output according to the address; if it is a write operation, the data to be written and the data to be read are combined into a data of the corresponding bit width, then the ECC encoding module performs ECC encoding, and then the interleaving module performs data interleaving. Finally, the user-side read / write control module writes the data through port A according to the address.

[0031] Step S4) When an ECC decoding error occurs, depending on the ECC error type, if it is a single-bit error, the control register group records the current state, the ECC corrects the error, and proceeds to step S3);

[0032] Step S5) When an ECC decoding error occurs, depending on the ECC error type, if it is uncorrectable, the control register group records the context and notifies the user. Based on the interrupt enable register, it is determined whether to output an interrupt to the outside.

[0033] As an improvement to the above system, the self-refreshing process of the self-refreshing control module includes:

[0034] Step T1) Read the data sequentially from port B of the block RAM in order from low address to high address;

[0035] Step T2) Deinterleaving is performed by the deinterleaving module, and then ECC decoding is performed by the ECC decoding module;

[0036] Step T3) Determine if the ECC decoding is correct. If the ECC decoding is correct, increment the address by 1, continue reading the next address, and return to step T1).

[0037] If an error occurs, record the error type, error count, data, and address. Modify the data according to the location of the data error and write it back to the original address through port B. Increment the address by 1 and continue reading the next address. Proceed to step T1.

[0038] If multiple errors occur, record the situation, notify the user, and determine whether to output an interrupt based on the interrupt enable register in the control register group.

[0039] As an improvement to the above system, the read / write collision control of the self-refresh control module specifically includes:

[0040] When ports A and B of the block RAM simultaneously read from and write to the same address of the block RAM, a read-write collision occurs. Port B adopts a read-write handshake mechanism, waiting for port A to complete its operation before proceeding with its own operation.

[0041] Compared with the prior art, the advantages of the present invention are:

[0042] 1. The present invention provides a hardening system for FPGA block RAM against single-event multi-bit flips, which converts multi-bit flips into multiple unit flips and implements Hamming encoding and decoding through combinational logic, and has the advantages of short delay and simple logic.

[0043] 2. The hardening system for FPGA block RAM against single-event multi-bit flips of FPGAs utilizes the idle state of the block RAM for self-refreshing and automatically writes back if an error occurs. It also incorporates RAM read / write collision design, which has the advantage of high reliability.

[0044] 3. The present invention provides a hardening system for FPGA block RAM against single-event multiple-bit flips. Based on the characteristics of 8-bit, 16-bit, 32-bit and 64-bit data widths, it proposes a block storage method, which has the advantages of high efficiency and high resource utilization. Attached Figure Description

[0045] Figure 1 This is an example of an incorrect pattern;

[0046] Figure 2 This is a block diagram of the hardening system for FPGA block RAM against single-event multi-bit flips according to the present invention.

[0047] Figure 3This is a diagram illustrating the data interleaving and storage method corresponding to the 8-bit data width of the present invention;

[0048] Figure 4 This is a diagram illustrating the data interleaving and storage method corresponding to the 16-bit data width of the present invention;

[0049] Figure 5 This is a diagram illustrating the data interleaving and storage method corresponding to the 32-bit data width of the present invention;

[0050] Figure 6 This is a diagram illustrating the data interleaving and storage method corresponding to the 64-bit data width of the present invention;

[0051] Figure 7 This is a flowchart of the user read / write steps for the block RAM of the present invention;

[0052] Figure 8 This is a flowchart of the block RAM self-refresh method of the present invention. Detailed Implementation

[0053] Solutions to multi-bit flip-flops in FPGAs include multi-bit error correction coding and data interleaving. Multi-bit error correction coding is computationally complex and requires long delays, making it unsuitable for real-time scenarios. Data interleaving is a commonly used method. This invention, combined with practical engineering applications, leverages the hardware resource layout characteristics of FPGAs to propose a specific hardened system for resisting multi-bit flip-flops in the FPGA's internal block RAM. An anti-MBU controller is designed for real-time control and RAM self-refresh, further improving the reliability of traditional data interleaving.

[0054] The system includes several anti-MBU controllers, each corresponding to a user RAM module, and the user RAM module includes one or more FPGA block RAMs. Each anti-MBU controller includes: a control register group, an ECC encoding module, an interleaving module, a user-side read / write control module, a self-refresh control module, a deinterleaving module, and an ECC decoding module.

[0055] The control register set is used for control and status recording of the MBU-resistant controller;

[0056] The ECC encoding module is used to perform ECC encoding based on the bit width of the data to be stored by the user.

[0057] The interleaving module is used to interleave data after ECC encoding.

[0058] The user-side read / write control module is used to input the interleaved data into the block RAM through the A port of the block RAM for block storage, and also to read the data out through the A port of the block RAM to enter the deinterleaving module.

[0059] The self-refresh control module is used to perform self-refresh when the block RAM is idle. That is, it periodically reads data from the B port of the block RAM, processes it through the deinterleaving module and the ECC decoding module, and then performs ECC verification, status acquisition and data write-back. It is also used to control read and write collisions in the block RAM.

[0060] The deinterleaving module is used to deinterleave four data points.

[0061] The ECC decoding module is used to perform ECC decoding on the deinterleaved data.

[0062] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0063] Example

[0064] like Figure 2 As shown, this application proposes a hardening system for FPGA block RAM against single-event multi-bit flips, which is used to detect and correct multi-bit flips in spaceborne FPGA block RAM.

[0065] The core function of this system is the design of a general-purpose block RAM anti-MBU controller. Each block RAM is configured with one MBU controller, which includes a control register group, an ECC encoding module, an interleaving module, a self-refresh control module, a deinterleaving module, and an ECC decoding module; among which:

[0066] 1) The control register group is used for the control and status recording of the anti-MBU controller, including configuration register, interrupt enable register, error count register, ECC error address, ECC error type, ECC status clear, ECC error data, etc.

[0067] 2) The ECC encoding module is used to implement the encoding of (8,5), (16,6), (32,7), and (64,8) Hamming codes;

[0068] 3) The interleaving module is used to implement the interleaving of four data streams;

[0069] 4) The self-refresh control module is used to realize data reading back in address order, ECC status acquisition, data write-back, and read / write collision control;

[0070] 5) The deinterleaving module is used to deinterleave the four data points;

[0071] 6) The ECC decoding module is used to decode (8,5), (16,6), (32,7), and (64,8) Hamming codes and output the error type and error location.

[0072] Its characteristics are:

[0073] 1) First, the data is encoded with Hamming code, then data interleaving is performed, and block storage is performed according to the data bit width. The designed data bit widths include 8 bits, 16 bits, 32 bits and 64 bits;

[0074] 2) The block RAM adopts a dual-port mode, and performs self-refresh when the block RAM is in an idle state, that is, periodically reads out and performs ECC (Error Correction Code) checking. If an error occurs, it is recorded and written back for correction;

[0075] 3) A design method of a general block RAM anti-MBU controller is proposed, which is used for Hamming code encoding and decoding, data interleaving, and self-refresh functions.

[0076] The following further describes the reinforcement method against single-event multiple-bit upset for FPGA block RAM in the present invention.

[0077] First, the ECC encoding to be adopted is determined according to the bit width of the data to be stored by the user. 8-bit data is encoded and decoded with Hamming code (8,5), 16-bit data is encoded and decoded with Hamming code (16,11), 32-bit data is encoded and decoded with Hamming code (32,26), and 64-bit data is encoded and decoded with Hamming code (64,57).

[0078] Figure 3 , Figure 4 , Figure 5 and Figure 6 are respectively diagrams of 8-bit, 16-bit, 32-bit, and 64-bit data widths after data interleaving of the present invention. A method of 4-data interleaving storage is adopted, which can correct up to 4-bit flips represented by "L" and "field" shapes. The basic interleaving method is: four pieces of data are stored in the order of low addresses 0-3, and the even bits at addresses 0 and 1 are exchanged with the even bits at addresses 2 and 3, as shown in Figure 3 . After 8-bit original data is Hamming encoded, it is 13 bits; after 16-bit original data is Hamming encoded, it is 22 bits; after 32-bit original data is Hamming encoded, it is 39 bits; after 64-bit original data is Hamming encoded, it is 72 bits. The minimum form of XILINX FPGA block RAM is 18K RAM, and two adjacent 18K RAMs can form a 36K RAM. The 18K RAM can be set to different data widths, supporting a maximum of 36 bits. Using this feature of FPGA block RAM, the block storage optimization design is performed on the encoded data, as follows:

[0079] 1) The 13-bit data after 8-bit encoding is stored in a 16-bit wide block RAM;

[0080] 2) The 22-bit data after 16-bit encoding is stored in a 16-bit wide block RAM by dividing into high and low addresses. The advantage is that it only needs one block RAM to implement, avoiding resource waste caused by using two block RAMs;

[0081] 3) The 39-bit data after 32-bit encoding uses a 32-bit wide block RAM to store the valid bits and an 8-bit wide block RAM to store the encoded bits. The advantage is that the second block RAM only needs an 8-bit width, avoiding resource waste.

[0082] 4) The 72-bit data after 64-bit encoding is stored using two 36-bit wide blocks of RAM.

[0083] In the hardening system for FPGA block RAM against single-event multi-bit flips (SEM), the FPGA block RAM adopts a dual-port mode. Port A is used for user read / write interfaces, and Port B is used for MBU controller interface protection. A handshake method on Port B is used to resolve RAM read / write collisions, prioritizing the user read / write interface. Specific implementation methods are as follows: Figure 7 As shown, the user read / write steps are as follows:

[0084] 1) Upon power-on, RAM is automatically initialized, and all RAM values ​​are written to 0;

[0085] 2) When the user read / write signal is valid, data is read from port A of RAM according to the address, deinterleaved, and ECC decoded;

[0086] 3) If the ECC decoding is correct, if it is a read operation, output the data according to the address; if it is a write operation, merge the data to be written and the data to be read into a data of the corresponding bit width, perform ECC encoding and interleaving, and then write the data according to the address.

[0087] 4) If an ECC decoding error occurs, depending on the ECC error type, if it is a single-bit error, record the situation, perform ECC error correction, then determine the read / write operation, and proceed to step 3).

[0088] 5) If an ECC decoding error occurs, depending on the ECC error type, if it is uncorrectable, record the situation and notify the user. Then, depending on the interrupt enable register, decide whether to output an interrupt.

[0089] like Figure 8 As shown, the present invention provides a hardening method for FPGA block RAM against single-event multi-bit flips (SEM). This method employs a self-refresh mechanism to further improve system reliability. Specifically, the anti-MBU controller reads data sequentially from port B in ascending order of address and performs ECC verification.

[0090] 1) If the ECC checks for errors, increment the address by 1 and continue reading the next address;

[0091] 2) If a bit error occurs, record the error type, error count, data, and address. Modify the data according to the location of the data error and write it back. Increment the address by 1 and continue reading the next address. The interrupt enable register can be used to determine whether to output the interrupt.

[0092] 3) If an error occurs that cannot be corrected, record the situation and notify the user. Then, depending on the interrupt enable register, decide whether to output the interrupt to the outside world.

[0093] like Figure 3 , Figure 5 , Figure 6 The diagram illustrates the interleaving of 8-bit, 32-bit, and 64-bit data widths. If a user writes only a single number, a 0 can be added to facilitate interleaving, and the data is written to the corresponding two addresses. If a number is modified, the numbers at both addresses must first be read back, de-interleaved, decoded, modified, and then re-encoded and interleaved back to the two addresses.

[0094] like Figure 4 The diagram illustrates the data interleaving process for a 16-bit data width. If a user writes only a single number, a 0 can be added to facilitate interleaving, and the data is written to the corresponding four addresses. If a number is modified, the numbers at the four addresses must first be read back, de-interleaved, decoded, modified, and then re-encoded and interleaved before being written back to the four addresses.

[0095] When ports A and B simultaneously read from or write to the same address in the block RAM, a read-write collision occurs. The user-side port B employs a read-write handshake mechanism, waiting for port A to complete its operation before proceeding. Port A has a higher priority than port B, ensuring the user's read and write operations are guaranteed.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A hardening system for FPGA block RAM against single-event multiple-flip (SEF) events, used to detect and correct SEF events in spaceborne FPGA block RAM, characterized in that, The system includes: Several anti-MBU controllers are provided, each corresponding to a user RAM module. The user RAM module includes one or more FPGA block RAMs. Each anti-MBU controller includes: a control register group, an ECC encoding module, an interleaving module, a user-side read / write control module, a self-refresh control module, a deinterleaving module, and an ECC decoding module. The control register group is used for the control and status recording of the anti-MBU controller; The ECC encoding module is used to perform ECC encoding based on the bit width of the data to be stored by the user; The interleaving module is used to interleave the ECC-encoded data and then write it into the block RAM for block storage via port A of the block RAM; the block storage of the block RAM specifically includes: For the bit width of the data to be stored by the user: The 8-bit data, after ECC encoding and interleaving, is stored in a 16-bit wide block RAM. The 16-bit data, after ECC encoding and interleaving, is stored in a 16-bit wide block RAM, divided into high and low address storage. The 32-bit data, after ECC encoding and interleaving, uses a 32-bit wide block RAM to store the valid bits and an 8-bit wide block RAM to store the encoded bits. The 64-bit data, after ECC encoding and interleaving, is stored in two 36-bit wide blocks of RAM. The user-side read / write control module is used to input the interleaved data into the block RAM through the A port of the block RAM for block storage, and is also used to read the data through the A port of the block RAM and enter the deinterleaving module. The self-refresh control module is used to perform self-refresh through the B port of the block RAM when the block RAM is idle; it is also used to perform read / write collision control on the block RAM. The deinterleaving module is used to deinterleave data; The ECC decoding module is used to perform ECC decoding on the deinterleaved data.

2. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 1, characterized in that, Both port A and port B of the block RAM are read / write ports, with port A having a higher priority than port B.

3. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 1, characterized in that, The control register group includes: a configuration register, an interrupt enable register, an error count register, an ECC error address register, an ECC error type register, an ECC status clear register, and an ECC error data register.

4. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 1, characterized in that, The processing procedure of the ECC encoding module includes: Based on the bit width of the data to be stored by the user, 8-bit data is encoded using Hamming code (8,5), 16-bit data is encoded using Hamming code (16,6), 32-bit data is encoded using Hamming code (32,7), and 64-bit data is encoded using Hamming code (64,8).

5. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 4, characterized in that, The data interleaving of the interleaving module specifically includes: The method of interleaving four data is adopted. The four ECC-encoded data are stored in the order of low address 0-3, and the even-numbered bits at addresses 0 and 1 are swapped with the even-numbered bits at addresses 2 and 3.

6. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 2, characterized in that, The read and write operations of the block RAM specifically include: Step S1) After power-on, the block RAM is automatically initialized, and all blocks RAM are written to 0; Step S2) When the user read / write enable signal is valid, the user-side read / write control module reads data from port A of the block RAM according to the address, the deinterleaving module performs deinterleaving, and then the ECC decoding module performs ECC decoding. Step S3) If the ECC decoding is correct, if it is a read operation, the data is output according to the address; if it is a write operation, the data to be written and the data to be read are combined into a data of the corresponding bit width, then the ECC encoding module performs ECC encoding, and then the interleaving module performs data interleaving. Finally, the user-side read / write control module writes the data through port A according to the address. Step S4) When an ECC decoding error occurs, depending on the ECC error type, if it is a single-bit error, the control register group records the current state, the ECC corrects the error, and proceeds to step S3). Step S5) When an ECC decoding error occurs, depending on the ECC error type, if it is uncorrectable, the control register group records the context and notifies the user. Based on the interrupt enable register, it is determined whether to output an interrupt to the outside.

7. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 2, characterized in that, The self-refreshing process of the self-refreshing control module includes: Step T1) Read the data sequentially from port B of the block RAM in order from low address to high address; Step T2) Deinterleaving is performed by the deinterleaving module, and then ECC decoding is performed by the ECC decoding module; Step T3) Determine if the ECC decoding is correct. If the ECC decoding is error-free, increment the address by 1, continue reading the next address, and return to step T1). If an error occurs, record the error type, error count, data, and address. Modify the data according to the location of the data error and write it back to the original address via port B. Increment the address and continue reading the next address, then proceed to step T1. If multiple errors occur, record the situation, notify the user, and determine whether to output an interrupt based on the interrupt enable register in the control register group.

8. The hardening system for FPGA block RAM against single-event multiple-bit flips according to claim 7, characterized in that, The read / write collision control of the self-refresh control module specifically includes: When ports A and B of the block RAM simultaneously read from and write to the same address of the block RAM, a read-write collision occurs. Port B adopts a read-write handshake mechanism, waiting for port A to complete its operation before proceeding with its own operation.

Images