Method for improving the resistance of nor flash memory

Abstract

A method for improving the endurance of a NOR flash memory is disclosed. The NOR flash memory includes a substrate, a well region formed in the substrate, a tunnel oxide layer, a floating gate, a dielectric layer and a control gate sequentially stacked on the substrate, and a source and a drain disposed in the well region. The method includes detecting the erase time of the NOR flash memory, and when the erase time exceeds a predetermined value, floating the source, applying a negative voltage to the control gate, and applying a positive voltage to the well region to Joule heat the drain terminal.

Description

Technical Field

[0001] This invention relates to a flash memory technology, and more particularly to a method for improving the tolerance of NOR flash memory. Background Technology

[0002] Flash memory has become a widely used type of memory in personal computers and other electronic devices because it retains data even when power is off. A flash memory generally consists of a substrate, a tunneling oxide layer, a floating gate, a dielectric layer and a control gate stacked sequentially on the substrate, as well as source and drain electrodes.

[0003] Flash memory includes NOR flash memory and NAND flash memory. NOR flash memory has a faster data read speed. It is written by hot electron injection, which allows electrons to tunnel through the floating gate, and erased by Fowler-Norheim tunneling. However, after multiple write / erase cycles, electrons tend to accumulate in the tunneling oxide layer near the drain terminal and at the interface between the tunneling oxide layer and the substrate. This accumulation of electrons can lead to a critical voltage Vc. T The changes cause the memory window to gradually shrink, leading to a gradual increase in the time required for erasure. Ultimately, this reduces the endurance of NOR flash memory, resulting in a short lifespan.

[0004] The traditional solution is to heat-anneal the entire semiconductor device containing flash memory to remove trapped electrons from the tunneling oxide layer at the drain end and at the interface between the tunneling oxide layer and the substrate. However, since semiconductor devices are usually packaged, this heating method often cannot reach the required high temperature due to the temperature limitations of the package material, and the overall efficiency is poor. Summary of the Invention

[0005] This invention provides a method for improving the durability of NOR flash memory, which can effectively reduce interface traps and bulk traps in NOR flash memory without affecting the packaging materials and interconnects in the semiconductor device, thereby improving the durability and lifespan of NOR flash memory.

[0006] The present invention provides a method for improving the tolerance of NOR flash memory, wherein the NOR flash memory includes a substrate, a well region formed in the substrate, a tunneling oxide layer, a floating gate, a dielectric layer and a control gate sequentially stacked on the substrate, and a source and a drain disposed in the well region. The method includes: detecting the erase time of the NOR flash memory; and when the erase time exceeds a predetermined value, placing the source in a floating state, applying a negative voltage to the control gate, and applying a positive voltage to the well region to perform Joule heating on the drain terminal.

[0007] In one embodiment of the present invention, the Joule heating time is greater than 1 second.

[0008] In one embodiment of the present invention, the Joule heating time is greater than 60 seconds.

[0009] In one embodiment of the present invention, the well region is a P-type doped region.

[0010] In one embodiment of the present invention, the negative voltage is -2V.

[0011] In one embodiment of the present invention, the negative voltage is less than -2V.

[0012] In one embodiment of the present invention, the positive voltage is between 3V and 5V.

[0013] In one embodiment of the present invention, the voltage of the drain electrode is 0V.

[0014] In one embodiment of the present invention, the Joule heating temperature is between 150°C and 800°C.

[0015] Based on the above, the method for improving the durability of NOR flash memory according to the present invention improves the durability of NOR flash memory by simultaneously detecting the required erase time during the write / erase process. When the erase time exceeds a predetermined value, Joule heating is applied to the drain terminal to remove trapped electrons from the tunneling oxide layer near the drain terminal and the junction between the tunneling oxide layer and the substrate. Furthermore, because Joule heating does not heat other parts of the semiconductor device, it does not affect the interconnects or overall package structure of the semiconductor device, thus improving its lifespan.

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a NOR flash memory.

[0018] Figure 2This is a step diagram illustrating an embodiment of the present invention for improving the durability of NOR flash memory.

[0019] Symbol Explanation

[0020] 10: NOR flash memory

[0021] 100:Substrate

[0022] 102: Tunnel

[0023] 110: Tunneling Oxide Layer

[0024] 120: Floating gate

[0025] 130: Dielectric layer

[0026] 140: Control gate

[0027] 150: Source Extreme

[0028] 160: Drain

[0029] S1, S2, S3: Steps Detailed Implementation

[0030] The following provides many different implementations or embodiments for carrying out various features of the invention. Moreover, these embodiments are merely illustrative and are not intended to limit the scope and application of the invention. Furthermore, for clarity, the relative dimensions (e.g., length, thickness, spacing, etc.) and relative positions of various regions or structural elements may be reduced or enlarged. Additionally, similar or identical element symbols are used in the various figures to denote similar or identical elements or features.

[0031] Figure 1 This is a schematic diagram of a NOR flash memory. Figure 2 This is a step diagram illustrating an embodiment of the present invention for improving the durability of a NOR flash memory.

[0032] Please refer to Figure 1 The NOR flash memory 10 includes a substrate 100, a well region 102 formed in the substrate, a tunneling oxide layer 110, a floating gate 120, a dielectric layer 130 and a control gate 140 stacked sequentially on the substrate 100, and a source 150 and a drain 160 disposed in the well region 102.

[0033] In this embodiment, substrate 100 can be a semiconductor substrate, such as a silicon substrate. Well region 102 can be formed by doping P-type dopant into substrate 100 using ion implantation. The tunneling oxide layer 110 can be a dielectric material, such as silicon oxide. Floating gate 120 can be a polysilicon layer. Dielectric layer 130 can be a single-layer or multi-layer structure; for example, dielectric layer 130 can be a composite layer composed of oxide / nitride / oxide (ONO). Control gate 140 can be a polysilicon layer. However, the present invention is not limited thereto; in other embodiments, other suitable materials can be used as the materials for the above layers, and the manufacturing methods of the above layers can also utilize existing technology, so they will not be described in detail here.

[0034] Please refer to the following at the same time Figure 1 and Figure 2 A method for improving the tolerance of NOR flash memory 10 includes: in step S1, during the write / erase process of NOR flash memory 10, simultaneously detecting the erase time of NOR flash memory 10.

[0035] Next, if the detected erasure time exceeds a predetermined value, step S2 is executed to put the source 150 in a floating state, apply a negative voltage to the control gate 140, and apply a positive voltage to the well region 102 to perform Joule heating on the drain 160 terminal.

[0036] In this embodiment, the negative voltage applied to the control gate 140 can be -2V or less. The positive voltage applied to the well region 102 is, for example, 3V to 5V. However, the invention is not limited thereto; the values ​​of the negative and positive voltages can be varied as needed. In some embodiments, the method for improving the tolerance of the NOR flash memory 10 further includes setting the drain voltage to 0V while keeping the source 150 in a floating state, applying a negative voltage to the control gate 140, and applying a positive voltage to the well region 102.

[0037] When the source 150, drain 160, control gate 140, and well region 102 of the NOR flash memory are within the aforementioned voltage range, Joule heating can be applied to the junction of the well region 102 and the drain 160. This causes electrons trapped in the tunneling oxide layer 110 near the junction of the well region 102 and the drain 160, and at the junction of the tunneling oxide layer 110 and the well region 102 (substrate 100), to move towards the substrate 100, preventing the accumulation of trapped electrons from causing a critical voltage V. T This change increases the time required for erasure and may even affect the durability of the NOR flash memory 10.

[0038] Finally, step S3 is executed to continue writing / erasing the NOR flash memory 10. Then, the process returns to step S1 and continues in a loop. Alternatively, if the detected erasure time remains within the predetermined value mentioned above, step S3 can be executed directly.

[0039] In this embodiment, Joule heating is applied directly to the drain 160 inside the NOR flash memory 10, eliminating the need for additional heating structures or steps outside the NOR flash memory 10. Furthermore, this invention only locally heats the drain 160, resulting in better performance than conventional methods that require heating the entire flash memory to improve electron accumulation. Moreover, in this invention, the method described above is immediately executed once the erase time of any segment in the flash memory exceeds a preset value, effectively extending the lifespan of the NOR flash memory and improving its durability.

[0040] In summary, the method for improving the resilience of NOR flash memory according to the present invention improves the resilience of NOR flash memory by simultaneously detecting the required erase time during the write / erase process. When the erase time exceeds a predetermined value, Joule heating is applied to the drain terminal to pull electrons trapped in the tunneling oxide layer near the drain terminal and at the interface between the tunneling oxide layer and the substrate to the substrate, preventing them from remaining in the tunneling oxide layer or at the interface between the tunneling oxide layer and the substrate. Furthermore, because Joule heating does not heat other parts of the semiconductor device, it does not affect the interconnects or overall package structure of the semiconductor device, thus improving its lifespan.

[0041] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for improving the tolerance of a NOR flash memory, wherein the NOR flash memory includes a substrate, a well region formed in the substrate, a tunneling oxide layer, a floating gate, a dielectric layer and a control gate sequentially stacked on the substrate, and a source and a drain disposed in the well region, the method comprising: The erase time of the NOR flash memory is detected; as well as When the erasure time exceeds a predetermined value, The source electrode is placed in a floating state. A negative voltage is applied to the control gate, and A positive voltage is applied to the well region to Joule heat the drain terminal, thereby removing trapped electrons from the tunneling oxide layer and the junction between the tunneling oxide layer and the substrate.

2. The method for improving the tolerance of NOR flash memory as described in claim 1, wherein the Joule heating time is greater than 1 second.

3. The method for improving the tolerance of NOR flash memory as described in claim 1, wherein the Joule heating time is greater than 60 seconds.

4. The method for improving the tolerance of NOR flash memory as described in claim 1, wherein the well region is a P-type doped region.

5. The method for improving the tolerance of NOR flash memory as described in claim 1, wherein the negative voltage is -2V.

6. The method for improving the tolerance of NOR flash memory as described in claim 1, wherein the negative voltage is less than -2V.

7. The method for improving the tolerance of NOR flash memory as claimed in claim 1, wherein the positive voltage is between 3V and 5V.

8. The method for improving the tolerance of NOR flash memory as described in claim 1, wherein the voltage of the drain is 0V.

9. The method for improving the tolerance of NOR flash memory as claimed in claim 1, wherein the Joule heating temperature is between 150°C and 800°C.

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