High electron mobility transistor structure and method of manufacture

Abstract

A method for fabricating a high electron mobility transistor structure, by controlling the growth of a passivation layer and a barrier layer in the same growth chamber without interruption, to avoid defects in the passivation layer during growth due to drastic changes in temperature, pressure or atmosphere, or to avoid deterioration of the interface between the passivation layer and the barrier layer, thereby providing a high-quality passivation layer and a high-quality interface between the passivation layer and the barrier layer, to achieve the goal of improving the performance of the high electron mobility transistor structure.

Description

Technical Field

[0001] This invention relates to semiconductor technology; in particular, it refers to a high electron mobility transistor. Background Technology

[0002] A high electron mobility transistor (HEMT) is a transistor with a two-dimensional electron gas (2-DEG). The 2-DEG is adjacent to the heterojunction surface between two materials with different band gaps. Since the HEMT does not use doped regions as the carrier channels of the transistor, but uses a 2-DEG with high electron mobility as the carrier channels, the HEMT has characteristics such as high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and can be widely used in high-power semiconductor devices.

[0003] To improve performance, a passivation layer, such as gallium nitride (GaN), is typically grown above the barrier layer of high electron mobility transistors (HETTs). However, GaN readily bonds with oxygen, leading to increased surface defects, which in turn causes issues such as insufficient device stability and increased leakage current. Therefore, providing a passivation layer that can improve the performance of HETTs is a pressing problem that needs to be solved. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a high electron mobility transistor structure and manufacturing method, which can provide a high-quality passivation layer and thereby improve the performance of the high electron mobility transistor.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a high electron mobility transistor structure, comprising the following steps:

[0006] A. Provide a substrate;

[0007] B. A nucleation layer is formed above the substrate;

[0008] C. A buffer layer is formed above the nucleation layer;

[0009] D. A channel layer is formed above the buffer layer;

[0010] E. A barrier layer is deposited above the channel layer, the growth temperature of the barrier layer is a first growth temperature, and a two-dimensional electron gas region is formed in the channel layer along the interface between the channel layer and the barrier layer, wherein step E is performed in a growth chamber.

[0011] F. After performing step E, a passivation layer is continuously deposited above the barrier layer in the growth chamber, and the growth temperature of the passivation layer is controlled to rise from the first growth temperature through a heating section to a second growth temperature.

[0012] The present invention also provides a high electron mobility transistor structure, which sequentially comprises: a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a passivation layer; wherein a two-dimensional electron gas region is formed in the channel layer along the interface between the channel layer and the barrier layer; the change in sheet resistance of the two-dimensional electron gas region of the channel layer within a time interval is less than or equal to 1%, and the time interval is greater than or equal to three months.

[0013] The advantage of this invention lies in that, by controlling the uninterrupted growth of the passivation layer and the barrier layer in the same growth chamber, defects in the passivation layer during growth or degradation of the interface quality between the passivation layer and the barrier layer due to drastic changes in temperature, pressure, or atmosphere can be avoided. This results in a high-quality passivation layer and interface between the passivation layer and the barrier layer, thereby improving the performance of high electron mobility transistors. Furthermore, this invention provides another high electron mobility transistor structure in which, through the formation of the passivation layer, the sheet resistance change of the two-dimensional electron gas region of the channel layer within a time interval is less than or equal to 1%, and the time interval is greater than or equal to three months, thereby improving the stability of the high electron mobility transistor. Attached Figure Description

[0014] Figure 1 A flowchart of a preferred embodiment of the present invention for manufacturing a high electron mobility transistor structure.

[0015] Figure 2 This is a schematic diagram of a high electron mobility transistor structure according to a preferred embodiment of the present invention.

[0016] Figure 3 This is a graph showing the relationship between time and temperature for growing the passivation layer according to a preferred embodiment of the present invention.

[0017] Figure 4 This is a graph showing the relationship between time and temperature for growing the passivation layer according to a preferred embodiment of the present invention.

[0018] Figure 5 This is a graph showing the relationship between time and temperature for growing the passivation layer according to a preferred embodiment of the present invention.

[0019] Figure 6 This is a graph showing the relationship between time and temperature for growing a passivation layer in a comparative example.

[0020] Figure 7This is a graph showing the relationship between time and temperature for growing the passivation layer according to a preferred embodiment of the present invention. Detailed Implementation

[0021] To more clearly illustrate the present invention, preferred embodiments are described in detail below with reference to the accompanying drawings. Please refer to... Figure 1 The diagram illustrates a preferred embodiment of a high electron mobility transistor structure manufacturing method according to the present invention, comprising the following steps:

[0022] Step S02, a substrate 10 is provided; the substrate 10 may be, for example, a silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or aluminum oxide (Al2O3) substrate.

[0023] Step S04: A nucleation layer 20 is formed over the substrate 10. The nucleation layer 20 may be a nitride nucleation layer such as aluminum nitride (AlN) or aluminum gallium nitride (AlGaN). For example, the nucleation layer 20 may be formed by metal-organic chemical vapor deposition (MOCVD).

[0024] Step S06: A buffer layer 30 is formed above the nucleation layer 20; the buffer layer 30 may be, for example, a gallium nitride (GaN) nitride buffer layer, and the buffer layer 30 may be formed by metal-organic chemical vapor deposition (MOCVD).

[0025] Step S08: A channel layer 40 is formed above the buffer layer 30; the channel layer 40 may be, for example, a gallium nitride (GaN) nitride channel layer, and the channel layer 40 may be formed by metal-organic chemical vapor deposition (MOCVD).

[0026] Step S10: A barrier layer 50 is deposited above the channel layer 40. The growth temperature of the barrier layer 50 is a first growth temperature T1, preferably 700-1000°C. A two-dimensional electron gas region is formed in the channel layer 40 along the interface between the channel layer 40 and the barrier layer 50. Step S10 is performed in a growth chamber. The barrier layer 50 can be a nitride barrier layer such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), or aluminum indium gallium nitride (AlInGaN). The barrier layer 50 can be formed by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0027] Step S12: After performing step S10, a passivation layer 60 is continuously deposited on top of the barrier layer 50 in the growth chamber. The growth temperature of the passivation layer 60 is controlled to rise from the first growth temperature T1 through a heating section RT to a second growth temperature T2, where the second growth temperature T2 is greater than or equal to 1000°C. The passivation layer 60 is silicon nitride and can be formed by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The total thickness of the passivation layer 60 is less than or equal to 100 nm, where the total thickness refers to the distance from the junction of the passivation layer 60 and the barrier layer 50 to the upper surface of the passivation layer 60.

[0028] In other words, after the barrier layer 50 is formed in the growth chamber of the metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) machine, the semi-finished product after completing step S10 is not removed from the growth chamber. That is, the barrier layer 50 is not exposed to air or the environment outside the growth chamber, but step S12 is directly performed in the growth chamber to form the passivation layer 60. In other words, the barrier layer 50 and the passivation layer 60 are formed under the same growth conditions of space, pressure and atmosphere, and the initial growth temperature of the passivation layer 60 is the same as that of the barrier layer 50. The same atmosphere means using the same carrier gas, such as hydrogen or nitrogen.

[0029] Therefore, by controlling the uninterrupted growth of the passivation layer 60 and the barrier layer 50 in the same growth chamber, defects in the passivation layer 60 during the growth process or degradation of the interface quality between the passivation layer 60 and the barrier layer 50 due to drastic changes in temperature, pressure, or atmosphere can be avoided. This provides a high-quality passivation layer 60 and a high-quality interface between the passivation layer 60 and the barrier layer 50, thereby improving the performance of high electron mobility transistors.

[0030] Step S12 includes maintaining the second growth temperature T2 within a high-temperature isothermal zone HT, that is, as Figure 3 As shown, the barrier layer 50 is grown at the first growth temperature T1 for a predetermined time t1, and then the passivation layer 60 is grown. The initial growth temperature of the passivation layer 60 is the same as that of the barrier layer 50, and it is heated to the second growth temperature T2 through the heating section RT. The second growth temperature T2 is then maintained for another predetermined time t2 to grow the passivation layer 60 to the required thickness. The percentage of the growth thickness of the passivation layer 60 in the high-temperature isothermal section HT to the total thickness of the passivation layer is greater than or equal to 50%.

[0031] In another embodiment, such as Figure 4As shown, step S12 includes controlling the growth temperature of the passivation layer 60 to first maintain the first growth temperature T1 in a low-temperature isothermal zone LT, then raise the temperature in the heating zone RT, and finally maintain the second growth temperature T2 in the high-temperature isothermal zone HT. The total thickness of the passivation layer 60 is the sum of the growth thicknesses of the passivation layer 60 in the low-temperature isothermal zone LT, the heating zone RT, and the high-temperature isothermal zone HT. The percentage of the growth thickness of the passivation layer 60 in the low-temperature isothermal zone LT to the total thickness of the passivation layer 60 is 0-25%, and the percentage of the growth thickness of the passivation layer 60 in the heating zone RT to the total thickness of the passivation layer 60 is 0-25%.

[0032] In another embodiment, the growth thickness of the low-temperature isothermal section LT accounts for 0% of the total thickness of the passivation layer 60, the growth thickness of the passivation layer 60 in the heating section RT accounts for 5-25% of the total thickness of the passivation layer 60, and the growth thickness of the high-temperature isothermal section HT accounts for 75-95% of the total thickness of the passivation layer 60; that is, in step S12, the growth temperature of the passivation layer 60 is controlled as follows: Figure 3 The process involves first raising the temperature from the first growth temperature T1 to the second growth temperature T2 in the heating zone RT, and then maintaining the second growth temperature for a predetermined time t2 to grow the passivation layer 60 to the required thickness.

[0033] In another embodiment, the growth thickness of the passivation layer 60 in the low-temperature isothermal zone LT accounts for 0-25% of the total thickness of the passivation layer 60, the growth thickness of the passivation layer 60 in the heating zone RT accounts for 5-25% of the total thickness of the passivation layer 60, and the growth thickness of the high-temperature isothermal zone HT accounts for 50-95% of the total thickness of the passivation layer 60.

[0034] Furthermore, it should be noted that the heating rate of the heating section RT is preferably 10–30 °C / min, and the heating section RT is as follows: Figure 5 The diagram may include multiple heating steps, with the number of heating steps preferably being 1 to 15. By controlling the heating of each step to 30 to 60°C and the heating rate to be less than or equal to 60°C / min, a better passivation layer 60 quality can be obtained.

[0035] The high electron mobility transistor structure 1 manufactured by the above-described high electron mobility transistor structure manufacturing method has preferred thin film density, surface roughness performance, and voltage resistance. The refractive index of the passivation layer 60 is 2.05 to 2.28, the surface roughness RMS of the passivation layer 60 is less than or equal to 0.5 nm, and the breakdown voltage value that the passivation layer 60 can withstand per unit thickness is 1 to 1.15 V / nm. The refractive index is obtained by measuring an elliptic thickness gauge.

[0036] Furthermore, the high electron mobility transistor structure manufacturing method includes measuring the sheet resistance of the two-dimensional electron gas region of the channel layer 40 to obtain a first sheet resistance value, and measuring the sheet resistance of the two-dimensional electron gas region of the channel layer 40 after a time interval to obtain a second sheet resistance value. The time interval is greater than or equal to three months. The percentage change in sheet resistance value is defined as (second sheet resistance value - first sheet resistance value) / first sheet resistance value * 100%. The absolute value of the percentage change in sheet resistance value of the high electron mobility transistor structure 1 manufactured by the above-described high electron mobility transistor structure manufacturing method is less than or equal to 0.1%. That is to say, the high electron mobility transistor structure 1 manufactured by the above-described high electron mobility transistor structure manufacturing method has good sheet resistance value stability.

[0037] Please refer to Table 1. The following description is based on multiple comparative examples and multiple embodiments. It should be noted that the second resistor value was measured again four months after the first resistor value was measured. The definition of the percentage change in the resistor value is as described above and will not be repeated here.

[0038] [Comparative Examples AB]

[0039] In Comparative Examples A and B, no passivation layer was deposited above the barrier layer. The difference between Comparative Examples A and B is that the structure of Comparative Example A underwent an RCA cleaning process after measuring the resistance value of the first wafer, while the structure of Comparative Example B did not undergo an RCA cleaning process after measuring the resistance value of the first wafer. As shown in Table 1, the wafer resistance value of the structure of Comparative Example A significantly increased from 372.7 ohm / sq to 687 ohm / sq before and after the RCA cleaning process, while the wafer resistance value of the structure of Comparative Example B, even without performing the RCA cleaning process, still showed a change of 3.57%.

[0040] [Comparative Example CE]

[0041] In Comparative Example CE, a passivation layer is deposited on top of the barrier layer in an intermittent manner. The aforementioned intermittent means that after the barrier layer is deposited, the passivation layer is not continuously grown in the growth chamber of the barrier layer at the same temperature, pressure or atmosphere. The difference between Comparative Example CE and Comparative Example CE is that the structures of Comparative Examples C and D undergo an RCA cleaning process after measuring the resistance value of the first piece, while the structure of Comparative Example E does not perform an RCA cleaning process after measuring the resistance value of the first piece.

[0042] As shown in Table 1, the chip resistance values ​​measured before and after the RCA cleaning process of Comparative Examples C and D did not show significant differences. Compared with Comparative Example A, the chip resistance value increased by 1.8 times before and after the cleaning process, which is a significant improvement. In other words, depositing a passivation layer on top of the barrier layer can slightly improve the stability of the chip resistance value. Even without performing the RCA cleaning process, the chip resistance value of Comparative Example E still changed by a percentage of -0.87%.

[0043] [Example AB]

[0044] In Examples A and B, a passivation layer is deposited on top of the barrier layer in a continuous manner using the high electron mobility transistor structure manufacturing method described above. The difference between Examples A and B is that the structure in Example A undergoes an RCA cleaning process after measuring the resistance value of the first wafer, while the structure in Example B does not undergo an RCA cleaning process after measuring the resistance value of the first wafer. As shown in Table 1, there is no significant difference in the wafer resistance value measured before and after the RCA cleaning process for the structure in Example A, and the percentage change in wafer resistance value for both the structures in Examples A and B is -0.05%. In other words, the high electron mobility transistor structure manufactured by the high electron mobility transistor structure manufacturing method described above has good wafer resistance value stability, and the absolute value of the percentage change in wafer resistance value can be controlled below 0.1%.

[0045] Table 1

[0046]

[0047] The following description is based on a comparative example and several embodiments. First, it should be noted that in Comparative Example 1 and Embodiments 1-4, the passivation layer was continuously grown in the growth chamber of the barrier layer deposition chamber at the same temperature, pressure, or atmosphere without interruption after the barrier layer was deposited. The first growth temperature T1 was 900°C, and the second growth temperature T2 was 1000°C. The total thickness of the passivation layer 60, as described above, is the sum of the growth thicknesses of the passivation layer 60 in the low-temperature isothermal section LT, the heating section RT, and the high-temperature isothermal section HT. Furthermore, in Comparative Example 1 and Embodiments 1-4... The total thickness of the passivation layer in section 4 is the same, and the percentage of the thickness of the passivation layer 60 in the high-temperature isothermal zone HT is the percentage of the growth thickness of the passivation layer 60 in the high-temperature isothermal zone HT to the total thickness of the passivation layer 60; the percentage of the thickness of the passivation layer 60 in the heating zone RT is the percentage of the growth thickness of the passivation layer 60 in the heating zone RT to the total thickness of the passivation layer 60; and the percentage of the thickness of the passivation layer 60 in the low-temperature isothermal zone LT is the percentage of the growth thickness of the passivation layer 60 in the low-temperature isothermal zone LT to the total thickness of the passivation layer 60.

[0048] [Comparative Example 1]

[0049] In Comparative Example 1, such as Figure 6 As shown, the growth temperature of the passivation layer is controlled to be the same as the first growth temperature T1. That is, the growth temperature of the passivation layer is controlled to be maintained at the first growth temperature T1 for a predetermined time t3 in the low temperature constant temperature section LT, so that the barrier layer grows to a predetermined thickness at the same growth temperature as the passivation layer. As shown in Table 2, the thickness percentage of the passivation layer in Comparative Example 1 is 100% in the low temperature constant temperature section LT, 0% in the heating section RT, and 0% in the high temperature constant temperature section HT.

[0050] [Example 1]

[0051] In Example 1, as Figure 7 As shown, the growth temperature during the growth of the passivation layer is the second growth temperature T2. That is, the growth temperature of the passivation layer is controlled to rise rapidly from the first growth temperature T1 to the second growth temperature T2 and maintained at the second growth temperature for a predetermined time t4 in the high-temperature constant temperature zone HT to grow the passivation layer to a predetermined thickness. As shown in Table 2, the thickness percentage of the passivation layer in Example 1 is 0% in the low-temperature constant temperature zone LT, 0% in the heating zone RT, and 100% in the high-temperature constant temperature zone HT. It should be noted that since the time for the growth temperature of the passivation layer to rise from the first growth temperature T1 to the second growth temperature T2 is very short, the thickness of the passivation layer grown in the heating zone RT is close to zero.

[0052] [Example 2-3]

[0053] In Examples 2 and 3, as Figure 3 As shown in Table 2, the passivation layer is heated from the first growth temperature T1 to the second growth temperature T2 in the heating section RT, and then maintained at the second growth temperature T2 for a predetermined time t2 in the high-temperature constant-temperature section HT. In Example 2, the passivation layer has a thickness percentage of 0% in the low-temperature constant-temperature section LT, a thickness percentage of 25% in the heating section RT, and a thickness percentage of 75% in the high-temperature constant-temperature section HT. In Example 3, the passivation layer has a thickness percentage of 0% in the low-temperature constant-temperature section LT, a thickness percentage of 5% in the heating section RT, and a thickness percentage of 95% in the high-temperature constant-temperature section HT.

[0054] [Example 4]

[0055] In Example 4, as Figure 4 As shown in Table 2, the passivation layer growth temperature is controlled to maintain the first growth temperature T1 for a predetermined time ta in the low-temperature constant-temperature section LT, and then the first growth temperature is raised to the second growth temperature T2 in the heating section RT for a predetermined time tb. Then, the second growth temperature T2 is maintained for a predetermined time tc in the high-temperature constant-temperature section HT. As shown in Table 2, the passivation layer thickness percentage in Example 4 is 25% in the low-temperature constant-temperature section LT, 25% in the heating section RT, and 50% in the high-temperature constant-temperature section HT.

[0056] Please refer to Table 2. As shown in Examples 1-4, when the growth thickness of the passivation layer in the low-temperature isothermal section LT accounts for 0-25% of the total thickness of the passivation layer and the growth thickness in the heating section RT accounts for 0-25% of the total thickness of the passivation layer, the refractive index of the film in Examples 1-4 is 2.074-2.11. Compared with the refractive index of 2.014 of the film in Comparative Example 1, the structure of Examples 1-4 has a preferred refractive index performance.

[0057] Furthermore, as shown in Examples 2-3, when the passivation layer satisfies the following conditions: the growth thickness of the passivation layer in the low-temperature isothermal section LT accounts for 0% of the total thickness of the passivation layer; the growth thickness of the passivation layer in the heating section RT accounts for 5-25% of the total thickness of the passivation layer; and the growth thickness of the passivation layer in the high-temperature isothermal section HT accounts for 75-95% of the total thickness of the passivation layer, the breakdown voltages of Examples 2-3 are 1.05 and 1.1 V / nm, respectively, and the RMS roughness is less than 0.5 nm. In contrast, the breakdown voltage of Comparative Example 1 is 0.96 V / nm, and the RMS roughness is greater than 0.5 nm. In other words, the structure of Examples 2-3 has superior withstand voltage and RMS roughness performance compared to Comparative Example 1.

[0058] In addition, as shown in Examples 2-4, when the growth thickness of the passivation layer in the heating section RT accounts for 5-25% of the total thickness of the passivation layer, and the growth thickness in the high-temperature isothermal section HT accounts for 50-95% of the total thickness of the passivation layer, the change in sheet resistance value of Examples 2-4 is less than or equal to 0.1%, while the change in sheet resistance value of Comparative Example 1 is greater than 0.5%. That is to say, the structure of Examples 2-4 has preferred sheet resistance value stability compared to Comparative Example 1. Furthermore, based on the results of Examples 2-4, it can be directly seen that compared to completing the growth of the passivation layer entirely in the low-temperature isothermal section (Comparative Example 1) or entirely in the high-temperature isothermal section (Example 1), during the growth process of the passivation layer, controlling the first growth temperature T1 to rise to the second growth temperature in the heating section RT within a time interval (Example 2-4) can yield a structure with preferred sheet resistance value stability.

[0059] Table 2

[0060] Percentage of passivation layer thickness (%) in the high-temperature isothermal region 0 100 75 95 50 Percentage of passivation layer thickness in the heated zone (%) 0 0 25 5 25 Percentage of passivation layer thickness (%) in the low-temperature isothermal region 100 0 0 0 25 Refractive index 2.014 2.1 2.078 2.074 2.11 Breakdown voltage (V / nm) 0.96 1.04 1.05 1.1 0.95 Percentage change in chip resistance (%) >0.5 0.5～0.2 ≤0.1 ≤0.1 ≤0.1 RMS roughness (nm) >0.5 >0.5 <0.5 <0.5 >0.5

[0061] This invention provides another high electron mobility transistor structure 1, such as Figure 2As shown, the high electron mobility transistor structure 1 sequentially includes: a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a barrier layer 50, and a passivation layer 60; wherein, a two-dimensional electron gas region is formed in the channel layer 40 along the interface between the channel layer and the barrier layer 50; the sheet resistance change of the two-dimensional electron gas region of the channel layer 40 within a time interval is less than or equal to 1%, and the time interval is greater than or equal to three months. Through the formation of the passivation layer 60, the sheet resistance change of the two-dimensional electron gas region of the channel layer 40 within the time interval is less than or equal to 1%, and the time interval is greater than or equal to three months, thereby achieving the purpose of improving the stability of the high electron mobility transistor. In this embodiment, the high electron mobility transistor structure 1 is manufactured using the above-described high electron mobility transistor structure manufacturing method.

[0062] The passivation layer 60 is made of silicon nitride, with a total thickness of less than or equal to 100 nm, a refractive index of 2.05–2.28, a surface roughness RMS of less than or equal to 0.5 nm, and a breakdown voltage per unit thickness of 1–1.15 V / nm. In other words, the high electron mobility transistor structure 1 provided by this invention has preferred thin film density, surface roughness, breakdown voltage, and sheet resistance stability, thereby achieving the goal of improving the stability of the high electron mobility transistor.

[0063] In summary, the advantages of this invention are that by controlling the uninterrupted growth of the passivation layer 60 and the barrier layer 50 in the same growth chamber, defects in the passivation layer 60 during growth or degradation of the interface quality between the passivation layer 60 and the barrier layer 50 due to drastic changes in temperature, pressure, or atmosphere can be avoided. This provides a high-quality passivation layer 60 and a high-quality interface between the passivation layer and the barrier layer, thereby improving the performance of high electron mobility transistors. Furthermore, this invention also provides a high electron mobility transistor structure 1 in which, through the formation of the passivation layer 60, the sheet resistance change of the two-dimensional electron gas region of the channel layer 40 within the specified time interval is less than or equal to 1%, and the time interval is greater than or equal to three months, thereby improving the stability of the high electron mobility transistor.

[0064] The above description is only a preferred embodiment of the present invention. Any equivalent changes made by applying the present invention specification and the claims should be included within the patent scope of the present invention.

[0065] Explanation of reference numerals in the attached figures

[0066] [This invention]

[0067] S02, S04, S06, S08, S10, S12: Steps

[0068] 1: High electron mobility transistor structure

[0069] 10: Substrate

[0070] 20: Nucleation layer

[0071] 30: Buffer layer

[0072] 40: Channel Layer

[0073] 50: Barrier Layer

[0074] 60: Passivation layer

[0075] HT: high temperature constant temperature section

[0076] LT: Low-temperature isothermal zone

[0077] RT: Heating Zone

[0078] T1: First growth temperature

[0079] T2: Second growth temperature

[0080] t1,t2,t3,t4,ta,tb,tc: Reservation time

Claims

1. A method for manufacturing a high electron mobility transistor structure, comprising the following steps: A. Provide a substrate; B. A nucleation layer is formed above the substrate; C. A buffer layer is formed above the nucleation layer; D. A channel layer is formed above the buffer layer; E. A barrier layer is deposited above the channel layer, the growth temperature of the barrier layer is a first growth temperature, and a two-dimensional electron gas region is formed in the channel layer along the interface between the channel layer and the barrier layer. Step E is performed in a growth chamber. F. After performing step E, a passivation layer is continuously deposited above the barrier layer in the growth chamber, and the growth temperature of the passivation layer is controlled to increase from the first growth temperature through a heating section to a second growth temperature; wherein... Step F includes maintaining the second growth temperature within a high-temperature isothermal zone.

2. The method for manufacturing a high electron mobility transistor structure as described in claim 1, wherein, The barrier layer and the passivation layer are formed under the same growth conditions of pressure and atmosphere.

3. The method for manufacturing a high electron mobility transistor structure as described in claim 1, wherein, The percentage of the passivation layer thickness in the high-temperature isothermal zone to the total thickness of the passivation layer is greater than or equal to 50%.

4. The method for manufacturing a high electron mobility transistor structure as described in claim 1, wherein, The second growth temperature is greater than or equal to 1000℃.

5. The method for manufacturing a high electron mobility transistor structure as described in claim 1, wherein, The method includes measuring the sheet resistance of the two-dimensional electron gas region of the channel layer to obtain a first sheet resistance value, and measuring the sheet resistance of the two-dimensional electron gas region of the channel layer after a time interval of more than or equal to three months to obtain a second sheet resistance value, wherein the absolute value of the percentage change in sheet resistance value is less than or equal to 0.1%, and the percentage change in sheet resistance value is defined as (second sheet resistance value - first sheet resistance value) / first sheet resistance value. 100%.

6. A high electron mobility transistor structure manufactured by the method of any one of claims 1 to 5, comprising, in sequence: One substrate; One nucleation layer; A buffer layer; One channel layer; A barrier layer and a two-dimensional electron gas region are formed in the channel layer along the interface between the channel layer and the barrier layer; A passivation layer; in, The change in sheet resistance of the two-dimensional electron gas region of the channel layer within a time interval is less than or equal to 1%, and the time interval is greater than or equal to three months.

7. The high electron mobility transistor structure as described in claim 6, wherein, The total thickness of the passivation layer is less than or equal to 100 nm.

8. The high electron mobility transistor structure as described in claim 6, wherein, The refractive index of the passivation layer is 2.05 to 2.

28.

9. The high electron mobility transistor structure as described in claim 6, wherein, The surface roughness RMS of the passivation layer is less than or equal to 0.5 nm.

10. The high electron mobility transistor structure as described in claim 6, wherein, The passivation layer can withstand a breakdown voltage of 1 to 1.15 V / nm per unit thickness.

11. The high electron mobility transistor structure as described in claim 6, wherein, The passivation layer is silicon nitride.

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