Method of forming a semiconductor structure
By employing multiple etching processes in GAA structure MOSFETs, the channel layer is protected by the difference in etching rate of the modified layer, thus solving the problem of channel layer damage and improving the performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-05-05
- Publication Date
- 2026-07-21
AI Technical Summary
The electrical performance of existing GAA structure MOSFETs still needs to be improved, especially since damage to the channel layer during formation leads to performance instability.
By employing a multi-etching process, different modified layers are formed on the surfaces of the channel layer and the sacrificial layer through surface treatment, and the etching rate difference of each modified layer is controlled to protect the channel layer and reduce damage.
This improves the morphological quality of the channel layer, ensures the performance stability and consistency of the semiconductor structure, and enhances the performance of the final semiconductor structure.
Smart Images
Figure CN117059490B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most important components in modern integrated circuits. The basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and source and drain doped regions located in the semiconductor substrate on both sides of the gate structure.
[0003] With the further development of semiconductor technology, traditional fin field-effect transistors (FETs) face limitations in increasing their operating current. Specifically, because only the area near the top surface and sidewalls of the fin is used as the channel region, the volume of the channel region within the fin is relatively small, which limits the increase in the operating current of the FET. Therefore, a gate all-around (GAA) MOSFET structure has been proposed, which increases the volume of the channel region and further increases the operating current of the GAA structure MOSFET.
[0004] However, the electrical performance of GAA structure MOSFETs in the existing technology still needs to be improved. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the final semiconductor structure.
[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a fin structure on the substrate, the fin structure including a plurality of sacrificial layers overlapping along the normal direction of the substrate surface, and a channel layer located between two adjacent sacrificial layers; etching the exposed sacrificial layers using a plurality of etching processes, each etching process including: performing surface treatment on the exposed sacrificial layers and the channel layer to form a first modified layer on the surface of the sacrificial layers and a second modified layer on the surface of the channel layer; performing a first etching process on the first modified layer and the second modified layer, etching a portion of the first modified layer, wherein the etching rate of the first modified layer in the first etching process is greater than the etching rate of the second modified layer; and after the first etching process, continuing to perform a second etching process on the remaining first modified layer and the sacrificial layers, wherein the etching rate of the sacrificial layer in the second etching process is greater than the etching rate of the channel layer.
[0007] Optionally, the surface treatment process includes an oxidation process.
[0008] Optionally, the oxidation process involves treating the substrate with ozonated deionized water or hydrogen peroxide.
[0009] Optionally, the material of the first modified layer is germanium monoxide, germanium dioxide, and a mixture containing silicon oxide; the thickness of the first modified layer is 0 angstroms to 30 angstroms.
[0010] Optionally, the material of the second modified layer is silicon oxide, and the thickness of the second modified layer is 5 to 30 angstroms.
[0011] Optionally, the first etching process is a first wet etching process, in which water is used as the etching solution.
[0012] Optionally, the second etching process is a second wet etching, which is an isotropic wet etching.
[0013] Optionally, the second wet etching process uses a mixture of ammonia, hydrogen peroxide, and water as the etching solution.
[0014] Optionally, in the second etching process, the ratio of the etching rate of the etching solution on the sacrificial layer to the etching rate of the etching solution on the channel layer ranges from 4:1 to 150:1.
[0015] Optionally, the volume ratio of the ammonia water to the hydrogen peroxide is 1:20 to 20:1.
[0016] Optionally, the sacrificial layer is made of silicon-germanium; the channel layer is made of monocrystalline silicon.
[0017] Optionally, the atomic percentage concentration of germanium atoms in the silicon-germanium complex ranges from 20% to 40%.
[0018] Optionally, the thickness of the sacrificial layer is 2nm to 50nm, and the thickness of the channel layer is 2nm to 50nm.
[0019] Optionally, it further includes: forming a pseudo-gate structure across the fin structure on the substrate, the pseudo-gate structure covering a portion of the sidewalls and top surface of the fin structure.
[0020] Optionally, it further includes: etching the fin structures on both sides of the dummy gate structure to form source / drain grooves within the fin structures, the sidewalls of the source / drain grooves exposing the sacrificial layer and the channel layer; and etching the sacrificial layer exposed by the source / drain grooves using a number of etching processes to form fin grooves within adjacent channel layers.
[0021] Optionally, the method further includes: forming a source / drain doped layer within the source / drain trench; forming a dielectric layer on the substrate, the fin structure, and the sidewall surface of the dummy gate structure, the dielectric layer exposing the top surface of the dummy gate structure; removing the dummy gate structure to form a gate opening within the dielectric layer; etching the gate opening to expose the sacrificial layer using several etching processes to form a gate trench between adjacent channel layers; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the channel layer.
[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0023] In the technical solution of this invention, during the etching process of the exposed sacrificial layer using several etching processes, a second modified layer is formed on the surface of the channel layer and a first modified layer is formed on the surface of the sacrificial layer. During the first etching process, the etching rate of the first modified layer is greater than the etching rate of the second modified layer, and during the second etching process, the etching rate of the sacrificial layer is greater than the etching rate of the channel layer. In this way, the second modified layer can protect the channel layer, and the large etching rate difference reduces damage to the channel layer during the removal of the sacrificial layer. This can effectively improve the morphology of the channel layer and ensure the performance of the final semiconductor structure. Attached Figure Description
[0024] Figures 1 to 2 This is a schematic diagram of a semiconductor structure.
[0025] Figures 3 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure in the first embodiment of the present invention;
[0026] Figures 15 to 22 This is a schematic diagram of the steps in the method for forming a semiconductor structure in the second embodiment of the present invention. Detailed Implementation
[0027] As described in the background section, the electrical performance of existing GAA structure MOSFETs still needs improvement. This will be explained in detail below with reference to the accompanying drawings.
[0028] Please refer to Figure 1 A substrate 100 is provided; a fin structure is formed on the substrate 100, the fin structure including a plurality of sacrificial layers 101 overlapping along the normal direction of the substrate surface, and a channel layer 102 located between two adjacent sacrificial layers 101; a pseudo-gate structure 103 is formed on the substrate 100 that spans the fin structure, the pseudo-gate structure 103 covering part of the sidewalls and part of the top surface of the fin structure.
[0029] Please refer to Figure 2 Source / drain grooves 104 are formed in the fin structures on both sides of the pseudo-gate structure 103; the portion of the sacrificial layer 101 exposed on the sidewall of the source / drain groove 104 is removed to form fin grooves 105.
[0030] However, in the above embodiment, in subsequent processes, a barrier layer (not shown) needs to be formed within the fin recess 105; after forming the barrier layer, the sacrificial layer 101 is removed, and a gate trench (not shown) is formed between adjacent channel layers 102; after forming the gate trench, a gate structure (not shown) is formed within the gate trench. Since the formation of the fin recess 105 and the removal of the sacrificial layer 101 both result in varying degrees of loss of the channel layer 102, the shape and length of the channel region formed by the gate structure surrounding the channel layer 102 will differ after the gate structure is formed. This leads to differences in the performance of the various MOS structures formed, resulting in poor performance of the final semiconductor structure.
[0031] Based on this, the present invention provides a method for forming a semiconductor structure. During the etching process of the exposed sacrificial layer using several etching processes, a second modified layer is formed on the surface of the channel layer and a first modified layer is formed on the surface of the sacrificial layer. In the first etching process, the etching rate of the first modified layer is greater than the etching rate of the second modified layer. In the second etching process, the etching rate of the sacrificial layer is greater than the etching rate of the channel layer. In this way, the second modified layer can protect the channel layer, and the large etching rate difference reduces damage to the channel layer during the removal of the sacrificial layer. This can effectively improve the morphology of the channel layer and ensure the performance of the final semiconductor structure.
[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0033] Figures 3 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure in the first embodiment of the present invention;
[0034] Figures 15 to 22 This is a schematic diagram of the steps in the method for forming a semiconductor structure in the second embodiment of the present invention.
[0035] First Embodiment
[0036] Please refer to Figure 3 Substrate 200 is provided.
[0037] The substrate 200 can be made of single-crystal silicon (Si) or silicon germanium (SiGe); in this embodiment, the substrate 200 is made of silicon germanium (SiGe).
[0038] Please refer to Figure 4 A fin structure is formed on the substrate 200. The fin structure includes several layers of sacrificial layers 201 that overlap along the normal direction of the surface of the substrate 200, and a channel layer 202 located between two adjacent sacrificial layers 201.
[0039] In this embodiment, the sacrificial layer 201 has three layers; the channel layer 202 also has three layers.
[0040] In this embodiment, the thickness of the sacrificial layer 201 is 2nm to 50nm, and the thickness of the channel layer 202 is 2nm to 50nm.
[0041] In this embodiment, the method for forming the fin structure includes: forming a fin material film (not shown) on the substrate 200, the fin material film including a plurality of sacrificial material films overlapping along the normal direction of the surface of the substrate 200, and a channel material film located between two adjacent sacrificial material films; forming a patterned layer (not shown) on the fin material film; etching the fin material film using the patterned layer as a mask to form the fin structure, the fin structure including a plurality of sacrificial layers 201 overlapping along the normal direction of the surface of the substrate 200, and a channel layer 202 located between two adjacent sacrificial layers 201.
[0042] In this embodiment, the sacrificial layer 201 and the channel layer 202 are made of different materials. The purpose is that the sacrificial layer 201 needs to be removed when the gate structure is subsequently formed. Therefore, by using different materials, the sacrificial layer 201 and the channel layer 202 have a larger etching selectivity, reducing the damage to the channel layer 202 during the removal of the sacrificial layer 201.
[0043] In this embodiment, the sacrificial layer 201 is made of silicon germanium (SiGe), and the channel layer 202 is made of single-crystal silicon (Si).
[0044] In this embodiment, the atomic percentage concentration of germanium atoms in the silicon-germanium (SiGe) ranges from 20% to 40%.
[0045] In this embodiment, after etching the fin material film to form the fin structure, the method further includes: etching a portion of the substrate 200 using the fin structure as a mask; forming an isolation structure 203 on the substrate 200, wherein the top surface of the isolation structure 203 is lower than the top surface of the substrate 200.
[0046] The material of the isolation structure 203 includes silicon oxide (SiO2) or silicon nitride (SiN). In this embodiment, the material of the isolation structure 203 is silicon nitride (SiN).
[0047] Please refer to Figure 5 A pseudo-gate structure is formed on the substrate 200, spanning the fin structure, and the pseudo-gate structure covers part of the sidewalls and top surface of the fin structure.
[0048] In this embodiment, the dummy gate structure includes: a gate dielectric layer 204 located on the fin structure, a dummy gate layer 205 located on the gate dielectric layer 204, a protective layer 206 located on the dummy gate layer 205, and a sidewall 207 located on the sidewalls of the dummy gate layer 205 and the protective layer 206.
[0049] In this embodiment, the dummy gate layer 205 is made of polycrystalline silicon (Si); in other embodiments, the dummy gate layer may also be made of amorphous silicon (A-Si).
[0050] In this embodiment, the protective layer 206 is made of silicon nitride (SiN); in other embodiments, the protective layer may also be made of silicon oxide (SiO2).
[0051] The method for forming the sidewall 207 includes: forming a sidewall material layer (not shown) on the top surface of the gate dielectric layer 204, the sidewall of the dummy gate layer 205, and the sidewall and top surface of the protective layer 206; and etching the sidewall material layer back until the protective layer 206 and the top surface of the gate dielectric layer 204 are exposed, thereby forming the sidewall 207.
[0052] The sidewall material layer is formed by one or more of the following processes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0053] In this embodiment, the sidewall material layer is formed using atomic layer deposition (ALD).
[0054] The sidewall 207 is made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), or silicon oxycarbonate (SiOCN).
[0055] In this embodiment, the sidewall 207 is made of silicon nitride (SiN).
[0056] In this embodiment, the sidewall 207 is used to define the location of the subsequent source / drain doped layers.
[0057] Please refer to Figure 6Source / drain grooves 208 are formed in the fin structures on both sides of the pseudo-gate structure.
[0058] In this embodiment, the method for forming the source / drain groove 208 includes: etching the fin structure using the dummy gate structure as a mask until the top surface of the substrate 200 is exposed, and forming the source / drain groove 208 in the fin structure on both sides of the dummy gate structure.
[0059] In this embodiment, the source / drain groove 208 serves to provide space for the subsequently formed source / drain doped layer.
[0060] The etching process for the fin structure includes either an anisotropic dry etching process or anisotropic wet etching process. In this embodiment, the etching process for the fin structure is anisotropic dry etching process. The parameters of the dry etching process include: the etching gases used are HBr and Ar, wherein the flow rate of HBr is 10 sccm to 1000 sccm, and the flow rate of Ar is 10 sccm to 1000 sccm.
[0061] The exposed sacrificial layer is etched using a series of etching processes to form fin grooves. Each etching process includes surface treatment, a first etching process, and a second etching process. Please refer to [reference needed] for details. Figures 7 to 9 .
[0062] Please refer to Figure 7 The exposed sacrificial layer 201 and the channel layer 202 are then surface-treated.
[0063] In this embodiment, the surface treatment is a surface oxidation treatment.
[0064] In this embodiment, after the surface treatment, a first modified layer is formed on the surface of the sacrificial layer and a second modified layer is formed on the surface of the channel layer. Specifically, an oxidation process is used to form a modified layer 210 on the exposed sidewalls of the sacrificial layer 201 and the channel layer 202.
[0065] In this embodiment, the oxidation process uses ozonated deionized water or hydrogen peroxide to treat the substrate 200.
[0066] In this embodiment, a first modified layer 211 is formed on the sidewall of the sacrificial layer 201, and a second modified layer 212 is formed on the sidewall of the channel layer 202.
[0067] In this embodiment, the thickness of the first modified layer 211 ranges from 0 angstroms to 30 angstroms. When the thickness of the first modified layer 211 is greater than 30 angstroms, it will lead to low removal efficiency of the sacrificial layer 201 during the subsequent second etching process, making the process difficult to control.
[0068] In this embodiment, the thickness of the second modified layer 212 ranges from 5 angstroms to 30 angstroms; when the thickness of the second modified layer 212 is less than 5 angstroms, it is difficult to suppress the etching effect on the channel layer 202 during the second etching process.
[0069] In this embodiment, after the oxidation process, the material of the first modified layer 211 formed on the sidewall of the sacrificial layer 201 is germanium monoxide (GeO), germanium dioxide (GeO2), and a mixture containing silicon oxide (SiO2), wherein germanium monoxide (GeO) is soluble in water; at the same time, the second modified layer 212 formed on the sidewall of the channel layer 202 is a mixture containing silicon oxide (SiO2), wherein silicon oxide (SiO2) is insoluble in water.
[0070] Please refer to Figure 8 The first modified layer 211 and the second modified layer 212 are subjected to a first etching process.
[0071] In this embodiment, the first etching process is a wet etching process, and the first wet etching uses water as the etching solution.
[0072] In this embodiment, the substrate 200 is washed with water.
[0073] In this embodiment, the first modified layer 211 and the second modified layer 212 are subjected to a first etching process, which etches a portion of the first modified layer 211. The etching rate of the first modified layer 211 is greater than the etching rate of the second modified layer 212. Specifically, after washing with water, the first modified layer 211 becomes thinner, while the second modified layer 212 remains on the sidewall of the channel layer 202.
[0074] In other embodiments, after being washed with water, the first modified layer 211 detaches from the sidewall of the sacrificial layer 201.
[0075] Please refer to Figure 9 After the first etching process, the remaining first modified layer 211 and the sacrificial layer 201 are subjected to a second etching process.
[0076] In this embodiment, the second etching process has a higher etching rate on the sacrificial layer 201 than on the channel layer 202.
[0077] In this embodiment, after the second etching process, a portion of the sacrificial layer 201 is removed, and a fin groove 209 is formed between two adjacent channel layers 202.
[0078] In this embodiment, during the first etching process, the etching rate of the first modified layer is greater than that of the second modified layer. Therefore, after the first etching process, the presence of the second modified layer 212 protects the channel layer 202 during the second etching process. Simultaneously, during the second etching process, the etching rate of the sacrificial layer 201 is greater than that of the channel layer 202. This protects the channel layer 202 during the etching of the sacrificial layer 201, preventing damage. Furthermore, the greater etching rate of the sacrificial layer 201 reduces corrosion of the channel layer 202. This dual effect minimizes damage to the channel layer 202 during the removal of the sacrificial layer 201, improving the formation quality of the channel layer 202 and preparing for the formation of a high-quality semiconductor structure.
[0079] In this embodiment, the number of etching processes is designed according to actual needs, and there are no specific requirements.
[0080] In this embodiment, the function of the fin groove 209 is to provide space for the subsequently formed barrier layer.
[0081] In this embodiment, the second etching process is a second wet etching, and the second wet etching is an isotropic wet etching.
[0082] In this embodiment, isotropic wet etching can ensure the consistency of the etching direction during the etching process, thus preparing for the formation of the high-quality fin groove 209.
[0083] In this embodiment, the second wet etching uses a mixture of ammonia (NH3), hydrogen peroxide (H2O2) and water as the etching solution.
[0084] In this embodiment, the ratio of the etching rate of the etching solution on the sacrificial layer 201 to the etching rate of the etching solution on the channel layer 202 ranges from 4:1 to 150:1. When the ratio of the etching rate of the etching solution on the sacrificial layer 201 to the etching rate of the etching solution on the channel layer 202 is less than 4:1, the channel layer 202 is easily damaged during the etching process of removing the sacrificial layer 201, increasing the damage to the channel layer 202 and thus increasing the differences between different channel layers 202, which is not conducive to forming a semiconductor structure with stable performance.
[0085] In this embodiment, the volume ratio of ammonia (NH3) to hydrogen peroxide (H2O2) is 1:20 to 20:1. If the volume ratio of ammonia (NH3) to hydrogen peroxide (H2O2) is less than 1:20, the reaction rate is very slow and it is difficult to meet the process requirements. If the volume ratio of ammonia (NH3) to hydrogen peroxide (H2O2) is greater than 20:1, the reaction is too fast, and there is a risk that the single crystal silicon will be etched by alkaline anisotropy.
[0086] In this embodiment, the etching rate of the sacrificial layer 201 is adjusted by changing the ratio of ammonia (NH3) and hydrogen peroxide (H2O2) to achieve the desired etching rate.
[0087] In this embodiment, the step of forming the etching solution includes: mixing the ammonia (NH3) and the hydrogen peroxide (H2O2) into the water, wherein the temperature of the water is 23°C to 75°C. Within this temperature range, the maximum solubility of the ammonia (NH3) and the hydrogen peroxide (H2O2) can be achieved, while providing suitable stability for etching, thereby reducing damage to the channel layer 202 during the removal of the sacrificial layer 201.
[0088] In this embodiment, the etching rate of the etching solution on the sacrificial layer 201 is proportional to the atomic percentage concentration of germanium atoms.
[0089] Please refer to Figure 10 A barrier layer 213 is formed within the fin groove 209.
[0090] In this embodiment, the barrier layer 213 is made of silicon nitride.
[0091] Please refer to Figure 11 After the barrier layer 213 is formed, a source / drain doped layer 214 is formed in the source / drain groove 208, and the source / drain doped layer 214 contains source / drain ions.
[0092] In this embodiment, the second modified layer 212 is removed before the source / drain doped layer 214 is formed.
[0093] In this embodiment, the formation process of the source / drain doped layer 214 includes an epitaxial growth process; the process of doping the source / drain ions in the source / drain doped layer 214 includes an in-situ doping process.
[0094] When the semiconductor structure is a P-type device, the material of the source / drain doped layer 214 includes silicon (Si), germanium (Ge), or silicon-germanium (SiGe); the source / drain ions are P-type ions, including boron ions and BF ions. 2-The source / drain doped layer 214 is made of silicon, gallium arsenide, or indium gallium arsenide when the semiconductor structure is an N-type device; the source / drain ions are N-type ions, including phosphorus ions or arsenic ions.
[0095] Please refer to Figure 12 A dielectric layer 215 is formed on the substrate 200, the fin structure, and the sidewall surface of the dummy gate structure, the dielectric layer 215 exposing the top surface of the dummy gate structure.
[0096] Please refer to Figure 13 Remove the dummy gate structure and form a gate opening 216 in the dielectric layer 215.
[0097] Please refer to Figure 14 The gate opening 216 is removed to expose the sacrificial layer 201, a gate trench is formed between adjacent channel layers 202, and a gate structure is formed in the gate opening 216 and the gate trench, the gate structure surrounding the channel layer 202.
[0098] In this embodiment, the gate structure includes a gate layer 217.
[0099] The gate layer 217 is made of metal, and the metal material includes one or more combinations of copper (Cu), tungsten (W), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), and aluminum (Al).
[0100] In this embodiment, the gate layer 217 is made of tungsten (W).
[0101] Second Embodiment
[0102] The difference between the second embodiment and the first embodiment is that the gate opening is etched through several etching processes to expose the sacrificial layer, and a gate trench is formed between adjacent channel layers.
[0103] In this embodiment, the process from providing the substrate to forming the source / drain trenches is described in reference [reference needed]. Figures 3 to 6 .
[0104] Please refer to Figure 15 The sacrificial layer 201 exposed by the source drain 211 is etched to form fin grooves 218 between adjacent channel layers 202.
[0105] Please refer to Figure 16 A barrier layer 219 is formed within the fin groove 218.
[0106] Please refer to Figure 17After the barrier layer 219 is formed, a source / drain doped layer 220 is formed in the source / drain groove 208, and the source / drain doped layer 220 contains source / drain ions.
[0107] Please refer to Figure 18 A dielectric layer 221 is formed on the substrate 200, the fin structure, and the sidewall surface of the dummy gate structure, and the dielectric layer 221 exposes the top surface of the dummy gate structure.
[0108] Please refer to Figure 19 Remove the dummy gate structure and form a gate opening 222 in the dielectric layer 221.
[0109] In this embodiment, the gate opening 222 exposes the sacrificial layer 201.
[0110] The gate opening 222 is removed by a series of etching processes to expose the sacrificial layer 201, and a gate trench 223 is formed between adjacent channel layers 202.
[0111] Each etching process includes surface treatment, a first etching process, and a second etching process. Please refer to [reference needed] for details. Figures 20 to 22 .
[0112] Please refer to Figure 20 The exposed sacrificial layer 201 and the channel layer 202 are surface treated to form a first modified layer 224 on the surface of the sacrificial layer and a second modified layer 225 on the surface of the channel layer 202.
[0113] In this embodiment, the surface treatment is a surface oxidation treatment.
[0114] In this embodiment, the substrate 200 is treated with hydrogen peroxide.
[0115] In this embodiment, after the oxidation process, the material of the first modified layer 224 formed on the sidewall of the sacrificial layer 201 is germanium monoxide (GeO), germanium dioxide (GeO2), and a mixture containing silicon oxide (SiO2), wherein germanium monoxide (GeO) is soluble in water; at the same time, the second modified layer 225 formed on the sidewall of the channel layer 202 is a mixture containing silicon oxide (SiO2), wherein silicon oxide (SiO2) is insoluble in water.
[0116] Please refer to Figure 21 The first modified layer 224 and the second modified layer 225 are subjected to a first etching process.
[0117] In this embodiment, the first etching process is a wet etching process, and the first wet etching uses water as the etching solution.
[0118] In this embodiment, the substrate 200 is washed with water.
[0119] In this embodiment, the first modified layer 224 and the second modified layer 225 are subjected to a first etching process, which etches a portion of the first modified layer 224. The etching rate of the first modified layer 224 is greater than the etching rate of the second modified layer 225. Specifically, after washing with water, the first modified layer 224 becomes thinner, while the second modified layer 225 remains on the sidewall of the channel layer 202.
[0120] In this embodiment, to demonstrate the thinning of the first modified layer 224 after the first etching treatment, from Figure 21 The diagram shows the angle from which the first modified layer 224 has been removed. In reality, a portion of the first modified layer 224 is still attached to the sidewall of the sacrificial layer 201.
[0121] Please refer to Figure 22 After the first etching process, the remaining first modified layer 228 and the sacrificial layer 201 are subjected to a second etching process to form a gate trench 223 between adjacent channel layers 202.
[0122] In this embodiment, the second etching process has a higher etching rate on the sacrificial layer 201 than on the channel layer 202.
[0123] In this embodiment, after the second etching process, the gate opening 222 is removed to expose the sacrificial layer 201, and a gate trench 223 is formed between adjacent channel layers 202.
[0124] After forming the gate trench 223, the second modified layer 225 on the channel layer 202 is removed. The process of forming the gate structure is the same as in the first embodiment. Please refer to [reference needed]. Figure 14 I won't go into further detail here.
[0125] Third Embodiment
[0126] The difference between the third embodiment and the first embodiment is that the exposed sacrificial layer is etched using a series of etching processes to form fin grooves, and the gate opening is etched using a series of etching processes to expose the sacrificial layer, forming gate trenches between adjacent channel layers.
[0127] For the process of providing the substrate and forming the gate opening within the dielectric layer in this embodiment, please refer to the first embodiment. Figures 3 to 13 .
[0128] For the process from gate opening to gate trench formation in this embodiment, please refer to the second embodiment. Figures 19 to 22The process.
[0129] After the gate trench is formed in this embodiment, the gate structure is formed. Please refer to the first embodiment for details. Figure 14 .
[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A fin structure is formed on the substrate, the fin structure comprising a plurality of sacrificial layers overlapping along the normal direction of the substrate surface, and a channel layer located between two adjacent sacrificial layers; The exposed sacrificial layer is etched using a series of etching processes, each of which includes: The exposed sacrificial layer and the channel layer are surface treated to form a first modified layer on the surface of the sacrificial layer and a second modified layer on the surface of the channel layer. A first etching process is performed on the first modified layer and the second modified layer, wherein a portion of the first modified layer is etched, and the etching rate of the first modified layer is greater than the etching rate of the second modified layer. After the first etching process, a second etching process is performed on the remaining first modified layer and the sacrificial layer, wherein the etching rate of the sacrificial layer in the second etching process is greater than the etching rate of the channel layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The surface treatment process includes: oxidation treatment process.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The oxidation process involves treating the substrate with ozonated deionized water or hydrogen peroxide.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first modified layer is a mixture of germanium monoxide, germanium dioxide and silicon oxide; the thickness of the first modified layer is 0 angstroms to 30 angstroms.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second modified layer is silicon oxide, and the thickness of the second modified layer is 5 angstroms to 30 angstroms.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first etching process is a first wet etching process, in which water is used as the etching solution.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second etching process is a second wet etching, which is an isotropic wet etching.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The second wet etching method uses a mixture of ammonia, hydrogen peroxide and water as the etching solution.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the second etching process, the ratio of the etching rate of the etching solution on the sacrificial layer to the etching rate of the etching solution on the channel layer ranges from 4:1 to 150:
1.
10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The volume ratio of ammonia to hydrogen peroxide is 1:20 to 20:
1.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sacrificial layer is made of silicon-germanium; the channel layer is made of monocrystalline silicon.
12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The atomic percentage concentration of germanium atoms in the silicon-germanium alloy ranges from 20% to 40%.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the sacrificial layer is 2nm~50nm, and the thickness of the channel layer is 2nm~50nm.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A pseudo-gate structure is formed on the substrate, spanning the fin structure, and the pseudo-gate structure covers part of the sidewalls and top surface of the fin structure.
15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Also includes: The fin structures on both sides of the dummy gate structure are etched to form source / drain grooves within the fin structures, and the sidewalls of the source / drain grooves expose the sacrificial layer and the channel layer. The sacrificial layer exposed by the source / drain groove is etched using the etching process several times, forming fin grooves in adjacent channel layers.
16. The method for forming a semiconductor structure as described in claim 15, characterized in that, Also includes: A source / drain doped layer is formed within the source / drain groove; A dielectric layer is formed on the substrate, the fin structure, and the sidewall surface of the dummy gate structure, the dielectric layer exposing the top surface of the dummy gate structure; Remove the dummy gate structure and form a gate opening in the dielectric layer; etch the gate opening using the etching process several times to expose the sacrificial layer and form a gate trench between adjacent channel layers; A gate structure is formed within the gate opening and the gate trench, the gate structure surrounding the channel layer.