Method of fabricating a superconducting interconnect structure and superconducting interconnect structure

Abstract

The application provides a preparation method of a superconducting interconnection structure and the superconducting interconnection structure, and relates to the technical field of quantum chip. The application discloses a preparation method of a superconducting interconnection structure and the superconducting interconnection structure, and relates to the technical field of quantum chip. Compared with the prior art, the application forms the first window, so that the reaction source gas can enter the first surface of the substrate from the first window and is deposited around the through hole to form a complete superconducting layer in the atomic deposition process, so that the deposition of the double-sided superconducting layer is realized, the deposition of the TSV double-sided superconducting layer is realized, complete superconducting layers are formed on the first surface and the second surface of the TSV, the process is simplified, and the preparation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of quantum chip technology, and more specifically, to a method for fabricating a superconducting interconnect structure and the superconducting interconnect structure itself. Background Technology

[0002] Through Silicon Via (TSV) technology is considered the most promising technology for achieving three-dimensional integration. TSV technology enables direct interconnection between chips by creating vertical through-holes between chips and wafers. It allows for maximum chip stacking density in three dimensions, the shortest interconnect lines between chips, and the smallest overall size, significantly improving chip speed and reducing chip power consumption, thus becoming one of the most attractive technologies in electronic packaging today.

[0003] In the application of TSVs in quantum chips, the current conventional process involves depositing a superconducting interconnect layer on the front, back, and sidewalls of the TSV. Superconducting materials can be effectively deposited on the silicon wafer surface and within the vias. However, under current process conditions, with the substrate placed on a heating stage, there isn't enough deposition space on the back side of the TSV due to its close contact with the stage surface. The superconducting precursor can only grow near the vias, resulting in an incomplete back-side superconducting interconnect layer and the inability to form superconducting connections. Therefore, conventional techniques typically require depositing superconducting interconnect layers separately on the front and back sides, i.e., two deposition processes, which are cumbersome, lengthy, and inefficient. Summary of the Invention

[0004] The present invention aims to provide, for example, a method for fabricating a superconducting interconnect structure and a superconducting interconnect structure, which can achieve the deposition of a double-sided superconducting layer of a TSV by deposition, forming a complete superconducting layer on both the first and second surfaces of the TSV, thereby simplifying the process and improving the fabrication efficiency.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a method for fabricating a superconducting interconnect structure, comprising:

[0007] A mask layer is formed on the first of the two surfaces of the substrate;

[0008] A through-hole is formed on the substrate using the mask layer, the through-hole penetrating the substrate;

[0009] The mask layer is patterned to form a first window exposing the substrate, and the via is located within the first window;

[0010] The substrate is supported on a stage using the mask layer, and superconducting material is deposited thereon. A superconducting layer is deposited on the second surface of the substrate, inside the via, and inside the first window.

[0011] In an alternative embodiment, the first window is in communication with the outside of the substrate.

[0012] In an optional embodiment, prior to the step of forming a via on the substrate using the mask layer, the fabrication method further includes:

[0013] An etching stop layer is formed on the second surface of the substrate.

[0014] In an optional embodiment, prior to the step of supporting the substrate on a stage using the mask layer and performing superconducting material deposition, the fabrication method further includes:

[0015] The etching stop layer is patterned to form a second window exposing the substrate, and the via is located within the second window;

[0016] During the deposition of superconducting materials, the superconducting layer is formed within the second window, the through-hole, and the first window, wherein the superconducting layer is made of a different material than the etch stop layer.

[0017] In an optional embodiment, the superconducting layer is made of titanium nitride, and the etching stop layer is made of aluminum.

[0018] In an optional implementation, the superconducting layer is formed using atomic layer deposition when depositing the superconducting material.

[0019] In an optional embodiment, after the step of supporting the substrate on the stage using the mask layer and performing superconducting material deposition, the fabrication method further includes:

[0020] Remove the etching stop layer;

[0021] The superconducting layer on the first surface of the substrate is patterned to form a superconducting circuit.

[0022] In an optional embodiment, the superconducting layer is formed, and the preparation method further includes:

[0023] Remove the mask layer.

[0024] In an optional embodiment, after the step of removing the mask layer, the preparation method further includes:

[0025] The superconducting layers on the first and second surfaces of the substrate are patterned to form two interconnected superconducting circuits.

[0026] In an optional embodiment, the step of forming a via on the substrate using the mask layer includes:

[0027] The mask layer is patterned to form aperture-like openings;

[0028] The substrate is etched through the aperture to form a through hole with the same shape as the aperture.

[0029] In an optional embodiment, the material of the mask layer is at least one of silicon dioxide and silicon nitride.

[0030] In an optional embodiment, prior to the step of forming a mask layer on the first surface of the substrate, the fabrication method further includes:

[0031] Cleaning removes organic residues from the substrate surface.

[0032] Secondly, the present invention provides a superconducting interconnect structure, which is prepared by the superconducting interconnect structure preparation method described in any of the foregoing embodiments.

[0033] The beneficial effects of the embodiments of the present invention include, for example:

[0034] The superconducting interconnect structure fabrication method and superconducting interconnect structure provided in this invention first form a mask layer on the first surface of a substrate, then use the mask layer to form a through-hole (TSV) that penetrates the substrate, completing the fabrication of the TSV. Next, the mask layer is patterned to form a first window, which connects to the TSV. Then, the first surface of the substrate is placed on a stage, allowing the mask layer to support the substrate. Finally, a superconducting layer is simultaneously deposited within the TSV, the second surface of the substrate, and the first window. Compared to existing technologies, this invention, by forming the first window, allows the reaction source gas to be directly deposited on the second surface of the substrate and in the TSV during atomic deposition. Simultaneously, it allows the gas to enter the first surface of the substrate through the first window and deposit around the TSV to form a complete superconducting layer, thus achieving the deposition of a double-sided superconducting layer. This method simplifies the fabrication process and improves fabrication efficiency by achieving the deposition of a double-sided TSV, forming a complete superconducting layer on both the first and second surfaces of the TSV. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1This is a flowchart illustrating the steps of a method for fabricating a superconducting interconnect structure according to the first embodiment of the present invention.

[0037] Figures 2 to 12 A process flow diagram of the fabrication method of the superconducting interconnect structure provided in the first embodiment of the present invention;

[0038] Figures 13 to 16 This is a process flow diagram of the fabrication method of the superconducting interconnect structure provided in the second embodiment of the present invention.

[0039] Icons: 100 - Superconducting interconnect structure; 110 - Substrate; 111 - Via; 130 - Superconducting layer; 200 - Mask layer; 210 - Hole opening; 230 - First window; 300 - Etching stop layer; 310 - Second window. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0042] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0043] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0044] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0045] As disclosed in the background section, the prior art typically uses titanium nitride (TiN) as the superconducting interconnect layer. A TiN layer is deposited on the front, back, and sidewalls of the TSV using atomic layer deposition (ALD). Due to the conformal nature of ALD, it can be effectively deposited on the silicon wafer surface and within the through-silicon vias. However, under the current process conditions, the substrate is placed on the ALD heating stage. On the back side of the TSV, because it is in a close fit with the stage surface, there is not enough deposition space. This causes the precursor to grow only near the vias, resulting in an incomplete TiN layer on the back side and the inability to form a superconducting interconnect.

[0046] Therefore, conventional techniques typically employ a two-stage deposition process to form superconducting layers on the front and back sides of the substrate, respectively. Specifically, after forming the vias, the mask layer and etch stop layer on the substrate surface need to be removed. Then, atomic deposition is performed with the front side of the substrate facing upwards, followed by atomic deposition with the back side facing upwards, thereby forming a superconducting layer on the substrate surface. Patterning is then performed on each side. This process is cumbersome, lengthy, and inefficient.

[0047] To address the aforementioned problems, this invention provides a novel method for fabricating a superconducting interconnect structure and the superconducting interconnect structure itself. It should be noted that, unless otherwise specified, the features in the embodiments of this invention can be combined with each other.

[0048] First Embodiment

[0049] This embodiment provides a method for fabricating a superconducting interconnect structure, used to prepare a superconducting interconnect structure 100 ( Figure 12 As shown in the figure, it can achieve the deposition of a double-sided superconducting layer 130 on the TSV by deposition, forming a complete superconducting layer 130 on both the first and second surfaces of the TSV, which simplifies the process and improves the preparation efficiency.

[0050] See Figure 1 The method for fabricating the superconducting interconnect structure provided in this embodiment includes the following steps:

[0051] S1: Cleaning removes organic residues from the surface of substrate 110.

[0052] Specifically, see [link / reference] Figure 2 First, a substrate 110 is provided, and the substrate 110 can be cleaned, specifically by using a piranha solution to remove organic residues from the surface of the substrate 110. The substrate 110 can be a silicon wafer or a sapphire wafer.

[0053] S2: A mask layer 200 is formed on the first of the two surfaces of the substrate 110.

[0054] Specifically, in conjunction with see Figure 3The substrate 110 has a first surface and a second surface opposite to each other. The mask layer 200 is located on the first surface of the substrate 110. The material of the mask layer 200 can be at least one of silicon dioxide and silicon nitride. In actual fabrication, a layer of silicon dioxide can be deposited on the first surface of the substrate 110 as the mask layer 200, and then the via 111 can be fabricated using the mask layer 200.

[0055] S3: An etch stop layer 300 is formed on the second surface of the substrate 110.

[0056] Specifically, in conjunction with see Figure 4 The etch stop layer 300 can be an aluminum layer. After the mask layer 200 is formed, the substrate 110 can be flipped and an aluminum layer can be deposited on the second surface of the substrate 110 as the etch stop layer 300.

[0057] S4: Pattern the mask layer 200 to form aperture-like openings 210.

[0058] Specifically, in conjunction with see Figure 5 In some embodiments, when performing step S4, a photoresist layer can first be coated and patterned, and then the silicon dioxide layer can be etched, for example, by using reactive ion etching (RIE) to form a hole-like opening 210. Finally, residual photoresist is removed so that the surface of the substrate 110 in the hole-like opening 210 is exposed.

[0059] S5: The substrate 110 is etched through the aperture 210 to form a through hole 111 with the same shape as the aperture 210.

[0060] Specifically, in conjunction with see Figure 6 A through-hole 111 is formed by etching using a deep silicon etching device. The through-hole 111 penetrates the substrate 110 and stops after etching to the aluminum layer.

[0061] S6: Remove etch stop layer 300.

[0062] Specifically, in conjunction with see Figure 7 The etching stop layer 300 on the second surface of the substrate 110 can be removed by wet etching process, thereby completely exposing the second surface of the substrate 110.

[0063] S7: Pattern the mask layer 200 to form a first window 230 that exposes the substrate 110.

[0064] Specifically, in conjunction with see Figure 8The mask layer 200 can be patterned to form a first window 230 exposing the substrate 110, with the via 111 located within the first window 230. In some embodiments, when performing step S7, photoresist can first be applied to the mask layer 200 and then exposed and developed for patterning. It should be noted that excess pattern should be exposed during exposure to connect the internal pattern with the outside. Then, the mask layer 200 surrounding the aperture 210 is removed by etching with photoresist as a mask, forming the first window 230, which connects to the via 111 and extends from the via 111 to the edge of the substrate 110.

[0065] In actual etching, the silicon dioxide layer on the first surface of the substrate 110 can be etched, for example, by using reactive ion etching (RIE) to expand the aperture 210 to form the first window 230. Finally, the residual adhesive is removed so that the surface of the substrate 110 in the first window 230 is exposed.

[0066] S8: The substrate 110 is supported on the stage using the mask layer 200 and superconducting material is deposited.

[0067] Specifically, in conjunction with see Figure 9 The substrate 110 is supported on the stage using the mask layer 200 and superconducting material is deposited. During atomic layer deposition, a superconducting layer 130 can be deposited in the via 111, on the first surface and the second surface of the substrate 110. In some embodiments, when performing step S8, the side of the mask layer 200 away from the substrate 110 can be first attached to the stage, and then the superconducting layer 130 can be deposited in the via 111, in the first window 230 and on the second surface of the substrate 110 using atomic layer deposition. The superconducting layer 130 can be a superconducting metal, such as titanium nitride.

[0068] It should be noted that in this embodiment, since the mask layer 200 is not completely removed, and a first window 230 is formed on the mask layer 200, the mask layer 200 forms a support frame to support the first surface of the substrate 110 detached from the surface of the stage. Because there is a layer of silicon dioxide several micrometers thick between the first surface of the substrate 110 and the surface of the stage, and the first window 230 is not blocked, reactive gas can enter the first surface of the substrate 110 through the first window 230 and deposit and grow the superconducting layer 130 on the first surface of the substrate 110. Furthermore, the thickness of the mask layer 200 is only a few micrometers, for example, 4-8 micrometers. Therefore, the temperature of the substrate 110 will not be too low due to the distance between the first surface of the substrate 110 and the surface of the stage, thus avoiding the inability to meet the deposition requirements of the superconducting layer 130 due to an excessively low substrate temperature, ensuring the successful deposition of the superconducting layer 130.

[0069] S9: Remove mask layer 200.

[0070] Specifically, see Figure 10 The remaining silicon dioxide layer on the first surface of the substrate 110 can be removed by wet etching, leaving only the superconducting layer 130 on the first surface. At this time, the superconducting layer 130 already has a certain pattern.

[0071] S10: Pattern the superconducting layer 130 on the first and second surfaces of the substrate 110 to form two interconnected superconducting circuits.

[0072] Specifically, the superconducting layer 130 on the first surface of the substrate 110 can first be patterned to obtain a superconducting circuit layer on the first surface, and then the adhesive can be removed to eliminate excess lines, such as... Figure 11 Then, the superconducting layer 130 on the second surface of the substrate 110 is patterned to obtain a superconducting circuit layer on the second surface, and the adhesive is removed, as shown below. Figure 12 The superconducting circuit layer is the expected superconducting circuit. The superconducting circuits on the first and second surfaces can be electrically connected through the superconducting material in the through-hole 111 to form a superconducting interconnect.

[0073] Please continue reading Figure 11 and Figure 12 This embodiment also provides a superconducting interconnect structure 100, which is prepared by the aforementioned preparation method. The superconducting interconnect structure 100 includes a substrate 110 and a superconducting layer 130. The substrate 110 has a first surface and a second surface opposite to each other, and a through hole 111 is provided on the substrate 110. The through hole 111 penetrates the substrate 110. The superconducting layer 130 is disposed in the first surface and the second surface of the substrate 110 and in the through hole 111. The superconducting layer 130 on the first surface and the second surface of the substrate 110 can form a superconducting circuit. The superconducting circuits on both sides are connected through the superconducting layer 130 in the through hole 111, thereby forming a superconductivity.

[0074] In summary, the fabrication method and superconducting interconnect structure 100 provided in this embodiment first form a mask layer 200 on the first surface of a substrate 110, then pattern the mask layer 200 to form a hole-like opening 210, and then etch a through-hole 111 on the substrate 110 through the hole-like opening 210. The through-hole 111 penetrates the substrate 110, completing the fabrication of the silicon through-hole 111. Then, the mask layer 200 is patterned to form a first window 230, which extends from the through-hole 111 to the edge of the substrate 110. Then, the first surface of the substrate 110 is placed on a stage so that the mask layer 200 can support the substrate 110. Then, a superconducting layer 130 is deposited simultaneously in the through-hole 111, on the first surface and the second surface of the substrate 110. Finally, the mask layer 200 is removed. Compared to existing technologies, this embodiment, by forming a first window 230, allows the reaction source gas to be directly deposited on the second surface of the substrate 110 and in the via 111 during the atomic deposition process. On the other hand, it can enter the first surface of the substrate 110 through the first window 230 and deposit around the via 111 to form a complete superconducting layer 130, thereby achieving the deposition of a double-sided superconducting layer 130. By using deposition to achieve the deposition of the TSV double-sided superconducting layer 130, a complete superconducting layer 130 is formed on both the first and second surfaces of the TSV, simplifying the process and improving the preparation efficiency. Furthermore, the superconducting layer 130 formed on the first surface of the substrate 110 can be pre-patterned, simplifying the subsequent patterning process.

[0075] Second Embodiment

[0076] This embodiment provides a method for fabricating a superconducting interconnect structure. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0077] The fabrication method of the superconducting interconnect structure provided in this embodiment is the same as that in the first embodiment in steps S1 and S2, which can be referred to in the first embodiment for details. The difference between the first embodiment and the fabrication method in this embodiment is that the fabrication method further includes the following steps:

[0078] S3: Pattern the mask layer 200 to form aperture-like openings 210.

[0079] S4: The substrate 110 is etched through the aperture 210 to form a through hole 111 with the same shape as the aperture 210.

[0080] S5: Pattern the mask layer 200 to form a first window 230 that exposes the substrate 110.

[0081] S6: The substrate 110 is supported on the stage using the mask layer 200 and superconducting material is deposited.

[0082] S7: Remove mask layer 200.

[0083] S8: Pattern the superconducting layer 130 on the first and second surfaces of the substrate 110 to form two interconnected superconducting circuits.

[0084] It should be noted that, compared with the first embodiment, this embodiment omits the preparation of the etching stop layer 300 and directly performs hole etching, thus simplifying the process steps.

[0085] Third Embodiment

[0086] This embodiment provides a method for fabricating a superconducting interconnect structure. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0087] The fabrication method of the superconducting interconnect structure provided in this embodiment is the same as that in the first embodiment in steps S1-S5, and you can refer to the first embodiment for details. The difference between the first embodiment and the first embodiment is that the fabrication method in this embodiment also includes the following steps:

[0088] S6: Pattern the etch stop layer 300 to form a second window 310 exposing the substrate 110.

[0089] Specifically, in conjunction with see Figure 13 In some embodiments, during step S6, a photoresist layer can first be uniformly coated onto the etch stop layer 300 and patterned by exposure. Then, the etch stop layer 300 can be etched, for example, using reactive ion etching (RIE), to form a second window 310. The via 111 is located within the second window 310. Finally, residual photoresist is removed, exposing the surface of the substrate 110 within the second window 310. An etchant with good etching effect on aluminum layers can be used, and the pattern of the second window 310 is the pattern of the desired superconducting layer 130.

[0090] S7: Pattern the mask layer 200 to form a first window 230 that exposes the substrate 110.

[0091] Specifically, in conjunction with see Figure 14 First, photoresist can be uniformly applied to the mask layer 200 and then exposed and developed to form a pattern. It is important to note that during exposure, excess pattern should be exposed to connect the internal pattern with the external environment. Then, the mask layer 200 around the aperture 210 can be etched away using photoresist as a mask to form a first window 230, which extends from the via 111 to the edge of the substrate 110.

[0092] S8: The substrate 110 is supported on the stage using the mask layer 200 and superconducting material is deposited.

[0093] Specifically, see Figure 15 First, the mask layer 200 can be placed on the stage with the side of the mask layer away from the substrate 110 attached. Then, an atomic layer deposition method is used to deposit a superconducting layer 130 on the surface of the substrate 110 in the via 111, the first window 230 and the second window 310.

[0094] It should be noted that the material of the superconducting layer 130 here needs to be different from the material of the etch stop layer 300. For example, the material of the superconducting layer 130 is titanium nitride, and the material of the etch stop layer 300 is aluminum.

[0095] S9: Remove mask layer 200.

[0096] Specifically, see Figure 16 The remaining silicon dioxide layer on the first surface of the substrate 110 can be removed by wet etching, leaving only the superconducting layer 130 on the first surface. At this time, the superconducting layer 130 already has a certain pattern.

[0097] S10: Pattern the superconducting layer 130 on the first surface of the substrate 110 to form a superconducting circuit.

[0098] Specifically, a wet etching process can be used to pattern the superconducting layer 130 on the first surface of the substrate 110 to obtain a superconducting circuit layer on the first surface, and then the resist can be removed to eliminate excess lines, such as... Figure 11 .

[0099] S11: Remove etch stop layer 300.

[0100] For details, please continue to see Figure 12 Excess aluminum can be removed using a wet etching process, leaving only the superconducting layer 130 on the second surface. At this point, the superconducting layer 130 has been patterned and forms the superconducting circuit layer on the second surface.

[0101] It is worth noting that in this embodiment, by patterning the etch stop layer 300 on the second surface of the substrate 110, a pattern of a double-sided superconducting layer 130 can be deposited and grown during the atomic deposition process, avoiding the need for subsequent re-patterning of the superconducting layer 130, further simplifying the process and improving efficiency.

[0102] The superconducting interconnect structure fabrication method and superconducting interconnect structure 100 provided in this embodiment first form a mask layer 200 on the first surface of a substrate 110 and an etch stop layer 300 on the second surface. Then, the mask layer 200 is patterned to form a hole-like opening 210. Through the hole-like opening 210, a through-hole 111 is etched on the substrate 110, which penetrates the substrate 110 to complete the fabrication of the silicon through-hole 111. Then, the etch stop layer 300 is patterned to form a second window 310. Then, the mask layer 200 is patterned again to form a first window 230, which extends from the through-hole 111 to the edge of the substrate 110. Then, the first surface of the substrate 110 is placed on a stage so that the mask layer 200 can support the substrate 110. Then, a superconducting layer 130 is deposited simultaneously in the through-hole 111, the first window 230, and the second window 310. Finally, the mask layer 200 and the etch stop layer 300 are removed. Compared with the first embodiment, this embodiment, through the preparation of the second window 310, enables the formation of a patterned superconducting layer 130 on both the first and second surfaces of the substrate 110 during the atomic deposition process, thereby achieving the patterning of the double-sided superconducting layer 130 through deposition growth, further simplifying the process and improving efficiency.

[0103] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a superconducting interconnect structure, characterized in that, include: A mask layer (200) is formed on the first of the two surfaces of the substrate (110). A through-hole (111) is formed on the substrate (110) using the mask layer (200). The mask layer (200) is patterned to form a first window (230) exposing the substrate (110), and the via (111) is located within the first window (230); The substrate (110) is supported on a stage using the mask layer (200) and superconducting material is deposited thereon. A superconducting layer (130) is deposited on the second surface of the two surfaces of the substrate (110), inside the via (111) and inside the first window (230). The first window (230) is in external communication with the substrate (110).

2. The method for fabricating the superconducting interconnect structure according to claim 1, characterized in that, After the superconducting layer (130) is formed, the preparation method further includes: Remove the mask layer (200).

3. The method for fabricating the superconducting interconnect structure according to claim 2, characterized in that, Prior to the step of forming a via (111) on the substrate (110) using the mask layer (200), the fabrication method further includes: An etch stop layer (300) is formed on the second surface of the substrate (110). The etching stop layer (300) is patterned to form a second window (310) exposing the substrate (110), and the via (111) is located within the second window (310); During the deposition of superconducting materials, the superconducting layer (130) is formed in the second window (310), the through hole (111), and the first window (230), wherein the superconducting layer (130) is made of a different material than the etch stop layer (300).

4. The method for fabricating a superconducting interconnect structure according to claim 3, characterized in that, The superconducting layer (130) is made of titanium nitride, and the etching stop layer (300) is made of aluminum.

5. The method for fabricating a superconducting interconnect structure according to claim 3, characterized in that, When depositing superconducting materials, the superconducting layer (130) is formed using atomic layer deposition.

6. The method for fabricating the superconducting interconnect structure according to claim 3, characterized in that, After the step of supporting the substrate (110) on the stage using the mask layer (200) and performing superconducting material deposition, the fabrication method further includes: Remove the etching stop layer (300); The superconducting layer (130) on the first surface of the substrate (110) is patterned to form a superconducting circuit.

7. The method for fabricating a superconducting interconnect structure according to claim 2, characterized in that, After the step of removing the mask layer (200), the preparation method further includes: The superconducting layer (130) on the first and second surfaces of the substrate (110) is patterned to form two interconnected superconducting circuits.

8. The method for fabricating a superconducting interconnect structure according to claim 1, characterized in that, The step of forming a via (111) on the substrate (110) using the mask layer (200) includes: The mask layer (200) is patterned to form aperture-like openings (210). The substrate (110) is etched through the aperture (210) to form a through hole (111) with the same shape as the aperture (210).

9. A superconducting interconnect structure, characterized in that, It is prepared using the method for preparing a superconducting interconnect structure as described in any one of claims 1-8.

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