Semiconductor device and method of forming the same, semiconductor structure

Abstract

A semiconductor device and a forming method thereof, and a semiconductor structure, the device comprising: a substrate comprising a shielding region and a protection region surrounding the shielding region; a shielding structure on the substrate in the shielding region; a bottom protection ring on the substrate in the protection region and surrounding the shielding structure, and used for grounding, the shielding structure being electrically connected with the bottom protection ring, the bottom protection ring comprising: a plurality of first conductive layers on the substrate in the protection region, the plurality of first conductive layers extending along a first direction and being arranged in parallel along a second direction, the plurality of first conductive layers forming a shape surrounding the shielding region, the first direction being perpendicular to the second direction; and a plurality of second conductive layers on the substrate in the protection region, the plurality of second conductive layers extending along the second direction and being arranged in parallel along the first direction, the plurality of second conductive layers forming a shape surrounding the shielding region, each second conductive layer penetrating the plurality of first conductive layers in the region where the second conductive layer is located along the second direction and being electrically connected with the plurality of first conductive layers. The application is beneficial to improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor device and a method for forming the same, and a semiconductor structure. Background Technology

[0002] In integrated circuits (ICs), such as CMOS radio frequency integrated circuits (RFICs), sensing devices are crucial electrical components whose performance parameters directly impact the overall performance of the IC. Most sensing devices in integrated circuits are planar inductors, such as planar spiral inductors. Compared to traditional wire-wound inductors, planar inductors offer advantages such as lower cost, easier integration, lower noise, and lower power consumption. Furthermore, planar inductors have high compatibility with existing integrated circuit manufacturing processes.

[0003] A key indicator for evaluating the performance of sensing devices is the quality factor (Q). A higher Q factor indicates better performance. One crucial factor affecting the Q factor is substrate loss at high frequencies. Therefore, reducing substrate loss is a common method to improve the Q factor of sensing devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a photoelectric sensor, thereby improving the photosensitivity of the photoelectric sensor.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device, comprising: a substrate including a shielding region and a protection region surrounding the shielding region; a shielding structure located on the substrate of the shielding region; and a bottom protection ring located on the substrate of the protection region and surrounding the shielding structure, wherein the bottom protection ring is used for grounding, and the shielding structure is electrically connected to the bottom protection ring. The bottom protection ring includes: a plurality of first conductive layers located on the substrate of the protection region, the plurality of first conductive layers extending along a first direction and arranged parallel to each other along a second direction, the plurality of first conductive layers forming a shape surrounding the shielding region, the first direction being perpendicular to the second direction; and a plurality of second conductive layers located on the substrate of the protection region, the plurality of second conductive layers extending along the second direction and arranged parallel to each other along the first direction, the plurality of second conductive layers forming a shape surrounding the shielding region, each second conductive layer penetrating the plurality of first conductive layers in its region along the second direction and being electrically connected to the plurality of first conductive layers.

[0006] This invention also provides a method for forming a semiconductor device, comprising: providing a substrate including a shielding region and a protection region surrounding the shielding region; forming a shielding structure on the substrate of the shielding region; and forming a bottom protection ring surrounding the shielding region on the substrate of the protection region. The step of forming the bottom protection ring includes: forming a plurality of crisscrossing first conductive layers and second conductive layers on the substrate of the protection region, wherein the plurality of first conductive layers extend along a first direction and are arranged parallel to each other along a second direction, and the plurality of first conductive layers form a shape surrounding the shielding region; and a plurality of second conductive layers extend along the second direction and are arranged parallel to each other along the first direction, and the plurality of second conductive layers form a shape surrounding the shielding region. Each second conductive layer penetrates the plurality of first conductive layers in its region along the second direction and is electrically connected to the plurality of first conductive layers, wherein the bottom protection ring is used for grounding, and the shielding structure is electrically connected to the bottom protection ring.

[0007] This invention also provides a semiconductor structure, including: a sensing device; and a semiconductor device provided in this invention, wherein the semiconductor device is located below the sensing device.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor device provided by the embodiments of the present invention, each second conductive layer penetrates through multiple first conductive layers in its region along a second direction and is electrically connected to multiple first conductive layers. Multiple first conductive layers and second conductive layers constitute a bottom protection ring. In the embodiments of the present invention, the bottom protection ring is formed by using the first conductive layer and the second conductive layer of the same layer, which can form a closed-loop bottom protection ring to improve the protection capability of the shielded area, which is beneficial to suppressing signal leakage, thereby reducing the probability of signal loss of the device surrounded by the bottom protection ring, and thus improving the performance of the device. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a semiconductor device;

[0011] Figures 2 to 4 This is a schematic diagram of the structure of another semiconductor device;

[0012] Figures 5 to 7 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0013] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor device formation method of the present invention;

[0014] Figure 15 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0015] Figure 16 This is a performance diagram of the sensing device when the semiconductor structure of this invention is in operation. Detailed Implementation

[0016] As can be seen from the background technology, devices surrounded by guard rings currently suffer from significant signal loss, making it difficult to improve device performance.

[0017] We will now analyze the reasons why it is currently difficult to improve the performance of two semiconductor devices.

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device.

[0019] refer to Figure 1 The semiconductor device includes: a substrate including a shielding region 40b and a protective zone 40a surrounding the shielding region 40b; a shielding structure located on the substrate of the shielding region 40b; and a protective ring 40 located on the substrate of the protective zone 40a, the protective ring 40 being electrically connected to the shielding structure and grounded.

[0020] In integrated circuits, such as CMOS radio frequency integrated circuits, sensing devices are crucial electrical components whose performance parameters directly impact the overall performance of the integrated circuit. Most sensing devices in integrated circuits are planar inductors, such as planar spiral inductors. Compared to traditional wire-wound inductors, planar inductors offer advantages such as lower cost, easier integration, lower noise, and lower power consumption. Furthermore, planar inductors have high compatibility with existing integrated circuit manufacturing processes.

[0021] A key indicator for evaluating the performance of sensing devices is the quality factor; a higher quality factor indicates better performance. One significant factor affecting the quality factor is signal loss. One method to reduce signal loss is to surround the shielding structure with a grounded protective ring 40, thereby suppressing signal leakage and reducing signal loss from the sensing device.

[0022] In semiconductor devices, the guard ring 40 is the shape surrounding the shielding region 40b. The shape of the guard ring 40 is typically an octagon or circle, capable of forming a surrounding pattern. However, with the continuous reduction in integrated circuit feature sizes, due to exposure limitations and design guidelines, it is difficult to form metal lines of arbitrary shapes (e.g., octagonal or circular). Figure 1 The continuous metal lines forming a protective ring 40 around the center are no longer suitable for the current process technology where the feature size of integrated circuits continues to shrink.

[0023] Reference Figures 2 to 4 This is a schematic diagram of the structure of another semiconductor device, in which... Figure 2 This is a top view of another semiconductor device. Figure 3 yes Figure 2 A magnified view of a portion of region A in the middle. Figure 4 yes Figure 3 (a) Sectional view along the CC direction.

[0024] Reference Figures 2 to 4 The semiconductor device includes: a substrate 10, including a shielding region 10b and a protective zone 10a surrounding the shielding region 10b; a shielding structure 30 located on the substrate 10 of the shielding region 10b; and a plurality of first metal lines 21 located on the substrate 10 of the protective zone 10a, the plurality of first metal lines 21 being arranged along a first direction (e.g., Figure 3 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 3 As shown in the Y direction, multiple first metal wires 21 are arranged in parallel to form a shape surrounding the shielding area 10b, with the first direction perpendicular to the second direction; multiple second metal wires 22 are located on the first metal wires 21, and multiple second metal wires 22 extend along the second direction and are arranged in parallel along the first direction, forming a shape surrounding the shielding area 10b. Each second metal wire 22 crosses the multiple first metal wires 21 in its area along the second direction and is electrically connected to the multiple first metal wires 21. The multiple first metal wires 21 and second metal wires 22 form a protective ring 20, which is used for grounding. The shielding structure 30 is electrically connected to the protective ring 20.

[0025] For clarity of illustration, Figure 3 (a) is Figure 2 A magnified view of a portion of region A in the middle. Figure 3 (b) is Figure 3 (a) is a schematic diagram of the first metal line 21. Figure 3 (c) is Figure 3 (a) Schematic diagram of the second metal line 22.

[0026] The first metal lines 21 all extend along a first direction, and the second metal lines 22 all extend along a second direction, which can adapt to the current process technology where the feature size of integrated circuits continues to shrink. However, research has found that, as Figure 4 As shown, the protective ring 20 is composed of a first metal line 21 and a second metal line 22 in an upper and lower layer structure. In the same layer, neither the first metal line 21 nor the second metal line 22 forms a closed structure. Therefore, the protection capability of the shielding area in each layer is insufficient, making it difficult to suppress signal leakage. This can easily lead to signal loss of the device surrounded by the protective ring 20, affecting the performance of the device. In particular, for sensing devices, it is difficult to improve the quality factor of the device.

[0027] To address the technical problem, embodiments of the present invention provide a semiconductor device, comprising: a substrate including a shielding region and a protection region surrounding the shielding region; a shielding structure located on the substrate of the shielding region; and a bottom protection ring located on the substrate of the protection region and surrounding the shielding structure, the bottom protection ring being grounded, the shielding structure being electrically connected to the bottom protection ring, the bottom protection ring comprising: a plurality of first conductive layers located on the substrate of the protection region, the plurality of first conductive layers extending along a first direction and arranged in parallel along a second direction, the plurality of first conductive layers forming a shape surrounding the shielding region, the first direction being perpendicular to the second direction; and a plurality of second conductive layers located on the substrate of the protection region, the plurality of second conductive layers extending along a second direction and arranged in parallel along the first direction, the plurality of second conductive layers forming a shape surrounding the shielding region, each second conductive layer penetrating the plurality of first conductive layers in its region along the second direction and being electrically connected to the plurality of first conductive layers.

[0028] In the semiconductor device provided by the embodiments of the present invention, a bottom protection ring is formed by using a first conductive layer and a second conductive layer of the same layer. This can form a closed-loop bottom protection ring, thereby improving the protection capability of the shielded area, which is beneficial to suppressing signal leakage. This helps to reduce the probability of signal loss of the device surrounded by the bottom protection ring, and thus helps to improve the performance of the device.

[0029] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] refer to Figures 5 to 7 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0031] Reference Figures 5 to 7 , Figure 5 This is a top view of a semiconductor device. Figure 6 for Figure 5 A magnified view of a portion of region B. Figure 7 (a) is Figure 6 Cross-sectional view along the DD direction. Figure 7 (b) is Figure 6 A cross-sectional view along the EE direction shows a semiconductor device comprising: a substrate 100 including a shielding region 100b and a protective region 100a surrounding the shielding region 100b; a shielding structure 300 located on the substrate 100 of the shielding region 100b; and a bottom protective ring 200 located on the substrate 100 of the protective region 100a and surrounding the shielding structure 300. The bottom protective ring 200 is used for grounding, and the shielding structure 300 is electrically connected to the bottom protective ring 200. The bottom protective ring 200 includes: a plurality of first conductive layers 210 located on the substrate 100 of the protective region 100a, the plurality of first conductive layers 210 being aligned along a first direction (e.g., ...). Figure 6 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 6As shown in the Y direction, multiple first conductive layers 210 are arranged in parallel to form a shape surrounding the shielding area 100b, with the first direction perpendicular to the second direction; multiple second conductive layers 220 are located on the base 100 of the protection area 100a, with the multiple second conductive layers 220 extending along the second direction and arranged in parallel along the first direction, forming a shape surrounding the shielding area 100b, with each second conductive layer 220 penetrating through the multiple first conductive layers 210 in its area along the second direction and electrically connected to the multiple first conductive layers 210.

[0032] In integrated circuits, such as CMOS radio frequency integrated circuits, sensors are crucial electrical components whose performance parameters directly impact the overall performance of the integrated circuit. Semiconductor devices are typically formed beneath the sensors in integrated circuits to isolate them from the substrate and reduce substrate losses.

[0033] The substrate 100 provides the basis for the process operation of semiconductor device formation. The substrate 100 of the shielding region 100b provides the basis for the process operation of shielding structure formation, and the substrate 100 of the protection region 100a provides the basis for the process operation of bottom protection ring (GR).

[0034] In this embodiment, the substrate 100 includes a substrate 160, discrete channel protrusions 110 located on the substrate 160, and a gate structure 130 that spans the channel protrusions 110 and covers a portion of the top and a portion of the sidewalls of the channel protrusions 110. Active and drain doped layers 120 are also formed in the channel protrusions 110 on both sides of the gate structure 130. The channel protrusions 110 extend along a second direction and are arranged in parallel along a first direction. The gate structure 130 extends along the first direction and is arranged in parallel along the second direction.

[0035] In the actual process of forming semiconductor devices, semiconductor devices are usually integrated with CMOS transistors on the same wafer. Therefore, semiconductor devices and CMOS transistors are formed in the same manufacturing process. At the same time, the substrate of the semiconductor device adopts the same structure as the CMOS transistor, which helps to improve the flatness of the entire wafer.

[0036] In this embodiment, substrate 160 is a silicon substrate. In other embodiments, the substrate may also be a substrate made of other materials such as germanium substrate, silicon germanide substrate, silicon carbide substrate, gallium arsenide substrate, or indium gallium dihydrogen phosphate substrate. The substrate material may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0037] In this embodiment, a fin field-effect transistor is introduced into the CMOS transistor manufacturing process. The channel bump 110 is a fin used to provide the channel of the fin field-effect transistor, and the gate structure 130 is used to control the conduction and cutoff of the fin field-effect transistor channel. Accordingly, the channel bump 110 and the gate structure 130 of the semiconductor device can be formed simultaneously during the process of forming the fin field-effect transistor. In other embodiments, a fully all-around (GAA) transistor can also be introduced, and the corresponding channel bump can also be one or more channel layers spaced apart in the longitudinal direction.

[0038] In this embodiment, the material of the channel protrusion 110 is the same as the material of the substrate 160, and the material of the channel protrusion 110 is silicon.

[0039] The type of gate structure 130 depends on the actual requirements of the fin field-effect transistor. In actual manufacturing processes, fin field-effect transistors use high-k gate dielectric material instead of traditional silicon dioxide gate dielectric material and use metal as the gate electrode. Therefore, in this embodiment, the gate structure 130 of the semiconductor device is a metal gate structure. In other embodiments, the gate structure of the semiconductor device can also be a polysilicon gate structure.

[0040] In this embodiment, the source / drain doped layer 120 of the semiconductor device is formed during the formation of the fin field-effect transistor. Therefore, the doping type of the source / drain doped layer 120 can be N-type or P-type.

[0041] In this embodiment, the channel protrusion 110 extends along the second direction and is arranged in parallel along the first direction, and the gate structure 130 extends along the first direction and is arranged in parallel along the second direction. Accordingly, the first conductive layer 210 extends along the first direction and is arranged in parallel along the second direction according to the direction of the gate structure 130, and the second conductive layer 220 extends along the second direction and is arranged in parallel along the first direction according to the direction of the channel protrusion 110.

[0042] In this embodiment, the semiconductor device further includes a dielectric layer 140 covering the substrate 100. The dielectric layer 140 serves to isolate adjacent devices and also provides a process basis for the formation of the first conductive layer 210 and the second conductive layer 220. In this embodiment, the material of the dielectric layer 140 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0043] In integrated circuits, a key indicator for evaluating the performance of sensing devices is the quality factor (Q). A higher quality factor indicates better performance. One important factor affecting the quality factor of a sensing device is substrate loss at high frequencies.

[0044] In this embodiment, the semiconductor device is disposed below the sensing device (e.g., an inductor), and the shielding structure 300 is used to shield the electric field lines and induced magnetic field lines of the sensing device, so that most of the electric field lines and induced magnetic field lines generated by the sensing device terminate at the shielding structure 300 and do not enter the substrate 160, thereby reducing the loss of the substrate 160 and correspondingly improving the quality factor of the sensing device. Specifically, the shielding structure 300 is a patterned ground shield (PGS) structure.

[0045] In this embodiment, the noise current generated in the shielding structure 300 is grounded by grounding the shielding structure 300.

[0046] In this embodiment, the shielding structure 300 includes multiple shielding layers. By employing multiple shielding layers, the coupling capacitance and coupling inductance between the shielding layers and the substrate 100 are effectively reduced. Adjacent shielding layers are electrically connected to each other, and the shielding layers are grounded. Therefore, when the sensing device is operating, the noise current generated by the upper shielding layer can be transmitted to the lower shielding layer and ultimately to ground, thereby suppressing the generation of crosstalk noise. In this embodiment, the material of the shielding structure 300 is a conductive material, including Cu, W, or Al.

[0047] The first conductive layer 210 is used to form the bottom protective ring 200, and the first conductive layer 210 is used to form the shape of the bottom protective ring 200 by arrangement.

[0048] In this embodiment, the first conductive layer 210 includes a source / drain plug layer located on top of the source / drain doped layer 120 and spanning multiple channel protrusions 110. The source / drain plug layer covers a portion of the top of the source / drain doped layer 120.

[0049] In this embodiment, by using the source / drain plug layer as the first conductive layer 210, the first conductive layer 210 can be formed during the formation of the fin field-effect transistor using the process of forming the source / drain plug layer, thereby reducing modifications to existing processes and improving the process efficiency of forming the first conductive layer 210.

[0050] In this embodiment, the first conductive layer 210 is located in the dielectric layer 140 on top of the substrate 100. Specifically, the first conductive layer 210 is located in the dielectric layer 140 on top of the source / drain doped layer 120.

[0051] In this embodiment, multiple first conductive layers 210 form an octagonal ring surrounding the shielding area 100b.

[0052] In this embodiment, the first conductive layer 210 is used to form the shape of the bottom protective ring 200 by arrangement. Accordingly, the bottom protective ring 200 is octagonal, which helps to make the signal suppression effect of the bottom protective ring 200 more uniform. Furthermore, the bottom protective ring 200 surrounds the shielding structure 300, and the shielding structure 300 is also octagonal, which helps to make the shielding structure 300 uniformly shield the electric field lines and induced magnetic field lines of the sensing device.

[0053] In other embodiments, the shape of the plurality of first conductive layers forming the surrounding shielding area can also be triangular, square, or circular.

[0054] In this embodiment, the material of the first conductive layer 210 is a conductive material, which can be Cu, W or Al.

[0055] The second conductive layer 220 is used to penetrate the first conductive layer 210 in the area, electrically connecting all the first conductive layers 210 in the area. At the same time, it is also used to form a bottom protective ring 200 together with the first conductive layer 210.

[0056] In this embodiment, the first conductive layer 210 and the second conductive layer 220 of the same layer are used to form a bottom protection ring 200, which can form a closed-loop bottom protection ring 200 to improve the protection capability of the shielding area 100b, which is beneficial to suppressing signal leakage, thereby reducing the probability of signal loss of the device surrounded by the bottom protection ring 200, and thus improving the performance of the device.

[0057] In this embodiment, the second conductive layer 220 includes a gate plug layer, located on top of the gate structure 130 and spanning multiple gate structures 130, with the gate plug layer covering a portion of the top of the gate structure 130. In this embodiment, using the gate plug layer as the second conductive layer 220 allows the second conductive layer 220 to be formed during the formation of the fin field-effect transistor using the same process as forming the gate plug layer, thereby reducing modifications to existing processes and improving the process efficiency of forming the second conductive layer 220.

[0058] In this embodiment, the second conductive layer 220 is located in the dielectric layer 140 on top of the substrate 100. Specifically, the second conductive layer 220 is located in the dielectric layer 140 on top of the gate structure 130. In this embodiment, the material of the second conductive layer 220 is a conductive material, which can be Cu, W, or Al.

[0059] It should be noted that the second conductive layer 220 and the first conductive layer 210 are electrically connected. In order to simplify the process steps of forming the first conductive layer 210 and the second conductive layer 220 and reduce the process cost, the first conductive layer 210 and the second conductive layer 220 are formed in the same process step; accordingly, the first conductive layer 210 and the second conductive layer 220 are an integral structure.

[0060] The bottom protective ring 200 surrounds and is electrically connected to the shielding structure 300, thereby grounding the noise current generated in the shielding structure 300. Specifically, in this embodiment, the bottom protective ring 200 is electrically connected to the shielding structure 300 via radial interconnects.

[0061] Accordingly, in this embodiment, the first conductive layer 210 and the second conductive layer 220 of the same layer form a bottom protection ring 200, which can form a closed-loop bottom protection ring 200, which is beneficial to suppressing signal leakage, thereby reducing the probability of signal loss of the sensing device and thus improving the Q value of the sensing device. At the same time, the bottom protection ring 200 formed by the first conductive layer 210 and the second conductive layer 220 of the same layer can also adapt to rules such as exposure limitations and design criteria, thereby adapting to the current process technology of continuously shrinking feature sizes of integrated circuits.

[0062] It should be noted that in this embodiment, the radial width d1 of the bottom protective ring 200 should not be too large or too small. If the radial width d1 of the bottom protective ring 200 is too large, the number of the first conductive layer 210 and the second conductive layer 220 used to form the bottom protective ring 200 will be too large, which will easily increase the complexity of the process of forming the bottom protective ring 200 and also easily cause unnecessary waste. If the radial width d1 of the bottom protective ring 200 is too small, the number of the first conductive layer 210 and the second conductive layer 220 used to form the bottom protective ring 200 will be too small, and their size will also be small, which will easily affect the electrical connection performance of the first conductive layer 210 and the second conductive layer 220, thereby affecting the protective function of the bottom protective ring 200 and its signal suppression function. Therefore, in this embodiment, the radial width d1 of the bottom protective ring 200 is 1 μm to 10 μm.

[0063] It should also be noted that in this embodiment, the inner diameter d2 of the bottom protective ring 200 should not be too large or too small. If the inner diameter d2 of the bottom protective ring 200 is too large, it will easily lead to an excessively large area occupied by the semiconductor device, resulting in unnecessary area waste; if the inner diameter d2 of the bottom protective ring 200 is too small, the area of ​​the shielding area 100b surrounded by the bottom protective ring 200 will be too small, which will easily cause process difficulties in the formation of the shielding structure 300, thereby affecting the formation of the semiconductor device. Therefore, in this embodiment, the inner diameter d2 of the bottom protective ring 200 is 10um to 300um.

[0064] In this embodiment, the bottom protective ring 200 has a plurality of equally spaced first openings 100c, which divide the bottom protective ring 200 into a plurality of mutually isolated units.

[0065] Correspondingly, the shielding structure 300 surrounded by the bottom protective ring 200 also has multiple equally spaced second openings, which divide the shielding structure 300 into multiple isolated units, wherein the second openings are connected to the first opening 100c.

[0066] By dividing the bottom protection ring 200 and the shielding structure 300 into multiple isolated units, it is beneficial to reduce the resistance of the bottom protection ring 200 and the shielding structure 300, thereby reducing the parasitic resistance of the bottom protection ring 200 and the shielding structure 300, and thus improving the Q value of the sensing device. Moreover, dividing the bottom protection ring 200 and the shielding structure 300 into multiple isolated units can also effectively suppress the formation of eddy currents in the bottom protection ring 200 and the shielding structure 300 caused by the magnetic field generated by the sensing device, thereby reducing the energy loss of the bottom protection ring 200 and the shielding structure 300 to the sensing device, and thus improving the Q value of the sensing device.

[0067] The more first openings 100c there are, the better the effect of improving the Q value of the sensing device. However, if there are too many first openings 100c, too many induced magnetic field lines will enter the substrate 160 through the first openings 100c, which will reduce the shielding effect of the shielding structure 300. Therefore, in this embodiment, the number of first openings 100c is two to eight.

[0068] Specifically, such as Figure 5 As shown, there are two first openings 100c, which are arranged radially opposite each other, dividing the bottom protective ring 200 into two symmetrical units. Setting the number of first openings 100c to two can also effectively reduce the energy loss of the sensing device by the bottom protective ring 200 and the shielding structure 300, thereby improving the Q value of the sensing device.

[0069] refer to Figure 7 The semiconductor device further includes: a top protection ring located on top of the bottom protection ring 200 and electrically connected to the bottom protection ring 200. The top protection ring includes: a plurality of first metal lines 410 formed on the bottom protection ring 200, the first metal lines 410 extending along a second direction and arranged in parallel along a first direction, the plurality of first metal lines 410 forming a shape surrounding the shielding area 100b; a plurality of second metal lines 420 formed on the first metal lines 410, the second metal lines 420 extending along a first direction and arranged in parallel along a second direction, the plurality of second metal lines 420 forming a shape surrounding the shielding area 100b, each second metal line 420 crossing the plurality of first metal lines 410 in its area along a first direction and electrically connected to the plurality of first metal lines 410.

[0070] In this embodiment, the first metal line 410 and the second metal line 420 form a top protective ring stacked on the bottom protective ring 200, which helps to enhance the protection capability of the bottom protective ring 200 for the shielding area 100b, further suppress signal leakage, thereby further reducing the proportion of signal leakage of the device surrounded by the bottom protective ring 200, and further improving the performance of the device.

[0071] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor device formation method of the present invention.

[0072] Reference Figure 8 and Figure 9 , Figure 8 Top view of the base Figure 9 for Figure 8 A cross-sectional view of region B in the middle provides a base 101, including a shielding region 101b and a protective zone 101a surrounding the shielding region 101b.

[0073] In integrated circuits, such as CMOS radio frequency integrated circuits, sensors are crucial electrical components whose performance parameters directly impact the overall performance of the integrated circuit. Semiconductor devices are typically formed beneath the sensors in integrated circuits to isolate them from the substrate and reduce substrate losses.

[0074] The substrate 101 provides the basis for the process operation of semiconductor device formation. The substrate 101 of the shielding region 101b provides the basis for the process operation of shielding structure formation, and the substrate 101 of the protection region 101a provides the basis for the process operation of bottom protection ring formation.

[0075] In this embodiment, the substrate 101 includes a substrate 161, discrete channel protrusions 111 located on the substrate 161, and a gate structure 131 spanning the channel protrusions 111 and covering a portion of the top and a portion of the sidewalls of the channel protrusions 111. Active and drain doped layers 121 are also formed in the channel protrusions 111 on both sides of the gate structure 131. The channel protrusions 111 extend along a second direction (e.g., ...). Figure 8 Extending along the Y-direction and along the first direction (as shown in the middle Y direction) Figure 8 The gate structure 131 is arranged in parallel along the first direction and parallel along the second direction (as shown in the X direction).

[0076] In the actual process of forming semiconductor devices, semiconductor devices are usually integrated with CMOS transistors on the same wafer. Therefore, semiconductor devices and CMOS transistors are formed in the same manufacturing process. At the same time, the substrate of the semiconductor device adopts the same structure as the CMOS transistor, which helps to improve the flatness of the entire wafer.

[0077] In this embodiment, substrate 161 is a silicon substrate. In other embodiments, the substrate may also be a substrate made of other materials such as germanium substrate, silicon germanide substrate, silicon carbide substrate, gallium arsenide substrate, or indium gallium dihydrogen phosphate substrate. The substrate material may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0078] In this embodiment, a fin field-effect transistor is introduced into the CMOS transistor manufacturing process. The channel bump 111 is a fin, used to provide the channel of the fin field-effect transistor, and the gate structure 131 is used to control the conduction and cutoff of the fin field-effect transistor channel. Accordingly, the channel bump 111 and the gate structure 131 of the semiconductor device can be formed simultaneously during the process of forming the fin field-effect transistor. In other embodiments, a fully enclosed transistor can also be introduced, and the corresponding channel bump can also be one or more channel layers spaced apart in the longitudinal direction.

[0079] In this embodiment, the material of the channel protrusion 111 is the same as the material of the substrate 161, and the material of the channel protrusion 111 is silicon.

[0080] The type of gate structure 131 depends on the actual requirements of the fin field-effect transistor. In actual manufacturing processes, fin field-effect transistors use high-k gate dielectric material instead of traditional silicon dioxide gate dielectric material and use metal as the gate electrode. Therefore, in this embodiment, the gate structure 131 of the semiconductor device is a metal gate structure. In other embodiments, the gate structure of the semiconductor device can also be a polysilicon gate structure.

[0081] In this embodiment, the source / drain doped layer 121 of the semiconductor device is formed during the formation of the fin field-effect transistor. Therefore, the doping type of the source / drain doped layer 121 can be N-type or P-type.

[0082] In this embodiment, the channel protrusion 111 extends along the second direction and is arranged in parallel along the first direction, and the gate structure 131 extends along the first direction and is arranged in parallel along the second direction. Accordingly, the first conductive layer 210 extends along the first direction and is arranged in parallel along the second direction according to the direction of the gate structure 131, and the second conductive layer 220 extends along the second direction and is arranged in parallel along the first direction according to the direction of the channel protrusion 111.

[0083] Reference Figures 9 to 13 A shielding structure 301 is formed on the substrate 101 of the shielding area 101b.

[0084] In integrated circuits, a key indicator for evaluating the performance of sensing devices is the quality factor; a higher quality factor indicates better performance. One important factor affecting the quality factor of sensing devices is substrate loss at high frequencies.

[0085] In this embodiment, the semiconductor device is disposed below the sensing device (e.g., an inductor). The shielding structure 301 is used to shield the electric field lines and induced magnetic field lines of the sensing device, so that most of the electric field lines and induced magnetic field lines generated by the sensing device terminate at the shielding structure 301 and do not enter the substrate 161, thereby reducing the loss of the substrate 161 and correspondingly improving the quality factor of the sensing device. Specifically, the shielding structure 301 is a patterned grounded shielding structure.

[0086] In this embodiment, the noise current generated in the shielding structure 301 is grounded by grounding the shielding structure 301.

[0087] In this embodiment, the shielding structure 301 includes multiple shielding layers. By employing multiple shielding layers, the coupling capacitance and coupling inductance between the shielding layers and the substrate 100 are effectively reduced. Adjacent shielding layers are electrically connected to each other, and the shielding layers are grounded. Therefore, when the sensing device is operating, the noise current generated by the upper shielding layer can be transmitted to the lower shielding layer and ultimately to ground, thereby suppressing noise crosstalk. In this embodiment, the material of the shielding structure 301 is a conductive material, including Cu, W, or Al.

[0088] Continue to refer to Figures 9 to 13The step of forming a bottom protective ring 201 surrounding the shielding area 100b on the base 101 of the protected area 101a includes: forming a plurality of crisscrossing first conductive layers 211 and second conductive layers 221 on the base 101 of the protected area 101a. The plurality of first conductive layers 211 extend along a first direction and are arranged in parallel along a second direction, forming a shape surrounding the shielding area 100b. The plurality of second conductive layers 221 extend along a second direction and are arranged in parallel along a first direction, forming a shape surrounding the shielding area 100b. Each second conductive layer 221 penetrates the plurality of first conductive layers 211 in its area along the second direction and is electrically connected to the plurality of first conductive layers 211. The bottom protective ring 201 is used for grounding, and the shielding structure 301 is electrically connected to the bottom protective ring 201.

[0089] In this embodiment, a bottom protection ring 201 is formed by the first conductive layer 211 and the second conductive layer 221 on the same layer. This closed-loop bottom protection ring 201 enhances the protection capability of the shielding area 101b, helps suppress signal leakage, and thus reduces the probability of signal loss in the device surrounded by the bottom protection ring 201, thereby improving device performance. Furthermore, the bottom protection ring 201 formed by the first conductive layer 211 and the second conductive layer 221 on the same layer can also adapt to rules such as exposure limitations and design guidelines, thus accommodating the current process technology where integrated circuit feature sizes are continuously decreasing.

[0090] Specifically, this embodiment helps to reduce the probability of signal loss in the sensing device, thereby helping to improve the Q value of the sensing device.

[0091] Reference Figures 11 to 13 , Figure 11 This is a top view of a semiconductor device. Figure 12 for Figure 11 A magnified view of a portion of region B. Figure 13 (a) is Figure 12 Cross-sectional view along the DD direction. Figure 13 (b) is Figure 12 In a cross-sectional view along the EE direction, in this embodiment, the first conductive layer 211 includes a source / drain plug layer located on top of the source / drain doped layer 121 and spanning multiple channel protrusions 111. The source / drain plug layer 121 covers a portion of the top of the source / drain doped layer 121.

[0092] The first conductive layer 211 is used to form the bottom protective ring 201, and the first conductive layer 211 is used to form the shape of the bottom protective ring 201 by arrangement.

[0093] In this embodiment, by using the source / drain plug layer as the first conductive layer 211, the source / drain plug layer can be formed during the formation of the fin field-effect transistor, thereby reducing modifications to existing processes and improving the process efficiency of forming the first conductive layer 211.

[0094] In this embodiment, multiple first conductive layers 211 form an octagonal ring surrounding the shielding region 101b.

[0095] In this embodiment, the first conductive layer 211 is arranged to form the shape of the bottom protective ring 201, and the bottom protective ring 201 is octagonal, which helps to make the signal suppression effect of the bottom protective ring 201 more uniform. Furthermore, the bottom protective ring 201 surrounds the shielding structure 301, and the shielding structure 301 is also octagonal, which helps to make the shielding structure 301 uniformly shield the electric field lines and induced magnetic field lines of the sensing device.

[0096] In other embodiments, the shape of the plurality of first conductive layers forming the surrounding shielding area can also be triangular, square, or circular.

[0097] In this embodiment, the material of the first conductive layer 211 is a conductive material, which can be Cu, W or Al.

[0098] Continue to refer to Figures 11 to 13 In this embodiment, the second conductive layer 221 includes a gate plug layer, which is located on top of the gate structure 130 and spans multiple gate structures 130. The gate plug layer covers part of the top of the gate structure 130.

[0099] The second conductive layer 221 is used to penetrate the first conductive layer 211 in the area, electrically connecting all the first conductive layers 211 in the area. At the same time, it is also used to form a bottom protective ring 201 together with the first conductive layer 211.

[0100] In this embodiment, by using the gate plug layer as the second conductive layer 221, the gate plug layer can be formed during the formation of the fin field-effect transistor, thereby reducing modifications to existing processes and improving the process efficiency of forming the second conductive layer 221.

[0101] In this embodiment, the material of the second conductive layer 221 is a conductive material, which can be Cu, W or Al.

[0102] The bottom protective ring 201 surrounds the shielding structure 301 and is electrically connected to the shielding structure 301, thereby grounding the noise current generated in the shielding structure 301.

[0103] Specifically, in this embodiment, the bottom protective ring 201 is electrically connected to the shielding structure 301 via radial interconnects.

[0104] It should be noted that in this embodiment, the radial width d1 of the bottom protective ring 201 should not be too large or too small. If the radial width d1 of the bottom protective ring 201 is too large, the number of first conductive layers 211 and second conductive layers 221 used to form the bottom protective ring 201 will be too large, which will easily increase the complexity of the process of forming the bottom protective ring 201 and also easily cause unnecessary waste. If the radial width d1 of the bottom protective ring 201 is too small, the number of first conductive layers 211 and second conductive layers 221 used to form the bottom protective ring 201 will be too small, and their size will also be small, which will easily affect the electrical connection performance of the first conductive layers 211 and second conductive layers 221, thereby affecting the protective function of the bottom protective ring 201 and its signal suppression function. Therefore, in this embodiment, the radial width d1 of the bottom protective ring 201 is 1 μm to 10 μm.

[0105] It should also be noted that in this embodiment, the inner diameter d2 of the bottom protective ring 201 should not be too large or too small. If the inner diameter d2 of the bottom protective ring 201 is too large, it will easily lead to an excessively large area occupied by the semiconductor device, resulting in unnecessary area waste; if the inner diameter d2 of the bottom protective ring 201 is too small, the area of ​​the shielding area 101b surrounded by the bottom protective ring 201 will be too small, which will easily cause process difficulties in the formation of the shielding structure 301, thereby affecting the formation of the semiconductor device. Therefore, in this embodiment, the inner diameter d2 of the bottom protective ring 201 is 10um to 300um.

[0106] In this embodiment, the bottom protective ring 201 has a plurality of equally spaced first openings 101c, which divide the bottom protective ring 201 into a plurality of mutually isolated units.

[0107] Correspondingly, the shielding structure 301 surrounded by the bottom protective ring 201 also has multiple equally spaced second openings, which divide the shielding structure 301 into multiple isolated units, wherein the second openings are connected to the first opening 101c.

[0108] By dividing the bottom protection ring 201 and the shielding structure 301 into multiple isolated units, it is beneficial to reduce the resistance of the bottom protection ring 201 and the shielding structure 301, thereby reducing the parasitic resistance of the bottom protection ring 201 and the shielding structure 301, and thus improving the Q value of the sensing device. Moreover, dividing the bottom protection ring 201 and the shielding structure 301 into multiple isolated units can also effectively suppress the formation of eddy currents in the bottom protection ring 201 and the shielding structure 301 caused by the magnetic field generated by the sensing device, thereby reducing the energy loss of the bottom protection ring 201 and the shielding structure 301 to the sensing device, and thus improving the Q value of the sensing device.

[0109] The more first openings 101c there are, the better the Q value of the sensing device will be improved. However, if there are too many first openings 101c, too many induced magnetic field lines will enter the substrate 160 through the first openings 101c, which will reduce the shielding effect of the shielding structure 301. Therefore, in this embodiment, the number of first openings 101c is two to eight.

[0110] Specifically, such as Figure 11 As shown, there are two first openings 101c, which are arranged radially opposite each other, dividing the bottom protective ring 201 into two symmetrical units. Setting the number of first openings 101c to two can also effectively reduce the energy loss of the sensing device by the bottom protective ring 201 and the shielding structure 301, thereby improving the Q value of the sensing device.

[0111] Specifically, refer to Figure 9 The step of forming a plurality of interlaced first conductive layers 211 and second conductive layers 221 on the substrate 101 of the protected area 101a includes: forming a dielectric layer 141 covering the substrate 101.

[0112] The dielectric layer 141 serves to isolate adjacent devices and also provides a process basis for the formation of the first conductive layer 211 and the second conductive layer 221.

[0113] In this embodiment, the material of the dielectric layer 141 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0114] refer to Figure 10 Multiple first trenches 212 are formed in the medium layer 141 of the protected area 101a. The multiple first trenches 212 extend along the first direction and are arranged in parallel along the second direction. The multiple first trenches 212 form a shape surrounding the shielding area 101b.

[0115] The first trench 212 is used to provide space for the formation of the first conductive layer 211.

[0116] Specifically, the first trench 212 exposes a portion of the top of the source / drain doped layer 121.

[0117] In this embodiment, the first trench 212 is formed using a dry etching process.

[0118] Dry etching is anisotropic, so by selecting dry etching, the etching becomes more directional, which is beneficial to improving the opening size accuracy of the first trench 212.

[0119] Continue to refer to Figure 10 Multiple second trenches 222 are formed in the medium layer 141 of the protected area 101a. The multiple second trenches 222 extend along the second direction and are arranged in parallel along the first direction. The multiple second trenches 222 form a shape surrounding the shielding area 101b. Each second trench 222 penetrates multiple first trenches 212 in the area along the second direction and is connected to multiple first trenches 212.

[0120] The second trench 222 is used to provide space for the formation of the second conductive layer 221.

[0121] Specifically, the second trench 222 exposes part of the top of the gate structure 131.

[0122] In this embodiment, the second trench 222 is formed using a dry etching process.

[0123] Dry etching is anisotropic, so by selecting dry etching, the etching becomes more directional, which is beneficial to improving the opening size accuracy of the second trench 222.

[0124] refer to Figure 13 The first trench 212 is filled to form a first conductive layer 211 located in the first trench 212; the second trench 222 is filled to form a second conductive layer 221 located in the second trench 222.

[0125] In this embodiment, the first conductive layer 211 is located in the dielectric layer 141 on top of the substrate 101. Specifically, the first conductive layer 211 is located in the dielectric layer 141 on top of the source / drain doped layer 121. The second conductive layer 221 is located in the dielectric layer 141 on top of the substrate 101. Specifically, the second conductive layer 221 is located in the dielectric layer 141 on top of the gate structure 130.

[0126] In this embodiment, the first groove 212 and the second groove 222 are filled in the same step.

[0127] In the same step, the first trench 212 and the second trench 222 are filled, which simplifies the process steps of forming the first conductive layer 211 and the second conductive layer 221 and reduces the process cost. Accordingly, the first conductive layer 211 and the second conductive layer 221 are an integral structure.

[0128] refer to Figure 14 After forming the bottom protection ring 200, the method further includes: forming a top protection ring on the bottom protection ring 201, the top protection ring being electrically connected to the bottom protection ring 201, the top protection ring including: a plurality of first metal wires 411 formed on the bottom protection ring 200, the first metal wires 411 extending along a second direction and arranged parallel to the first direction, the plurality of first metal wires 411 forming a shape surrounding the shielding area 101b; a plurality of second metal wires 421 formed on the first metal wires 411, the second metal wires 421 extending along a first direction and arranged parallel to the second direction, the plurality of second metal wires 421 forming a shape surrounding the shielding area 101b, each second metal wire 421 crossing the plurality of first metal wires 411 in its area along the first direction and being electrically connected to the plurality of first metal wires 411.

[0129] In this embodiment, the first metal line 411 and the second metal line 421 form a top protective ring stacked on the bottom protective ring 201, which helps to enhance the protection capability of the bottom protective ring 201 for the shielding area 101b, further suppress signal leakage, thereby further reducing the proportion of signal leakage of the device surrounded by the bottom protective ring 201, and further improving the performance of the device.

[0130] Specifically, a back-end process is used to form a first metal line 411 and a second metal line 421. The first metal line 411 is the first layer metal line (M1) in the back-end process, and the second metal line 421 is the second layer metal line (M2) in the back-end process.

[0131] Figure 15 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 16 This is a performance diagram of the sensing device when the semiconductor structure of this invention is in operation.

[0132] refer to Figure 15 The semiconductor structure includes: a sensing device 500; and a semiconductor device provided in this embodiment of the invention, wherein the semiconductor device is located below the sensing device 500.

[0133] In integrated circuits, such as CMOS radio frequency integrated circuits, the sensor 500 is an important electrical component. Its performance parameters directly affect the performance of the integrated circuit. An important indicator for measuring the performance of the sensor 500 is the quality factor (Q). The higher the Q factor, the better the performance of the sensor 500. One important factor affecting the Q factor of the sensor 500 is substrate loss at high frequencies. Semiconductor devices are typically formed beneath the sensor 500 in integrated circuits to isolate the sensor 500 from the substrate and reduce substrate loss.

[0134] In this embodiment, the first conductive layer and the second conductive layer of the same layer are used to form a bottom protection ring 200, which can form a closed loop bottom protection ring 200 to improve the protection capability of the shielding area 100b, which is beneficial to suppressing signal leakage, thereby reducing the probability of signal loss of the device surrounded by the bottom protection ring 200, and thus improving the performance of the device.

[0135] Specifically, the bottom protection ring 200 is formed by using the first conductive layer and the second conductive layer of the same layer. The bottom protection ring 200 can form a closed loop, which is beneficial to suppressing signal leakage, thereby reducing the probability of signal loss of the sensing device 500, and thus improving the Q value of the sensing device 500.

[0136] like Figure 16 As shown, the horizontal axis represents frequency and the vertical axis represents Q value. Curve 1 shows the Q value curve of the sensing device at different frequencies in a semiconductor structure using a conventional guard ring, and curve 2 shows the Q value curve of the sensing device at different frequencies in a semiconductor structure using the bottom guard ring 200 in this embodiment of the invention. In the semiconductor structure using the bottom guard ring 200 in this embodiment of the invention, the Q value of the sensing device is significantly improved.

[0137] In this embodiment, the semiconductor device is disposed below the sensing device 500 (e.g., an inductor), and the shielding structure 300 is used to shield the electric field lines and induced magnetic field lines of the sensing device, so that most of the electric field lines and induced magnetic field lines generated by the sensing device 500 terminate at the shielding structure 300 and do not enter the substrate, thereby reducing substrate loss and correspondingly improving the Q value of the sensing device 500.

[0138] In this embodiment, the sensing device 500 is a passive radio frequency device.

[0139] Radio frequency passive devices are typically in a high-frequency state during operation. Therefore, the semiconductor structure of this embodiment is effective in improving the Q value of radio frequency passive devices.

[0140] In this embodiment, the sensing device 500 includes an input terminal, a metal body layer, and an output terminal. The metal body layer extends from the input terminal in a spiral ring shape to the output terminal. The projection of the metal body layer on the substrate surface is in the shielding area 100b of the substrate.

[0141] Specifically, in this embodiment, the sensing device 500 is an inductor. Specifically, the sensing device 500 is a planar differential inductor, and the number of spiral loops extending from the metal body layer is at least one. In other embodiments, the sensing device may also be other electronic devices capable of generating a magnetic field and forming eddy currents within the substrate, such as a planar spiral inductor, a transformer, or a balun.

[0142] The projection of the metal layer on the substrate surface is in the shielding area 100b of the substrate, thereby achieving the shielding effect of the shielding structure 300 on the electric field lines and induced magnetic field lines in the metal layer.

[0143] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a shielding area and a protective area surrounding the shielding area; A shielding structure is located on the base of the shielding area; A bottom protective ring, located on the base of the protected area and surrounding the shielding structure, is used for grounding. The shielding structure is electrically connected to the bottom protective ring. The bottom protective ring includes: Multiple first conductive layers are located on the base of the protected area. The multiple first conductive layers extend along a first direction and are arranged in parallel along a second direction. The multiple first conductive layers form a shape surrounding the shielding area. The first direction is perpendicular to the second direction. Multiple second conductive layers are located on the base of the protected area. The multiple second conductive layers extend along the second direction and are arranged in parallel along the first direction. The multiple second conductive layers form a shape surrounding the shielding area. Each second conductive layer penetrates the multiple first conductive layers in its area along the second direction and is electrically connected to the multiple first conductive layers.

2. The semiconductor device as claimed in claim 1, characterized in that, The substrate includes a substrate, discrete channel protrusions on the substrate, and a gate structure that spans the channel protrusions and covers a portion of the top and a portion of the sidewalls of the channel protrusions. Active and drain doped layers are also formed in the channel protrusions on both sides of the gate structure. The channel protrusions extend along the second direction and are arranged in parallel along the first direction. The gate structure extends along the first direction and is arranged in parallel along the second direction. The first conductive layer includes a source / drain plug layer located on top of the source / drain doped layer and spanning the plurality of channel protrusions, the source / drain plug layer covering a portion of the top of the source / drain doped layer; The second conductive layer includes a gate plug layer located on top of the gate structure and spanning multiple gate structures, the gate plug layer covering a portion of the top of the gate structure.

3. The semiconductor device as described in claim 1 or 2, characterized in that, The semiconductor device further includes: a dielectric layer covering the substrate; Both the first conductive layer and the second conductive layer are located in the dielectric layer on top of the substrate.

4. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes: a top protective ring, located on top of the bottom protective ring and electrically connected to the bottom protective ring, the top protective ring comprising: Multiple first metal wires are located on the bottom protective ring. The first metal wires extend along a second direction and are arranged in parallel along a first direction. The multiple first metal wires form a shape that surrounds the shielding area. A plurality of second metal wires are located on the first metal wire, the second metal wires extend along a first direction and are arranged in parallel along a second direction, the plurality of second metal wires form a shape surrounding the shielding area, each second metal wire crosses the plurality of first metal wires in the area along the first direction and is electrically connected to the plurality of first metal wires.

5. The semiconductor device as claimed in claim 1, characterized in that, The bottom protective ring has a radial width of 1 μm to 10 μm.

6. The semiconductor device as claimed in claim 1, characterized in that, The inner diameter of the bottom protective ring is between 10µm and 300µm.

7. The semiconductor device as claimed in claim 1, characterized in that, Multiple first conductive layers form an octagonal, triangular, square, or circular shape surrounding the shielding area.

8. The semiconductor device as claimed in claim 1, characterized in that, The bottom protective ring has multiple equally spaced first openings, which divide the bottom protective ring into multiple isolated units.

9. The semiconductor device as claimed in claim 1, characterized in that, The shielding structure has multiple equally spaced second openings, which divide the shielding structure into multiple isolated units.

10. The semiconductor device as claimed in claim 8, characterized in that, The number of the first opening is two to eight.

11. The semiconductor device as claimed in claim 1, characterized in that, The first conductive layer and the second conductive layer are an integral structure.

12. A method for forming a semiconductor device, characterized in that, include: Provide a substrate, including a shielding area and a protective area surrounding the shielding area; A shielding structure is formed on the substrate of the shielding area; A bottom protective ring is formed on the base of the protected area, surrounding the shielded area. The step of forming the bottom protective ring includes: forming a plurality of crisscrossing first conductive layers and second conductive layers on the base of the protected area. The plurality of first conductive layers extend along a first direction and are arranged parallel to each other along a second direction, forming a shape surrounding the shielded area. The plurality of second conductive layers extend along the second direction and are arranged parallel to each other along the first direction, forming a shape surrounding the shielded area. Each second conductive layer penetrates the plurality of first conductive layers in its area along the second direction and is electrically connected to the plurality of first conductive layers. The bottom protective ring is used for grounding, and the shielding structure is electrically connected to the bottom protective ring.

13. The method for forming a semiconductor device as described in claim 12, characterized in that, The substrate includes a substrate, discrete channel protrusions on the substrate, and a gate structure that spans the channel protrusions and covers a portion of the top and a portion of the sidewalls of the channel protrusions. Active and drain doped layers are also formed in the channel protrusions on both sides of the gate structure. The channel protrusions extend along the second direction and are arranged in parallel along the first direction. The gate structure extends along the first direction and is arranged in parallel along the second direction. The first conductive layer includes a source / drain plug layer located on top of the source / drain doped layer and spanning the plurality of channel protrusions, the source / drain plug layer covering a portion of the top of the source / drain doped layer; The second conductive layer includes a gate plug layer located on top of the gate structure and spanning multiple gate structures, the gate plug layer covering a portion of the top of the gate structure.

14. The method for forming a semiconductor device as described in claim 12 or 13, characterized in that, The step of forming a plurality of crisscrossing first and second conductive layers on the substrate of the protected area includes: forming a dielectric layer covering the substrate; Multiple first trenches are formed in the medium layer of the protected area. The multiple first trenches extend along a first direction and are arranged in parallel along a second direction. The multiple first trenches form a shape surrounding the shielding area. Multiple second trenches are formed in the medium layer of the protected area. The multiple second trenches extend along the second direction and are arranged in parallel along the first direction. The multiple second trenches form a shape surrounding the shielding area. Each second trench penetrates multiple first trenches in the area along the second direction and is connected to multiple first trenches. The first trench is filled to form a first conductive layer located in the first trench; The second trench is filled to form a second conductive layer located in the second trench.

15. The method for forming a semiconductor device as described in claim 14, characterized in that, In the same step, the first trench and the second trench are filled.

16. The method for forming a semiconductor device as claimed in claim 12, characterized in that, The method for forming the semiconductor device further includes: after forming a bottom protective ring, forming a top protective ring on the bottom protective ring, wherein the top protective ring is electrically connected to the bottom protective ring, and the top protective ring comprises: Multiple first metal lines are formed on the bottom protective ring. The first metal lines extend along the second direction and are arranged in parallel along the first direction. The multiple first metal lines form a shape that surrounds the shielding area. Multiple second metal wires are formed on the first metal wire, the second metal wires extend along a first direction and are arranged in parallel along a second direction, the multiple second metal wires form a shape surrounding the shielding area, each second metal wire crosses the multiple first metal wires in the area along the first direction and is electrically connected to the multiple first metal wires.

17. A semiconductor structure, characterized in that, include: Sensing devices; The semiconductor device according to any one of claims 1 to 11, wherein the semiconductor device is located below the sensing device.

18. The semiconductor structure as claimed in claim 17, characterized in that, The sensing device is a radio frequency passive device.

19. The semiconductor structure as claimed in claim 17, characterized in that, The sensing device includes an input terminal, a metal body layer, and an output terminal, wherein the metal body layer extends from the input terminal in a spiral ring shape to the output terminal; The projection of the metal body layer onto the substrate surface is within the shielding area of ​​the substrate.

Images