An antireflection vertical cavity surface emitting laser

Abstract

This invention discloses an anti-reflection vertical-cavity surface-emitting laser (VCSEL). The anti-reflection CCSEL has an anti-reflection layer with a thickness equal to an odd multiple of one-quarter of the laser wavelength on the outer surface of the laser's output window. The anti-reflection layer consists of a lower silicon-based dielectric layer and an upper crystalline ITO layer. The refractive index of the silicon-based dielectric layer is between that of the crystalline ITO and the refractive index of the output window material. The thickness of the crystalline ITO layer is 5–15 nm. A series of nanopillars / nanopores are formed in the anti-reflection layer, extending downwards from the upper surface. The diameter of the nanopillars / nanopores is 50–400 nm, and the height / depth of the nanopillars / nanopores is less than or equal to the thickness of the anti-reflection layer and greater than or equal to one-third of the thickness of the anti-reflection layer. Compared to existing technologies, the anti-reflection CCSEL of this invention exhibits excellent anti-reflection performance and has a simple fabrication process and low cost.

Description

Technical Field

[0001] This invention relates to a vertical cavity surface-emitting laser, and more particularly to an anti-reflection vertical cavity surface-emitting laser. Background Technology

[0002] Unlike traditional edge-emitting lasers (EELs) such as DFB, DBR, and FB, vertical-cavity surface-emitting lasers (VCSELs) are semiconductor laser structures where an optical resonant cavity is formed perpendicular to the semiconductor epitaxial wafer, and the emitted laser beam is perpendicular to the substrate surface. They offer advantages such as small size, low power consumption, high efficiency, long lifetime, circular beam, and two-dimensional array integration, making them promising for applications in optical communication, attitude sensing sensors, printing, and magnetic storage. Due to the thin active region, short cavity length, and low single-layer gain of traditional VCSELs, oxide-confined DBR structures are currently widely used to improve their effective photon confinement capability. The oxide aperture formed by the oxide confinement structure provides excellent lateral control over the current injected into the active region, resulting in almost no lateral current. Simultaneously, this oxide aperture structure can also laterally confine the light emitted from the laser's active region, giving the laser fewer modes. A VCSEL with fewer modes can be stably coupled to an optical fiber.

[0003] The end faces of photonic devices such as connectors, splitters, terminators, and optical fibers have a certain reflectivity. When a vertical-cavity surface-emitting laser (VCSEL) transmits light between these devices, the device end faces reflect some of the light emitted by the laser back to the laser end face. The reflectivity of the laser end face then reflects back the light reflected from the device end faces. The light reflected back from the laser end face has a phase difference and an intensity difference compared to the emitted light. When both types of light are received by the devices simultaneously, it degrades the transmission quality of the optical communication signal. Furthermore, the light reflected back to the laser interacts with the laser's spontaneous emission, altering the laser's initial operating characteristics, such as increased spectral linewidth, increased threshold current, decreased signal-to-noise ratio, and increased relative intensity noise, thus affecting the laser's performance and reliability. Therefore, it is necessary to improve the anti-emission performance of VCSELs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide an anti-reflection vertical cavity surface-emitting laser with excellent anti-reflection performance, and with a simple manufacturing process and low cost.

[0005] The present invention specifically adopts the following technical solutions to solve the above-mentioned technical problems:

[0006] An antireflective vertical-cavity surface-emitting laser (VCSEL) has an antireflective layer with a thickness equal to an odd multiple of one-quarter of the laser wavelength disposed on the outer surface of the laser's output window. The antireflective layer consists of a lower silicon-based dielectric layer and an upper crystalline ITO layer. The refractive index of the silicon-based dielectric layer is between that of the crystalline ITO and the refractive index of the output window material. The thickness of the crystalline ITO layer is 5–15 nm. A series of nanopillars / nanopores are formed in the antireflective layer from the top surface downwards. The diameter of the nanopillars / nanopores is 50–400 nm. The height / depth of the nanopillars / nanopores is less than or equal to the thickness of the antireflective layer and greater than or equal to one-third of the thickness of the antireflective layer.

[0007] Preferably, the silicon-based dielectric layer is a composite of one or more of the following materials: SiON, SiN x Nanocrystalline silicon.

[0008] Preferably, the anti-reflection vertical-cavity surface-emitting laser is an oxide-confined vertical-cavity surface-emitting laser.

[0009] Preferably, the method for preparing the anti-reflective layer includes the following steps:

[0010] S1. The silicon-based dielectric layer is formed on the outer surface of the laser's light-emitting window;

[0011] S2. Perform hydrophobic surface treatment on the surface of the silicon-based dielectric layer;

[0012] S3. Deposit an amorphous ITO with a thickness of 5-15 nm on the surface of the silicon-based dielectric layer to form an incomplete amorphous ITO film;

[0013] S4. Annealing treatment transforms the deposited amorphous ITO into crystalline ITO, resulting in an incomplete crystalline ITO layer.

[0014] S5. Using the incomplete crystalline ITO layer as a self-aligned template, the silicon-based dielectric layer is etched to form the nanopillars / nanopores.

[0015] More preferably, the hydrophobic surface treatment is performed using radio frequency sputtering.

[0016] More preferably, the annealing temperature of the annealing treatment is 150–250 °C, and the annealing time is 60–130 s.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0018] This invention, by setting an anti-reflection layer with a nanopillar / nanopore microstructure on the outer surface of the traditional VCSEL light-emitting window, can effectively eliminate the possibility of crosstalk between the light reflected back from the laser end face and the light emitted by the laser, thus improving the transmission quality of optical communication signals. In addition, it also eliminates the possibility of the light reflected back to the laser interacting with the spontaneous light emitted by the laser, improving the performance and reliability of the laser. At the same time, the microstructure has a very good scattering effect on the light reflected back to the laser end face, eliminating the possibility of the light reflected back to the laser end face returning to the laser and affecting the performance of the laser.

[0019] This invention only requires adding an anti-reflection layer fabrication step after the traditional VCSEL fabrication process, without making significant changes to the existing VCSEL fabrication process. Moreover, the fabrication of the anti-reflection layer can be achieved using existing mature semiconductor equipment and processes, resulting in lower costs. Attached Figure Description

[0020] Figure 1 This is a schematic cross-sectional view of the oxidation-limited antireflective VCSEL of the present invention;

[0021] Figures 2-8 A schematic cross-sectional view of the present invention's oxide-restricted antireflective VCSEL with different morphological antireflective layers;

[0022] Figures 9 to 24 This is a schematic diagram illustrating the preparation process of the oxidation-limited antireflective VCSEL of the present invention.

[0023] The meanings of the reference numerals in the figure are as follows:

[0024] 1. GaAs substrate; 2. Buffer layer; 3. N-type DBR layer; 4. Quantum well active layer; 5. Oxide confinement layer; 6. P-type DBR layer; 7. Passivation layer; 8. P-type metal; 9. N-type metal; 10⁻¹ to 10⁻⁸ antireflection layer. Detailed Implementation

[0025] To improve the anti-reflection performance of VCSELs, the present invention proposes to set an anti-reflection layer with a nanopillar / nanopore microstructure on the outer surface of the light-emitting window of a traditional VCSEL.

[0026] The antireflective vertical-cavity surface-emitting laser proposed in this invention has an antireflective layer with a thickness of an odd multiple of one-quarter of the laser wavelength on the outer surface of the laser's output window. The antireflective layer consists of a lower silicon-based dielectric layer and an upper crystalline ITO layer. The refractive index of the silicon-based dielectric layer is between that of the crystalline ITO and the refractive index of the output window material. The thickness of the crystalline ITO layer is 5–15 nm. A series of nanopillars / nanopores are formed in the antireflective layer from the top surface downwards. The diameter of the nanopillars / nanopores is 50–400 nm. The height / depth of the nanopillars / nanopores is less than or equal to the thickness of the antireflective layer and greater than or equal to one-third of the thickness of the antireflective layer.

[0027] Preferably, the method for preparing the anti-reflective layer includes the following steps:

[0028] S1. The silicon-based dielectric layer is formed on the outer surface of the laser's light-emitting window;

[0029] S2. Perform hydrophobic surface treatment on the surface of the silicon-based dielectric layer;

[0030] S3. Deposit an amorphous ITO with a thickness of 5-15 nm on the surface of the silicon-based dielectric layer to form an incomplete amorphous ITO film;

[0031] S4. Annealing treatment transforms the deposited amorphous ITO into crystalline ITO, resulting in an incomplete crystalline ITO layer.

[0032] S5. Using the incomplete crystalline ITO layer as a self-aligned template, the silicon-based dielectric layer is etched to form the nanopillars / nanopores.

[0033] To facilitate public understanding, the technical solution of the present invention will be described in detail below using an oxidation-limited VCSEL as an example and in conjunction with the accompanying drawings. It should be noted that the anti-reflection structure in the anti-emission layer of the present invention is a nanoscale microstructure, which has been enlarged in the accompanying drawings for clearer illustration.

[0034] Figure 1 The cross-sectional structure of the oxide-limited antireflective VCSEL of this embodiment is shown, as follows: Figure 1 As shown, it includes: a GaAs substrate 1, a buffer layer 2, an N-type DBR layer 3, a quantum well active layer 4, an oxide confinement layer 5, a P-type DBR layer 6, a passivation layer 7, a P-type metal 8, and an N-type metal 9. An oxide hole is formed in the center of the oxide confinement layer, and the area surrounded by the P-type metal 8 is the laser's output window. This part of the structure is the same as that of existing oxide-confined VCSELs. Figure 1As shown, the present invention differs from existing VCSELs in that an anti-reflection layer 10-1 with a thickness of (2n+1)λ / 4 is provided on the outer surface of the light-emitting window, where λ is the laser wavelength and n is a natural number, i.e., the thickness of the anti-reflection layer 10-1 is an odd multiple of one-quarter of the laser wavelength; the anti-reflection layer 10-1 is composed of a lower silicon-based dielectric layer and an upper crystalline ITO layer, the refractive index of the silicon-based dielectric layer is between the refractive index of the crystalline ITO (lower refractive index) and the refractive index of the light-emitting window material (higher refractive index), the thickness of the crystalline ITO layer is 5-15 nm, and a series of nanopillars / nanopores are formed in the anti-reflection layer 10-1 from the upper surface downward, the diameter of the nanopillars / nanopores is 50-400 nm, and the height / depth of the nanopillars / nanopores is less than or equal to the thickness of the anti-reflection layer and greater than or equal to one-third of the thickness of the anti-reflection layer 10-1. Figure 1 The image shows one morphology of the nanostructure in the antireflective layer 10-1, where the height / depth of the nanopillars / nanopores is equal to the thickness of the antireflective layer, and the sidewalls of the nanopillars / nanopores are substantially perpendicular to the outer surface of the light-emitting window. When different etching depths and etching processes are used in the fabrication of the antireflective layer, the antireflective layer can exhibit other different morphologies. Figures 2-8 Figures 10⁻² to 10⁻⁸ show other morphologies of the antireflective layer. In some morphologies, the height / depth of the nanopillars / nanopores is less than the thickness of the antireflective layer. In some morphologies, the sidewalls of the nanopillars / nanopores are not perpendicular to the outer surface of the light-emitting window, and the whole is conical or inverted conical.

[0035] The material of the silicon-based dielectric layer must consider both etching performance and refractive index requirements; therefore, it is preferably a composite of one or more of the following materials: SiON, SiN. x Nanocrystalline silicon.

[0036] A nanostructure layer with nanopillars / nanopores is formed on the outer surface of the laser's output window. When the size of the nanostructure layer is sufficiently small, it forms a composite layer with a continuously varying refractive index with the air layer. Observing from the laser end face as the inside and the opposite side as the outside, the refractive index of this composite layer gradually decreases from the inside to the outside, eventually becoming the same as the refractive index of air. Observing from the outside to the inside, the refractive index of the composite layer changes in the opposite direction, gradually increasing. When the wavelength of the light emitted by the laser is larger than the diameter of the aforementioned nanopillars / nanopores, the light wave reflected back to the laser end face is affected by the continuous refractive index change within the composite layer, making the microstructure undetectable. This eliminates the reflection phenomenon caused by abrupt changes in refractive index and eliminates the possibility of the reflected light wave being returned to the laser end face.

[0037] Furthermore, the nanopillar / nanopore structure exhibits excellent scattering properties for light reflected back to the laser end face, eliminating the possibility of light reflected back to the laser end face returning to the laser interior and affecting laser performance.

[0038] The specific preparation process of the above-mentioned oxidation-limited antireflective VCSEL is as follows:

[0039] Step 1: The cross-section of the epitaxial wafer selected in this embodiment is as follows: Figure 9 As shown, the structure includes, from bottom to top, a GaAs substrate, a buffer layer, an N-type DBR layer, a quantum well active layer, and a P-type DBR layer; photoresist is coated on the epitaxial wafer surface, with a photoresist film thickness of 3-10 μm; the photoresist is exposed and developed to obtain a P-Mesa ring-shaped photoresist, see [reference]. Figure 10 ;

[0040] Step 2: Using ICP dry etching, etch the epitaxial wafer obtained in Step 1. The etching gas is Cl2 / BCl3 or Cl2 / SiCl4. Etch down to the 1-10 pairs of P-DBRs below the quantum well layer to form a P Mesa step structure, exposing the high-aluminum layer to be oxidized. See [link to relevant documentation]. Figure 11 Remove the photoresist to obtain the P Mesa stage, see [link / reference]. Figure 12 ;

[0041] Step 3: The Al in the high-alumina layer to be oxidized is oxidized using a wet oxidation process to obtain a P-Mesa step structure with an oxidation-confined structure. See [link to relevant documentation]. Figure 13 ;

[0042] Step 4: Deposit a passivation layer on the surface of the epitaxial wafer obtained in Step 3. The deposition process is PECVD or ALD, and the film material is SiN. x Materials include SiON, Al2O3, and TiO2. The film layer can be a single layer or a stack of the above materials, with a film thickness of 50-500 nm and a water vapor barrier capacity (WVTR) of 5E. -2 ~1E -4 See Figure 14 ;

[0043] Step 5: Etch the metal vias in the dielectric layer of the epitaxial wafer obtained in Step 4 using CF4+Ar or BOE as the etching gas, to obtain an epitaxial wafer with vias. See [link to relevant documentation]. Figure 15 ;

[0044] Step 6: Deposit metal to fill the Via holes of the epitaxial wafer obtained in Step 5. The metal can be Au, Pt, Ag, Al, etc. See [link to relevant documentation]. Figure 16 The existing fabrication process for oxide-limited VCSELs can now be completed; it is only necessary to cleave individual lasers or laser arrays from the wafer as needed.

[0045] Step 7: Deposit a silicon-based dielectric layer on the epitaxial wafer obtained in Step 6. The preferred material for the silicon-based dielectric layer is SiON or SiN. x Nanocrystalline Si, the film thickness is the target thickness of the antireflective layer minus the target thickness of the crystalline ITO layer, see [reference]. Figure 17 ;

[0046] Step 8: Coat the surface of the epitaxial wafer obtained in Step 7 with photoresist, the photoresist film thickness is 5-15 μm; expose and develop the photoresist, leaving only the light-emitting window with photoresist, and the other areas without photoresist, see [link to relevant documentation]. Figure 18 ;

[0047] Step 9: Etch the silicon-based dielectric layer on the epitaxial wafer completed in Step 8. The etching gas is CF4+Ar or BOE. After etching, remove the resist. After etching, only the surface of the laser emission window will have the silicon-based dielectric layer remaining. See [link to relevant documentation]. Figure 19 ;

[0048] Step 10: Coat the surface of the epitaxial wafer obtained in Step 9 with photoresist, the photoresist film thickness being 5-15 μm; expose and develop the photoresist until only the surface of the light-emitting window is free of photoresist, while the remaining areas are covered by photoresist. See [link to relevant documentation]. Figure 20 ;

[0049] Step 11: Perform hydrophobic surface treatment on the silicon-based dielectric layer on the light-emitting window of the epitaxial wafer obtained in Step 10. The surface contact angle of the silicon-based dielectric layer increases after hydrophobic surface treatment. The specific surface contact angle can be controlled by adjusting the hydrophobic surface treatment process parameters according to actual needs. Hydrophobic surface treatment can be performed using various existing chemical or physical methods, such as radio frequency sputtering and catalytic chemical vapor deposition. In this embodiment, radio frequency sputtering is used for hydrophobic surface treatment. The sputtering target is polytetrafluoroethylene, the sputtering gas is argon, the sputtering power is 20-100 W, the sputtering pressure is 5-50 Pa, and the surface treatment time is 5-60 s. See [link to relevant documentation]. Figure 20 ;

[0050] Step 12: Under vacuum, the epitaxial wafer, after hydrophobic surface treatment, is transferred to the ITO deposition chamber for amorphous ITO deposition, with a film thickness of 5-15 nm. This forms an incomplete amorphous ITO film on the surface of the silicon-based dielectric layer. (See [link to relevant documentation]). Figure 21 ;

[0051] Because the contact angle of the silicon-based dielectric layer increases after hydrophobic treatment, depositing an appropriate thickness of ITO will result in an incomplete thin film layer. This incompleteness is determined by the size of the contact angle on the silicon-based dielectric layer surface. When the contact angle is not too large (typically 100-120°), ITO forms a thin film with a network-like structure, such as... Figure 22As shown in the left image, the ITO is continuous at this point, with numerous voids distributed within the ITO film, each with a diameter of 50-100 nm. When the contact angle is large (typically above 120°), the ITO forms a completely discontinuous film, such as... Figure 22 As shown in the image on the right, a large number of ITO "islands" are distributed within the ITO film. The ITO "islands" are surrounded by continuous voids, and the diameter of a single ITO "island" is 100-400 nm.

[0052] After ITO deposition is completed and the photoresist is removed, the resulting epitaxial wafer is as follows: Figure 23 As shown;

[0053] Step 13: Annealing is performed to transform the deposited amorphous ITO into crystalline ITO, thereby improving the etching resistance stability of ITO as a self-aligned mask. At the same time, the refractive index of ITO decreases to 1.6 after annealing, which can improve the overall anti-reflection performance of the anti-reflection layer. In this embodiment, the annealing temperature is 150-250 °C and the annealing time is 60-130 s.

[0054] Step 14: Using the obtained incomplete crystalline ITO layer as a self-aligned mask, etch the silicon-based dielectric layer. The silicon-based dielectric layer in the ITO-covered area is protected, while the silicon-based dielectric layer in the area not covered by ITO is etched away. The etching gas can be CF4+Ar, CHF3+Ar, CH2F2+Ar, C4F8+Ar, or CF4+CHF3+Ar, CF4+CH2F2+Ar, CF4+CF8+Ar, CHF3+CH2F2+Ar, CHF3+CF8+Ar, CH2F2+CF8+Ar. In this embodiment, the etching power is 50-300 W, and the etching pressure is 0.1-5 Pa. The silicon-based dielectric layer in the area not covered by ITO is completely or partially etched away. After reaching the predetermined etching depth, the etching is stopped and the photoresist is removed, resulting in an anti-reflective layer with a microstructure of a series of nanopillars / nanopores from the top surface downwards. Figure 24 As shown; depending on the etching depth and etching process used, it is possible to form... Figures 1 to 8 The image shows various forms of anti-reflective layers.

Claims

1. An anti-reflection vertical-cavity surface-emitting laser, characterized in that, An antireflective layer with a thickness of an odd multiple of one-quarter of the laser wavelength is disposed on the outer surface of the laser's output window. The antireflective layer consists of a lower silicon-based dielectric layer and an upper crystalline ITO layer. The refractive index of the silicon-based dielectric layer is between that of the crystalline ITO and the refractive index of the output window material. The thickness of the crystalline ITO layer is 5–15 nm. A series of nanopillars / nanopores are formed in the antireflective layer from the top surface downwards. The diameter of the nanopillars / nanopores is 50–400 nm. The height / depth of the nanopillars / nanopores is less than or equal to the thickness of the antireflective layer and greater than or equal to one-third of the thickness of the antireflective layer.

2. The anti-reflection vertical-cavity surface-emitting laser as described in claim 1, characterized in that, The silicon-based dielectric layer is a composite of one or more of the following materials: SiON, SiN x Nanocrystalline silicon.

3. The anti-reflection vertical-cavity surface-emitting laser as described in claim 1, characterized in that, It is an oxide-confined vertical-cavity surface-emitting laser.

4. The anti-reflection vertical-cavity surface-emitting laser as described in any one of claims 1 to 3, characterized in that, The method for preparing the anti-reflective layer includes the following steps: S1. The silicon-based dielectric layer is formed on the outer surface of the laser's light-emitting window; S2. Perform hydrophobic surface treatment on the surface of the silicon-based dielectric layer; S3. Deposit an amorphous ITO with a thickness of 5-15 nm on the surface of the silicon-based dielectric layer to form an incomplete amorphous ITO film; S4. Annealing treatment transforms the deposited amorphous ITO into crystalline ITO, resulting in an incomplete crystalline ITO layer. S5. Using the incomplete crystalline ITO layer as a self-aligned template, the silicon-based dielectric layer is etched to form the nanopillars / nanopores.

5. The anti-reflection vertical-cavity surface-emitting laser as described in claim 4, characterized in that, The hydrophobic surface treatment is performed using radio frequency sputtering.

6. The anti-reflection vertical-cavity surface-emitting laser as described in claim 4, characterized in that, The annealing temperature for the annealing treatment is 150–250 °C, and the annealing time is 60–130 s.

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