BUCK open loop full-bridge control circuit

Abstract

The application discloses a BUCK open-loop full-bridge control circuit, comprising a BUCK drive control circuit and a full-bridge drive control circuit, wherein the BUCK drive control circuit comprises a first differential amplification circuit, a second differential amplification circuit, an AND gate circuit and a first NAND gate circuit, the reverse input end of the first differential amplification circuit is connected with a BUCK inductor current sampling signal, and the forward input end of the first differential amplification circuit is connected with an output voltage feedback signal; the full-bridge drive control circuit comprises an RC charging and discharging circuit, a charging and discharging control circuit, a third differential amplification circuit, a flip-flop circuit and a second NAND gate circuit. The application realizes the drive control circuit of the BUCK+ open-loop full-bridge by using discrete devices, and can guarantee the control signal to be accurate, the response speed to be fast and the reliability to be high while realizing 100% domesticization of power supply devices.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, specifically to a BUCK open-loop full-bridge control circuit. Background Technology

[0002] With the development of science and technology, the application of switching power supplies is becoming increasingly widespread, and the requirements for power density and efficiency are also becoming higher. The BUCK+ open-loop full-bridge topology, due to its ability to achieve soft switching at the full-bridge stage and its higher efficiency compared to traditional topologies, is widely used in the switching power supply field. However, due to the influence of regional trade, procuring foreign chips used in the BUCK+ open-loop full-bridge topology is difficult, and delivery times are very long, severely impacting the production of switching power supplies. Therefore, it is necessary to achieve domestic production of components, but currently there are no domestically available alternative chips. Summary of the Invention

[0003] To overcome the problem that the existing BUCK+ open-loop full-bridge topology cannot achieve 100% domestic component production due to the lack of domestically available alternative chips, this invention provides a BUCK open-loop full-bridge control circuit that, while achieving domestic production of power supply components, also ensures accurate control signals, fast response speed, and high reliability.

[0004] The technical solution of this invention is as follows:

[0005] A BUCK open-loop full-bridge control circuit includes a BUCK drive control circuit and a full-bridge drive control circuit. The BUCK drive control circuit includes a first differential amplifier circuit, a second differential amplifier circuit, an AND gate circuit, and a first NAND gate circuit. The inverting input terminal of the first differential amplifier circuit is connected to the BUCK inductor current sampling signal, the non-inverting input terminal of the first differential amplifier circuit is connected to the output voltage feedback signal, the output terminal of the first differential amplifier circuit is connected to the non-inverting input terminal of the second differential amplifier circuit, the inverting input terminal of the second differential amplifier circuit is connected to the charging / discharging terminal of the full-bridge drive control circuit, the output terminal of the second differential amplifier circuit is connected to the input terminal of the AND gate circuit, the output terminal of the AND gate circuit is connected to the input terminal of the first NAND gate circuit and the driving terminal of the BUCK power transistor, the output terminal of the first NAND gate circuit is connected to the driving terminal of the BUCK freewheeling transistor, the first output terminal of the full-bridge drive control circuit is connected to the driving terminal of the first full-bridge arm, and the second output terminal of the full-bridge drive control circuit is connected to the driving terminal of the second full-bridge arm.

[0006] According to the BUCK open-loop full-bridge control circuit of the above scheme, the first differential amplifier circuit includes a differential amplifier U4, resistors R1, R2, R3, and R4, and capacitors C1, C2, C3, and C4. The BUCK inductor current sampling signal is connected to the inverting input terminal of the differential amplifier U4, one end of capacitor C2, and one end of capacitor C3 after passing through resistor R2. The other end of capacitor C3 is connected to the other end of capacitor C2, the output terminal of differential amplifier U4, and the positive input terminal of the second differential amplifier circuit after passing through resistor R4. The output voltage feedback signal is connected to one end of resistor R3, one end of capacitor C1, and the positive input terminal of differential amplifier U4 after passing through resistor R1. The positive power supply terminal of differential amplifier U4 is connected to the power supply and one end of capacitor C4. The negative power supply terminal of differential amplifier U4, the other end of resistor R3, the other end of capacitor C1, and the other end of capacitor C4 are all grounded.

[0007] According to the BUCK open-loop full-bridge control circuit of the above scheme, the second differential amplifier circuit includes a differential amplifier U5, resistors R5, R6, R7 and capacitor C5. The output terminal of the first differential amplifier circuit is connected to the positive input terminal of the differential amplifier U5 and one end of resistor R7 after passing through resistor R5. The charging and discharging terminal of the full-bridge drive control circuit is connected to the inverting input terminal of the differential amplifier U5 after passing through resistor R6. The output terminal of the differential amplifier U5 is connected to the other end of resistor R7 and the input terminal of the AND gate circuit. The positive power supply terminal of the differential amplifier U5 is connected to the power supply and one end of capacitor C5. The negative power supply terminal of the differential amplifier U5 and the other end of capacitor C5 are both grounded.

[0008] According to the above scheme of BUCK open-loop full-bridge control circuit, the AND gate circuit includes AND gate U6. Pins 1 and 2 of AND gate U6 are both connected to the output terminal of the second differential amplifier circuit, pin 3 of AND gate U6 is grounded, and pin 4 of AND gate U6 is connected to the input terminal of the first NAND gate circuit and the driving terminal of BUCK power transistor, respectively.

[0009] According to the above scheme of BUCK open-loop full-bridge control circuit, the first NAND gate circuit includes NAND gate U7 and capacitor C6. Pins 1 and 2 of NAND gate U7 are both connected to the output terminal of the AND gate circuit. Pin 4 of NAND gate U7 is connected to the driving terminal of the BUCK freewheeling diode. Pin 5 of NAND gate U7 is connected to the power supply and one end of capacitor C6 respectively. The other end of capacitor C6 and pin 3 of NAND gate U7 are both grounded.

[0010] According to the above-described BUCK open-loop full-bridge control circuit, the full-bridge drive control circuit includes an RC charging / discharging circuit, a charging / discharging control circuit, a third differential amplifier circuit, a trigger circuit, and a second NAND gate circuit. The input terminals of the RC charging / discharging circuit and the positive input terminal of the third differential amplifier circuit are both connected to the power supply. The output terminal of the RC charging / discharging circuit is connected to the inverting input terminal of the second differential amplifier circuit, the output terminal of the charging / discharging control circuit, and the inverting input terminal of the third differential amplifier circuit, respectively. The output terminal of the third differential amplifier circuit is connected to the input terminal of the charging / discharging control circuit and the input terminal of the trigger circuit, respectively. The output terminal of the trigger circuit is connected to the input terminal of the second NAND gate circuit and the driving terminal of the first full-bridge arm, respectively. The output terminal of the second NAND gate circuit is connected to the driving terminal of the second full-bridge arm.

[0011] Furthermore, the full-bridge drive control circuit also includes a voltage divider circuit. The first terminal of the voltage divider circuit is connected to the power supply, the second terminal of the voltage divider circuit is connected to the positive input terminal of the third differential amplifier circuit, and the third terminal of the voltage divider circuit is connected to the output terminal of the third differential amplifier circuit.

[0012] Furthermore, the voltage divider circuit includes resistors R9, R10, and R13. The power supply passes through resistor R9 and is connected to the positive input terminal of the third differential amplifier circuit, one end of resistor R10, and one end of resistor R13, respectively. The other end of resistor R10 is grounded, and the other end of resistor R13 is connected to the output terminal of the third differential amplifier circuit.

[0013] Furthermore, the RC charging and discharging circuit includes a resistor R8 and a capacitor C7. The power supply passes through the resistor R8 and is connected to the inverting input terminal of the second differential amplifier circuit, the inverting input terminal of the third differential amplifier circuit, and one end of the capacitor C7. The other end of the capacitor C7 is grounded.

[0014] Furthermore, the charge / discharge control circuit includes switching transistors Q1 and Q2, resistors R11 and R12. Pin 3 of switching transistor Q1 is connected to the inverting input of the third differential amplifier circuit and the output of the RC charge / discharge circuit via resistor R11. Pin 2 of switching transistor Q1 is connected to pin 3 of switching transistor Q2 and one end of resistor R12. The other end of resistor R12 is connected to the power supply. Pin 2 of switching transistor Q2 is connected to the output of the third differential amplifier circuit. Pin 1 of both switching transistor Q1 and switching transistor Q2 is grounded.

[0015] Furthermore, the third differential amplifier circuit includes a differential amplifier U1 and a capacitor C8. The second terminal of the voltage divider circuit is connected to the positive input terminal of the differential amplifier U1. The output terminal of the RC charge-discharge circuit is connected to the inverting input terminal of the differential amplifier U1. The output terminal of the differential amplifier U1 is connected to the third terminal of the voltage divider circuit, the input terminal of the charge-discharge control circuit, and the input terminal of the trigger circuit. The positive power supply terminal of the differential amplifier U5 is connected to the power supply and one end of the capacitor C8. The negative power supply terminal of the differential amplifier U1 and the other end of the capacitor C8 are both grounded.

[0016] Furthermore, the trigger circuit includes a D flip-flop U2 and a capacitor C9. Pin 1 of the D flip-flop U2 is connected to the output of the second NAND gate circuit, pin 2 of the D flip-flop U2 is connected to the output of the third differential amplifier circuit, pin 3 of the D flip-flop U2 is grounded, pin 4 of the D flip-flop U2 is connected to the input of the second NAND gate circuit and the driving terminal of the first full-bridge arm, pin 5 of the D flip-flop U2 is connected to the power supply and one end of the capacitor C9, and the other end of the capacitor C9 is grounded.

[0017] Furthermore, the second NAND gate circuit includes NAND gate U3. Pins 1 and 2 of NAND gate U3 are both connected to pin 4 of D flip-flop U2. Pin 3 of NAND gate U3 is grounded. Pin 4 of NAND gate U3 is connected to pin 1 of D flip-flop U2 and the driving terminal of the second full-bridge arm, respectively. Pin 5 of NAND gate U3 is connected to the power supply.

[0018] Furthermore, the first full-bridge arm and the second full-bridge arm are alternately turned on by 180 degrees. The output terminal of the trigger circuit outputs a first PWM drive signal to the input terminal of the second NAND gate circuit and the drive terminal of the first full-bridge arm. The output terminal of the second NAND gate circuit outputs a second PWM drive signal to the drive terminal of the second full-bridge arm. The first PWM drive signal and the second PWM drive signal are out of phase by 180 degrees.

[0019] Furthermore, the duty cycles of the first PWM drive signal and the second PWM drive signal are both 50%.

[0020] According to the above scheme, the driving frequency of the BUCK drive control circuit is twice the driving frequency of the full-bridge drive control circuit.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] The present invention provides a BUCK open-loop full-bridge control circuit, which is divided into two parts: a BUCK drive control circuit and a full-bridge drive control circuit. It uses discrete components to realize the drive control circuit of BUCK + open-loop full-bridge. While achieving 100% localization of power supply components, it can also ensure simple circuit structure, accurate control signal, fast response speed, high reliability, and prevent power supply from having differential frequency oscillation. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the principle framework of the present invention;

[0025] Figure 2 This is a circuit diagram of the BUCK drive control circuit in this invention;

[0026] Figure 3 This is a circuit diagram of the full-bridge drive control circuit in this invention. Detailed Implementation

[0027] To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It is also stated that the embodiments described below are for illustrative purposes only and are not intended to limit the invention.

[0028] It should be noted that the term "connection" and similar terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal connection of two components or the interaction between two components, unless otherwise explicitly defined. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or specifying the number of technical features.

[0029] Please see Figure 1This embodiment provides a BUCK open-loop full-bridge control circuit, including a BUCK drive control circuit 1 and a full-bridge drive control circuit 2. The drive frequency of the BUCK drive control circuit 1 is twice that of the full-bridge drive control circuit 2, which can prevent differential frequency oscillation in the power supply and is beneficial to the power supply output characteristics.

[0030] Please see Figure 1 In this embodiment, the BUCK drive control circuit 1 includes a first differential amplifier circuit 101, a second differential amplifier circuit 102, an AND gate circuit 103, and a first NAND gate circuit 104. The inverting input terminal of the first differential amplifier circuit 101 is connected to the BUCK inductor current sampling signal IV, the non-inverting input terminal of the first differential amplifier circuit 101 is connected to the output voltage feedback signal VE, and the output terminal of the first differential amplifier circuit 101 is connected to the non-inverting input terminal of the second differential amplifier circuit 102. The input terminal is connected to the charging and discharging terminal of the full-bridge drive control circuit 2. The output terminal of the second differential amplifier circuit 102 is connected to the input terminal of the AND gate circuit 103. The output terminal of the AND gate circuit 103 is connected to the input terminal of the first NAND gate circuit 104 and the driving terminal of the BUCK power transistor, respectively. The output terminal of the first NAND gate circuit 104 is connected to the driving terminal of the BUCK freewheeling transistor. The first output terminal of the full-bridge drive control circuit 2 is connected to the driving terminal of the first full-bridge arm. The second output terminal of the full-bridge drive control circuit 2 is connected to the driving terminal of the second full-bridge arm.

[0031] Please see Figure 2 Specifically, the first differential amplifier circuit 101 includes a differential amplifier U4, resistors R1, R2, R3, and R4, and capacitors C1, C2, C3, and C4. The BUCK inductor current sampling signal IV passes through resistor R2 and is connected to the inverting input terminal of the differential amplifier U4, one end of capacitor C2, and one end of capacitor C3. The other end of capacitor C3 passes through resistor R4 and is connected to the other end of capacitor C2, the output terminal of the differential amplifier U4, and the positive input terminal of the second differential amplifier circuit 102. The output voltage feedback signal VE passes through resistor R1 and is connected to one end of resistor R3, one end of capacitor C1, and the positive input terminal of the differential amplifier U4. The positive power supply terminal of the differential amplifier U4 is connected to the 5V power supply and one end of capacitor C4. The negative power supply terminal of the differential amplifier U4, the other end of resistor R3, the other end of capacitor C1, and the other end of capacitor C4 are all grounded.

[0032] Please see Figure 2Specifically, the second differential amplifier circuit 102 includes a differential amplifier U5, resistors R5, R6, R7, and capacitor C5. The output terminal of the first differential amplifier circuit 101 is connected to the positive input terminal of the differential amplifier U5 and one end of resistor R7 via resistor R5. The charging and discharging terminal of the full-bridge drive control circuit 2 is connected to the inverting input terminal of the differential amplifier U5 via resistor R6. The output terminal of the differential amplifier U5 is connected to the other end of resistor R7 and the input terminal of AND gate circuit 103. The positive power supply terminal of the differential amplifier U5 is connected to the 5V power supply and one end of capacitor C5. The negative power supply terminal of the differential amplifier U5 and the other end of capacitor C5 are both grounded.

[0033] Please see Figure 2 Specifically, the AND gate circuit 103 includes an AND gate U6. Pins 1 and 2 of the AND gate U6 are both connected to the output of the second differential amplifier circuit 102. Pin 3 of the AND gate U6 is grounded. Pin 4 of the AND gate U6 is connected to the input of the first NAND gate circuit 104 and the driving terminal of the BUCK power transistor, respectively.

[0034] Please see Figure 2 Specifically, the first NAND gate circuit 104 includes a NAND gate U7 and a capacitor C6. Pins 1 and 2 of the NAND gate U7 are both connected to the output terminal of the AND gate circuit 103. Pin 4 of the NAND gate U7 is connected to the driving terminal of the BUCK freewheeling diode. Pin 5 of the NAND gate U7 is connected to the 5V power supply and one end of the capacitor C6, respectively. The other end of the capacitor C6 and pin 3 of the NAND gate U7 are both grounded.

[0035] The working principle of the above-mentioned BUCK drive control circuit 1:

[0036] The BUCK inductor current sampling signal IV is sent to the inverting input of differential amplifier U4 after passing through resistor R2. The output voltage feedback signal VE is sent to the non-inverting input of differential amplifier U4 after passing through resistor R1. The signals received by the non-inverting and inverting inputs of differential amplifier U4 are differentially amplified by the internal integrated circuit and output as a level signal through the output of differential amplifier U4. This level signal is sent to the non-inverting input of differential amplifier U5 after passing through resistor R5. The inverting input of differential amplifier U5 receives the RC charge and discharge from the full-bridge drive control circuit 2. The triangular wave signal RAMP output by the circuit (i.e., the charging / discharging terminal) is compared with the signals received at the positive and negative input terminals of the differential amplifier U5. A PWM wave is then output at the output of the differential amplifier U5. This PWM wave passes through AND gate U6, and pin 4 of AND gate U6 outputs a first drive signal DT to the drive terminal of the BUCK power transistor. The first drive signal DT then passes through NAND gate U7, generating a second drive signal DTOFF, which is complementary to the first drive signal DT, and is sent to the drive terminal of the BUCK freewheeling transistor to control its switching. The first drive signal DT and the second drive signal DTOFF work in a complementary manner; when the first drive signal DT is high, the second drive signal DTOFF is low, and vice versa. In other embodiments, if the BUCK uses a diode for freewheeling, then NAND gate U7 can be omitted, making the control method simpler and more reliable, but the efficiency will be reduced.

[0037] Please see Figure 1In this embodiment, the full-bridge drive control circuit 2 includes an RC charge / discharge circuit 201, a voltage divider circuit 202, a charge / discharge control circuit 203, a third differential amplifier circuit 204, a trigger circuit 205, and a second NAND gate circuit 206. The input terminal of the RC charge / discharge circuit 201 and the first terminal of the voltage divider circuit 202 are both connected to a 5V power supply. The second terminal of the voltage divider circuit 202 is connected to the positive input terminal of the third differential amplifier circuit 204. The output terminal of the RC charge / discharge circuit 201 is connected to the second differential amplifier circuit 206. The inverting input terminal of the voltage divider circuit 202, the output terminal of the charge / discharge control circuit 203, and the inverting input terminal of the third differential amplifier circuit 204 are connected. The output terminal of the third differential amplifier circuit 204 is connected to the third terminal of the voltage divider circuit 202, the input terminal of the charge / discharge control circuit 203, and the input terminal of the trigger circuit 205. The output terminal of the trigger circuit 205 is connected to the input terminal of the second NAND gate circuit 206 and the driving terminal of the first full-bridge arm. The output terminal of the second NAND gate circuit 206 is connected to the driving terminal of the second full-bridge arm. The full-bridge circuit operates in open-loop mode with no freewheeling inductor in the subsequent stage. The first and second full-bridge arms alternately conduct 180 degrees to ensure stable output voltage. In addition, the output terminal of the trigger circuit 205 outputs the first PWM drive signal LO to the input terminal of the second NAND gate circuit 206 and the drive terminal of the first full-bridge arm. The output terminal of the second NAND gate circuit 206 outputs the second PWM drive signal HO to the drive terminal of the second full-bridge arm. The first PWM drive signal LO and the second PWM drive signal HO are a pair of complementary PWM drive signals with a duty cycle of 50% respectively. The first PWM drive signal LO and the second PWM drive signal HO are out of phase by 180 degrees to achieve alternating conduction of the first and second full-bridge arms of the open-loop full-bridge.

[0038] Please see Figure 3 Specifically, the RC charging and discharging circuit 201 includes a resistor R8 and a capacitor C7. The 5V power supply passes through the resistor R8 and is connected to the inverting input terminal of the second differential amplifier circuit 102, the inverting input terminal of the third differential amplifier circuit 204, and one end of the capacitor C7. The other end of the capacitor C7 is grounded.

[0039] Please see Figure 3 Specifically, the voltage divider circuit 202 includes resistors R9, R10, and R13. The 5V power supply is connected to the positive input terminal of the third differential amplifier circuit 204, one end of resistor R10, and one end of resistor R13 after passing through resistor R9. The other end of resistor R10 is grounded, and the other end of resistor R13 is connected to the output terminal of the third differential amplifier circuit 204.

[0040] Please see Figure 3Specifically, the charge / discharge control circuit 203 includes switching transistors Q1 and Q2, resistors R11 and R12. Pin 3 of switching transistor Q1 is connected via resistor R11 to both the inverting input of the third differential amplifier circuit 204 and the output of the RC charge / discharge circuit 201. Pin 2 of switching transistor Q1 is connected to pin 3 of switching transistor Q2 and one end of resistor R12. The other end of resistor R12 is connected to a 5V power supply. Pin 2 of switching transistor Q2 is connected to the output of the third differential amplifier circuit 204. Pins 1 of both switching transistors Q1 and Q2 are grounded. The charge / discharge control circuit 203, composed of switching transistors Q1 and Q2, resistors R11 and R12, controls the on / off state of the discharge circuit at the inverting input of the differential amplifier U1.

[0041] Please see Figure 3 Specifically, the third differential amplifier circuit 204 includes a differential amplifier U1 and a capacitor C8. The second terminal of the voltage divider circuit 202 is connected to the positive input terminal of the differential amplifier U1. The output terminal of the RC charge-discharge circuit 201 is connected to the inverting input terminal of the differential amplifier U1. The output terminal of the differential amplifier U1 is connected to the third terminal of the voltage divider circuit 202, the input terminal of the charge-discharge control circuit 203, and the input terminal of the trigger circuit 205, respectively. The positive power supply terminal of the differential amplifier U1 is connected to the 5V power supply and one end of the capacitor C8, respectively. The negative power supply terminal of the differential amplifier U1 and the other end of the capacitor C8 are both grounded.

[0042] Please see Figure 3 Specifically, the trigger circuit 205 includes a D flip-flop U2 and a capacitor C9. Pin 1 of the D flip-flop U2 is connected to the output of the second NAND gate circuit 206. Pin 2 of the D flip-flop U2 is connected to the output of the third differential amplifier circuit 204. Pin 3 of the D flip-flop U2 is grounded. Pin 4 of the D flip-flop U2 is connected to the input of the second NAND gate circuit 206 and the driving end of the first full-bridge arm, respectively. Pin 5 of the D flip-flop U2 is connected to the 5V power supply and one end of the capacitor C9, respectively. The other end of the capacitor C9 is grounded.

[0043] Please see Figure 3 Specifically, the second NAND gate circuit 206 includes a NAND gate U3. Pins 1 and 2 of the NAND gate U3 are both connected to pin 4 of the D flip-flop U2. Pin 3 of the NAND gate U3 is grounded. Pin 4 of the NAND gate U3 is connected to pin 1 of the D flip-flop U2 and the driving terminal of the second full-bridge arm, respectively. Pin 5 of the NAND gate U3 is connected to a 5V power supply.

[0044] The working principle of the above-mentioned full-bridge drive control circuit 2:

[0045] The 5V power supply charges and discharges capacitor C7 through resistor R8, generating a triangular wave signal RAMP. The voltage at the positive input terminal of differential amplifier U1 is formed by the voltage divider circuit 202, which consists of the 5V power supply and resistors R9, R10, and R13. When the output terminal of differential amplifier U1 is high, resistor R13 is equivalent to being connected in parallel with resistor R9, resulting in a higher voltage at the positive input terminal of differential amplifier U1. When the output terminal of differential amplifier U1 is low, resistor R13 is equivalent to being connected in parallel with resistor R10, resulting in a lower voltage at the positive input terminal of differential amplifier U1. The voltage at the positive input terminal of differential amplifier U1 can be varied by resistor R13.

[0046] The charging and discharging control circuit 203, composed of switching transistors Q1 and Q2, resistors R11 and R12, controls the on / off state of the discharge circuit at the inverting input of differential amplifier U1. When the output of differential amplifier U1 is high, switching transistor Q2 is turned on and switching transistor Q1 is turned off, at which time capacitor C7 is in the charging state; when the output of differential amplifier U1 is low, switching transistor Q2 is turned off and switching transistor Q1 is turned on, at which time capacitor C7 is in the discharging state. After the positive and negative input terminals of differential amplifier U1 are compared, a clock signal is generated at the output terminal of differential amplifier U1. This clock signal is sent to pin 2 of D flip-flop U2, and then the clock signal is divided by D flip-flop U2. Pin 4 of D flip-flop U2 outputs the first PWM drive signal LO to the drive terminal of the first full-bridge arm. The first PWM drive signal LO is then passed through NAND gate U3 to generate a second PWM drive signal HO that is 180 degrees out of phase with the first PWM drive signal LO, which is sent to the drive terminal of the second full-bridge arm. The first PWM drive signal LO and the second PWM drive signal HO are used to alternately conduct the first and second full-bridge arms of the open-loop full-bridge.

[0047] In summary, the BUCK open-loop full-bridge control circuit provided in this embodiment of the invention is divided into two parts: BUCK drive control circuit 1 and full-bridge drive control circuit 2. It utilizes discrete components to realize the drive control circuit of BUCK + open-loop full-bridge, achieving 100% localization of power supply components while ensuring simple circuit structure, accurate control signals, fast response speed, high reliability, and preventing differential frequency oscillation of the power supply.

[0048] It should be understood that those skilled in the art can make improvements or modifications based on the above description to achieve protection in other aspects, such as undervoltage and overcurrent protection, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0049] The present invention has been described above with reference to the accompanying drawings. Obviously, the implementation of the present invention is not limited to the above-described manner. Any improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A BUCK open-loop full-bridge control circuit, comprising a BUCK drive control circuit and a full-bridge drive control circuit, characterized in that, The BUCK drive control circuit includes a first differential amplifier circuit, a second differential amplifier circuit, an AND gate circuit, and a first NAND gate circuit. The inverting input terminal of the first differential amplifier circuit is connected to the BUCK inductor current sampling signal, the non-inverting input terminal of the first differential amplifier circuit is connected to the output voltage feedback signal, the output terminal of the first differential amplifier circuit is connected to the non-inverting input terminal of the second differential amplifier circuit, the inverting input terminal of the second differential amplifier circuit is connected to the charging / discharging terminal of the full-bridge drive control circuit, the output terminal of the second differential amplifier circuit is connected to the input terminal of the AND gate circuit, the output terminal of the AND gate circuit is connected to the input terminal of the first NAND gate circuit and the driving terminal of the BUCK power transistor, the output terminal of the first NAND gate circuit is connected to the driving terminal of the BUCK freewheeling transistor, the first output terminal of the full-bridge drive control circuit is connected to the driving terminal of the first full-bridge arm, and the second output terminal of the full-bridge drive control circuit is connected to the driving terminal of the second full-bridge arm. The full-bridge drive control circuit includes an RC charging / discharging circuit, a charging / discharging control circuit, a third differential amplifier circuit, a trigger circuit, and a second NAND gate circuit. The input terminals of the RC charging / discharging circuit and the positive input terminal of the third differential amplifier circuit are both connected to the power supply. The output terminal of the RC charging / discharging circuit is connected to the inverting input terminal of the second differential amplifier circuit, the output terminal of the charging / discharging control circuit, and the inverting input terminal of the third differential amplifier circuit, respectively. The output terminal of the third differential amplifier circuit is connected to the input terminal of the charging / discharging control circuit and the input terminal of the trigger circuit, respectively. The output terminal of the trigger circuit is connected to the input terminal of the second NAND gate circuit and the driving terminal of the first full-bridge arm, respectively. The output terminal of the second NAND gate circuit is connected to the driving terminal of the second full-bridge arm.

2. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The first differential amplifier circuit includes a differential amplifier U4, resistors R1, R2, R3, and R4, and capacitors C1, C2, C3, and C4. The BUCK inductor current sampling signal passes through resistor R2 and is connected to the inverting input terminal of differential amplifier U4, one end of capacitor C2, and one end of capacitor C3. The other end of capacitor C3 passes through resistor R4 and is connected to the other end of capacitor C2, the output terminal of differential amplifier U4, and the positive input terminal of the second differential amplifier circuit. The output voltage feedback signal passes through resistor R1 and is connected to one end of resistor R3, one end of capacitor C1, and the positive input terminal of differential amplifier U4. The positive power supply terminal of differential amplifier U4 is connected to the power supply and one end of capacitor C4. The negative power supply terminal of differential amplifier U4, the other end of resistor R3, the other end of capacitor C1, and the other end of capacitor C4 are all grounded.

3. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The second differential amplifier circuit includes a differential amplifier U5, resistors R5, R6, and R7, and a capacitor C5. The output terminal of the first differential amplifier circuit is connected to the positive input terminal of the differential amplifier U5 and one end of resistor R7 via resistor R5. The charging and discharging terminal of the full-bridge drive control circuit is connected to the inverting input terminal of the differential amplifier U5 via resistor R6. The output terminal of the differential amplifier U5 is connected to the other end of resistor R7 and the input terminal of the AND gate circuit. The positive power supply terminal of the differential amplifier U5 is connected to the power supply and one end of capacitor C5. The negative power supply terminal of the differential amplifier U5 and the other end of capacitor C5 are both grounded.

4. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The AND gate circuit includes an AND gate U6. Pins 1 and 2 of the AND gate U6 are both connected to the output of the second differential amplifier circuit. Pin 3 of the AND gate U6 is grounded. Pin 4 of the AND gate U6 is connected to the input of the first NAND gate circuit and the driving terminal of the BUCK power transistor, respectively. Pin 5 of the AND gate U6 is connected to the power supply.

5. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The first NAND gate circuit includes a NAND gate U7 and a capacitor C6. Pins 1 and 2 of the NAND gate U7 are both connected to the output terminal of the AND gate circuit. Pin 4 of the NAND gate U7 is connected to the driving terminal of the BUCK freewheeling diode. Pin 5 of the NAND gate U7 is connected to the power supply and one end of the capacitor C6 respectively. The other end of the capacitor C6 and pin 3 of the NAND gate U7 are both grounded.

6. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The full-bridge drive control circuit also includes a voltage divider circuit. The first terminal of the voltage divider circuit is connected to the power supply, the second terminal of the voltage divider circuit is connected to the positive input terminal of the third differential amplifier circuit, and the third terminal of the voltage divider circuit is connected to the output terminal of the third differential amplifier circuit.

7. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The first full-bridge arm and the second full-bridge arm are alternately turned on by 180 degrees. The output terminal of the trigger circuit outputs a first PWM drive signal to the input terminal of the second NAND gate circuit and the drive terminal of the first full-bridge arm. The output terminal of the second NAND gate circuit outputs a second PWM drive signal to the drive terminal of the second full-bridge arm. The first PWM drive signal and the second PWM drive signal are out of phase by 180 degrees.

8. The BUCK open-loop full-bridge control circuit according to claim 7, characterized in that, The duty cycle of both the first PWM drive signal and the second PWM drive signal is 50%.

9. The BUCK open-loop full-bridge control circuit according to claim 1, characterized in that, The drive frequency of the BUCK drive control circuit is twice that of the full-bridge drive control circuit.

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