A Common-Mode Voltage Cancellation Method Based on Multi-Level SVPWM Modulation in Non-Orthogonal Coordinate Systems

Abstract

This invention provides a common-mode voltage elimination method for multi-level SVPWM modulation based on a non-orthogonal coordinate system. By introducing a new non-orthogonal coordinate system and performing coordinate transformation and inverse transformation, the common-mode voltage is completely eliminated, thus thoroughly avoiding its adverse effects on the system. Although the final output switching state with zero common-mode voltage is not the nearest three vectors, the reference voltage can still be synthesized using the nearest three vectors method before the final inverse coordinate transformation step, thereby effectively reducing the difficulty of selecting the switching vectors. The quadratic abc coordinate system proposed in this invention is essentially a trimmed version of the original abc coordinate system, ensuring that existing vector synthesis methods based on the abc coordinate system remain practical and providing valuable reference for other modulation methods.

Description

Technical Field

[0001] This invention belongs to the field of multilevel space vector modulation technology for power electronic devices, specifically relating to a method for eliminating common-mode voltage in multilevel SVPWM modulation based on a non-orthogonal coordinate system. Background Technology

[0002] Currently, Space Vector Pulsation (SVPWM) is widely used in multilevel converter modulation due to its high voltage utilization and the ability to optimize converter performance through the rational selection of redundant switching states. However, most existing multilevel SVPWM algorithms use the nearest three vectors to synthesize the reference voltage vector. This can only limit the common-mode voltage amplitude to a certain level through the rational selection of redundant switching states, but cannot completely eliminate it. This means that problems caused by common-mode voltage, such as bearing current, power loss, electromagnetic interference, and insulation faults, cannot be eradicated. While selecting non-nearest three vectors offers some possibility for completely eliminating common-mode voltage, a good method for selecting switching states has not yet been developed in the current technology. Furthermore, the modulation complexity of non-nearest three vectors compared to the nearest three vector method limits their practical application. Summary of the Invention

[0003] In view of this, and to address the technical problems existing in this field, the present invention provides a method for eliminating common-mode voltage in multi-level SVPWM modulation based on a non-orthogonal coordinate system, specifically including the following steps:

[0004] Step 1: Perform coordinate transformation on the SVPWM switching vector using the following transformation matrix T:

[0005]

[0006] Transform the switch vector from the original abc coordinate system to a new coordinate system so that the coordinates of the transformed switch vector have a fractional form;

[0007] Step 2: Divide the switching states in the new coordinate system into two categories: the first category is obtained by transforming the switching states that generate zero common-mode voltage in the original abc coordinate system; the second category is the remaining switching states; the desired output switching state is selected only from the switching states of the first category through subsequent transformations.

[0008] Step 3: Set a real number for any switch state in the new coordinate system, so that the corresponding switch vector coordinates after adding the first type of switch state to the real number can be changed from the fractional form to the integer form, while the switch vector coordinates after adding any real number to the second type of switch state cannot be changed from the fractional form to the integer form.

[0009] Step 4: Extract the first type of switch state corresponding to the switch vector coordinates that can be converted into integers in Step 3 in the new coordinate system, add them to one or more real numbers and convert them into switch states with values ​​between [0n-1] to simplify the spatial vector diagram, where n is the number of converter levels, and at the same time obtain a quadratic abc coordinate system;

[0010] Step 5: After determining the available nearest three-vector switching state in the quadratic abc coordinate system based on the reference voltage vector, use the inverse matrix T of the transformation matrix T. inv Transform it into the original abc coordinate system as a switch state; add each switch state to a positive offset to obtain the final output switch state, which is used to synthesize a reference voltage in the original abc coordinate system.

[0011] Furthermore, the transformation matrix T mentioned in step one is non-full rank. Redundant switching states of the same switching vector in the original abc coordinate system correspond to the same switching state in the new coordinate system. And since the inverse matrix of the non-full rank transformation matrix T cannot be directly obtained, the constraint that the sum of the phase voltages of the three-phase balanced system is zero can be introduced to obtain its inverse matrix:

[0012]

[0013] Inverse matrix T inv It is also not full rank, which ensures the switching state (C) a C b C c ) and (C a +α,C b +α,C c When transforming from the new coordinate system back to the original abc coordinate system, +α)(α is a real number) will still correspond to the same switch state.

[0014] Furthermore, in step five, the inverse matrix T is used. inv The nearest available three vectors are transformed into the switch state in the original abc coordinate system, so that its coordinate values ​​are in the range of [-(n-1) / 2(n-1) / 2]; the corresponding positive offset is set to (n-1) / 2, so that the final output switch state coordinate values ​​are in the range of [0n-1] and the generated common-mode voltages are all zero.

[0015] The multi-level SVPWM modulation common-mode voltage elimination method based on a non-orthogonal coordinate system provided by the present invention achieves complete elimination of common-mode voltage by introducing a new non-orthogonal coordinate system and performing coordinate transformation and inverse transformation, thus completely avoiding its adverse effects on the system. Although the final output switching state with zero common-mode voltage is not the nearest three vectors, the reference voltage can still be synthesized using the nearest three vectors method before the final inverse coordinate transformation step, thereby effectively reducing the difficulty of selecting the switching vectors. The quadratic abc coordinate system proposed in this invention is essentially a trimming of the original abc coordinate system, ensuring that existing vector synthesis methods based on the abc coordinate system remain practical and also providing significant reference value for other modulation methods. Attached Figure Description

[0016] Figure 1 This is a five-level spatial vector diagram in the original abc coordinate system;

[0017] Figure 2 This is a schematic diagram illustrating the transformation from the original abc coordinate system to the new coordinate system in this invention;

[0018] Figure 3 This is a five-level spatial vector diagram of an example of the present invention in a quadratic abc coordinate system. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In one embodiment based on the present invention, the above method is performed on a five-level converter. Each phase of the five-level converter can generate five levels {0, 1, 2, 3, 4}, and the three-phase levels are combined to form five levels. 3 = 125 switch states. For Figure 1 The existing multilevel SVPWM modulation shown typically uses the nearest three vectors to synthesize the reference voltage vector, such as the reference voltage vector V. ref It can be synthesized from the three nearest vectors (0,3,1), (1,3,1) and (1,3,2), but the two remaining vectors, except for the switching vector (1,3,2), produce different levels of common-mode voltage.

[0021] Figure 2 and Figure 3 The coordinate transformation process of the switch vector obtained by this invention is shown, and the specific steps include:

[0022] Step 1, such as Figure 2As shown in (a), taking hexagons H1 and H2 in the five-level space vector diagram as examples, the switch vectors on H1 and H2 are transformed from the original abc coordinate system to the new coordinate system through matrix T, as follows: Figure 2 As shown in (b), the switch vector coordinates in the new abc coordinate system have a fractional form.

[0023] like Figure 2 As shown in (b), the transformation matrix T is non-full rank, ensuring that redundant switch states of the same switch vector in the original abc coordinate system correspond to the same switch state in the new coordinate system. Furthermore, the inverse matrix T is non-full rank. inv This makes the switching state (C) in the new coordinate system a C b C c ) and (C a +α,C b +α,C c When +α)(α is a real number) is transformed back to the original abc coordinate system, it will also correspond to the same switch state.

[0024] Step 2: Divide the switching states in the new abc coordinate system into two categories: the first category is obtained by transforming the switching states that generate zero common-mode voltage in the original abc coordinate system; the second category is the remaining switching states; the desired output switching state is selected only from the switching states of the first category through subsequent transformations.

[0025] Step 3: Set a usable real number in the real number field for any switch state in the new coordinate system, for example... Figure 2 (b) The switch state located on the dotted-dash hexagon can be increased by 1 / 3 or 2 / 3 to become an integer, while the second type of switch state cannot be changed from a fraction to an integer after being added to any real number.

[0026] Step 4: Extract the first type of switch state corresponding to the switch vector coordinates that can be converted into integers in Step 3 in the new abc coordinate system, add them to one or more real numbers and convert them into switch states with values ​​between [0 4] to simplify the spatial vector diagram, and at the same time obtain a quadratic abc coordinate system;

[0027] For example, Figure 2 The switch states (-1 / 3, -1 / 3, 2 / 3) in (b) can be transformed into (0, 0, 1), (1, 1, 2), (2, 2, 3), and (3, 3, 4) by adding 1 / 3, 4 / 3, 7 / 3, and 10 / 3 respectively. Extracting all such switch states and adding different real numbers yields the following results: Figure 3 The novel non-orthogonal coordinate system is shown. It can be seen that the novel non-orthogonal coordinate system is similar to... Figure 1The spatial vector diagram formed by the two innermost hexagons is identical, that is, a clipped version of the original ABC coordinate system, hence it is called a quadratic ABC coordinate system.

[0028] Step 5, with Figure 1 Reference voltage vector V ref =(v a,ref ,v b,ref ,v c,ref = (-0.8, 1.3, -0.5) * V dc / (n-1)(V dc Taking the DC bus voltage of the converter as an example, the reference voltage vector is first transformed from the original abc coordinate system to the quadratic abc coordinate system through matrix T to obtain the new reference vector O'S' = (-0.6, -0.1, 0.7) * V dc / (n-1), such as Figure 3 As shown. In this quadratic abc coordinate system, a new reference vector is synthesized using the three nearest vectors. The available three nearest vector switch states are (1,2,3), (2,2,3), and (2,3,3). When the three nearest vectors are transformed by the inverse transformation matrix T... inv When transformed back to the original abc coordinate system, the switch states are (-1,2,-1), (-1,1,0), and (0,1,-1). Adding a positive offset (n-1) / 2 = 2 to each switch state yields the final output switch states as (1,4,1), (1,3,2), and (2,3,1). It can be verified that the common-mode voltage generated by each switch state is zero. This quadratic abc coordinate system is well applicable to common arbitrary level converters.

[0029] It should be understood that the sequence number of each step in the embodiments of the present invention does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0030] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for eliminating common-mode voltage in multi-level SVPWM modulation based on a non-orthogonal coordinate system, characterized in that: Specifically, the following steps are included: Step 1: Perform coordinate transformation on the SVPWM switching vector using the following transformation matrix T: Transform the switch vector from the original abc coordinate system to a new coordinate system so that the coordinates of the transformed switch vector have a fractional form; Step 2: Divide the switching states in the new coordinate system into two categories: the first category is obtained by transforming the switching states that generate zero common-mode voltage in the original abc coordinate system; the second category is the remaining switching states; the desired output switching state is selected only from the switching states of the first category through subsequent transformations. Step 3: Set a real number for any switch state in the new coordinate system, so that the corresponding switch vector coordinates of the first type of switch state can be changed from the fractional form to the integer form after adding the real number, while the switch vector coordinates of the second type of switch state cannot be changed from the fractional form to the integer form after adding any real number. Step 4: Extract the first type of switch state corresponding to the switch vector coordinates that can be converted into integers in Step 3 in the new abc coordinate system, add them to one or more real numbers and convert them into switch states with values ​​between [0n-1] to simplify the spatial vector diagram, where n is the number of converter levels, and at the same time obtain a quadratic abc coordinate system; Step 5: After determining the available nearest three-vector switching state in the quadratic abc coordinate system based on the reference voltage vector, use the inverse matrix T of the transformation matrix T. inv Transform it into the original abc coordinate system as a switching state; add each switching state to a positive offset to obtain the final output switching state, which is used to synthesize a reference voltage in the original abc coordinate system.

2. The method as described in claim 1, characterized in that: The transformation matrix T mentioned in step one is non-full rank, and its inverse matrix cannot be directly obtained. By introducing the constraint that the sum of the phase voltages of the three-phase balanced system is zero, its inverse matrix can be obtained as follows:

3. The method as described in claim 2, characterized in that: In step five, the inverse matrix T is used. inv The nearest available three vectors are transformed into the switch state in the original abc coordinate system, so that its coordinate values ​​are in the range of [-(n-1) / 2(n-1) / 2]; the corresponding positive offset is set to (n-1) / 2, so that the final output switch state coordinate values ​​are in the range of [0n-1] and the generated common-mode voltages are all zero.

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