A control method and device of a motor, a motor and a storage medium

Abstract

The application discloses a motor control method and device, a motor and a storage medium. The method comprises the following steps: a vector control module of a driving unit of a motor generates a control signal by combining a given rotating speed value of the motor, a sampling rotating speed value of the motor and a sampling current value of the motor, so as to: output the control signal to a driving module, so that the driving module controls the on-off of a power switch tube in an inverter module under the control of the control signal, and realizes the control of the motor; wherein the vector control module takes FPGA as a control core and is loaded with a CORDIC algorithm. According to the scheme, the given rotating speed value of the motor, the sampling rotating speed value of the motor and the sampling current value of the motor are combined, and the target rotating speed set by an upper computer, that is, the given rotating speed value of the motor, so that the vector control module of the driving unit of the motor takes FPGA as the control core and adopts the CORDIC algorithm to control the motor, and the control effect of the motor is improved.

Description

Technical Field

[0001] This invention belongs to the field of servo motor vector control technology, specifically relating to a motor control method, device, motor, and storage medium, and more particularly to a control method, device, motor, and storage medium for a vector control system of a motor drive unit based on an FPGA asynchronous motor. Background Technology

[0002] Electric motors (such as asynchronous motors) have advantages such as simple structure, convenient manufacturing, use and maintenance, reliable operation, small size, and low cost, making them the first choice for most AC-driven machine tools. The energy flow and power output between the motor power unit and the energy source are controlled by the motor drive unit. The main control chip, as the core of the motor drive unit, processes sensor signals and motor rotor position signals according to the control strategy and outputs a pulse width modulation waveform. This waveform is amplified by the power drive circuit and then controls the conduction state of the power devices in the inverter circuit, thereby driving the motor to rotate.

[0003] In the relevant solutions, the chip selection scheme uses a Digital Signal Processor (DSP) as the control core, employing a control strategy of hardware and software co-design. However, while the vector control module of the motor drive unit uses a DSP as the control core, DSP-based control is easily affected by motor parameters, especially the rotor resistance, which can impact the control performance of the motor.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a motor control method, device, motor, and storage medium to address the problem in related solutions where the vector control module of the motor drive unit (such as an asynchronous motor) uses a DSP as the control core. However, the DSP-based control method is easily affected by motor parameters, especially the rotor resistance, which can impact the control effect. The invention aims to improve the motor control effect by combining the motor's reference current value, sampled current value, sampled speed value, and the target speed set by the host computer (i.e., the given speed value). This allows the vector control module of the motor drive unit to use an FPGA as the control core and employ the CORDIC algorithm for calculation.

[0006] This invention provides a method for controlling a motor, wherein the motor has a drive unit; the drive unit includes a communication unit and an inverter control unit; the inverter control unit includes an inverter module composed of power switching transistors, a drive module for driving the inverter module, and a vector control module for controlling the drive module; the vector control module uses an FPGA as its control core and is loaded with a CORDIC algorithm; the method for controlling the motor includes: after the motor is powered on and started, the vector control module acquires the motor's rotational speed value and records it as the sampled rotational speed value of the motor; acquiring the... The current value of the motor is recorded as the sampled current value of the motor; and the rotational speed value transmitted by the communication unit is recorded as the given rotational speed value of the motor; the given rotational speed value is the target rotational speed value issued by the host computer for adjusting the rotational speed of the motor; the vector control module, in combination with the given rotational speed value of the motor, the sampled rotational speed value of the motor, and the sampled current value of the motor, generates a control signal, and outputs the control signal to the drive module, so that the drive module controls the switching of the power switch in the inverter module under the control of the control signal, thereby realizing the control of the motor.

[0007] In some embodiments, the vector control module further includes a photoelectric encoder and a speed calculator; acquiring the motor's rotational speed value and recording it as the motor's sampled rotational speed value includes: receiving the motor's rotational speed signal sampled by the photoelectric encoder; calculating the motor's rotational speed signal using the speed calculator to obtain a rotational speed value corresponding to the motor's rotational speed signal, and recording it as the motor's sampled rotational speed value.

[0008] In some embodiments, the vector control module further includes a current detection module, an A / D converter, an FIR filter, and a Clark-Park transformation module; acquiring the current value of the motor, and recording it as the sampled current value of the motor, includes: receiving the current signal of the motor detected by the current detection module; performing A / D conversion on the current signal of the motor through the A / D converter, filtering it through the FIR filter, and then performing Clark-Park transformation on it using the CORDIC algorithm by the Clark-Park transformation module to obtain the current value corresponding to the current signal of the motor, and recording it as the sampled current value of the motor.

[0009] In some embodiments, the communication unit includes a CAN bus and a NIOS soft-core processor; the CAN bus and the NIOS soft-core processor are located between the host computer and the vector control module; acquiring the rotational speed value transmitted by the communication unit and recording it as the given rotational speed value of the motor includes: receiving a speed control signal sent by the user through the host computer via the CAN bus; the speed control signal is a signal used to adjust the rotational speed of the motor; and processing the speed control signal received through the CAN bus by the NIOS soft-core processor and outputting a rotational speed value corresponding to the speed control signal sent by the host computer, which is recorded as the given rotational speed value of the motor.

[0010] In some embodiments, the vector control module further includes a first comparator, a second comparator, a third comparator, a first PI controller, a second PI controller, a third PI controller, a Park inverse converter module, and an SVPWM module. The vector control module, in conjunction with a given motor speed value, a sampled motor speed value, and a sampled motor current value, generates a control signal, including: outputting a first current value by passing the given motor speed value and the sampled motor speed value through the first comparator and the first PI controller; outputting a first voltage value by passing the first current value and the sampled motor current value through the second PI controller; obtaining a second voltage value by passing a pre-set reference current value and the sampled motor current value through the third comparator and the third PI controller; and outputting a control signal by passing the first voltage value and the second voltage value through the Park inverse converter module and the SVPWM module.

[0011] In some embodiments, the method further includes: during the operation of the motor, the vector control module acquires the operating parameters of the motor; and the vector control module uploads the operating parameters of the motor to the host computer through the communication unit, so as to enable the host computer to monitor the operating parameters of the motor.

[0012] In conjunction with the above method, another aspect of the present invention provides a motor control device, wherein the motor has a drive unit; the drive unit includes: a communication unit and an inverter control unit; the inverter control unit includes: an inverter module composed of power switching transistors, a drive module for driving the inverter module, and a vector control module for controlling the drive module; the vector control module uses an FPGA as its control core and is loaded with a CORDIC algorithm; the motor control device includes: an acquisition unit configured to, after the motor is powered on and started, cause the vector control module to acquire the motor's rotational speed value, which is recorded as the motor's sample value. The system acquires the following parameters: a rotational speed value; a current value of the motor, recorded as the sampled current value of the motor; and a rotational speed value transmitted by the communication unit, recorded as the given rotational speed value of the motor. The given rotational speed value is a target rotational speed value issued by the host computer for adjusting the rotational speed of the motor. The control unit is configured to enable the vector control module to generate a control signal by combining the given rotational speed value of the motor, the sampled rotational speed value of the motor, and the sampled current value of the motor, and to output the control signal to the drive module, so that the drive module controls the switching of the power switch in the inverter module under the control of the control signal, thereby controlling the motor.

[0013] In some embodiments, the vector control module further includes a photoelectric encoder and a speed calculator; the acquisition unit acquires the rotational speed value of the motor and records it as the sampled rotational speed value of the motor, including: receiving the rotational speed signal of the motor sampled by the photoelectric encoder; calculating the rotational speed signal of the motor through the speed calculator to obtain the rotational speed value corresponding to the rotational speed signal of the motor, and recording it as the sampled rotational speed value of the motor.

[0014] In some embodiments, the vector control module further includes a current detection module, an A / D converter, an FIR filter, and a Clark-Park transformation module; the acquisition unit acquires the current value of the motor and records it as the sampled current value of the motor, including: receiving the current signal of the motor detected by the current detection module; performing A / D conversion on the current signal of the motor through the A / D converter, filtering it through the FIR filter, and then performing Clark-Park transformation on it using the CORDIC algorithm through the Clark-Park transformation module to obtain the current value corresponding to the current signal of the motor, which is recorded as the sampled current value of the motor.

[0015] In some embodiments, the communication unit includes a CAN bus and a NIOS soft-core processor; the CAN bus and the NIOS soft-core processor are located between the host computer and the vector control module; the acquisition unit acquires the rotational speed value transmitted by the communication unit and records it as the given rotational speed value of the motor, including: receiving a speed control signal sent by the user through the host computer via the CAN bus; the speed control signal is a signal used to adjust the rotational speed of the motor; and processing the speed control signal received through the CAN bus via the NIOS soft-core processor and outputting a rotational speed value corresponding to the speed control signal sent by the host computer, which is recorded as the given rotational speed value of the motor.

[0016] In some embodiments, the vector control module further includes a first comparator, a second comparator, a third comparator, a first PI controller, a second PI controller, a third PI controller, a Park inverse converter module, and an SVPWM module. The acquisition unit enables the vector control module to generate a control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, including: outputting a first current value by passing the given speed value of the motor and the sampled speed value of the motor through the first comparator and the first PI controller; outputting a first voltage value by passing the first current value and the sampled current value of the motor through the second PI controller; obtaining a second voltage value by passing a preset reference current value and the sampled current value of the motor through the third comparator and the third PI controller; and outputting a control signal by passing the first voltage value and the second voltage value through the Park inverse converter module and the SVPWM module.

[0017] In some embodiments, the system further includes: the acquisition unit is configured to enable the vector control module to acquire the operating parameters of the motor during the operation of the motor; the control unit is further configured to enable the vector control module to upload the operating parameters of the motor to a host computer through the communication unit, so as to enable the host computer to monitor the operating parameters of the motor.

[0018] In conjunction with the above-described device, the present invention further provides a motor, comprising: the motor control device described above.

[0019] In conjunction with the above method, the present invention further provides a storage medium comprising a stored program, wherein, when the program is executed, the device on which the storage medium is located executes the motor control method described above.

[0020] Therefore, the solution of this invention, through the vector control system of the motor drive unit, sets up a CAN bus, a CPU control module with a NIOS soft-core processor (such as a NIOS II soft-core processor), and a vector control module with an FPGA as the control core and incorporating the CORDIC algorithm; when controlling the vector control system of the motor drive unit, the motor current signal is collected, filtered, and then subjected to Clark-Park transformation to obtain a reference value, which is then transmitted to the vector control module; the motor speed signal is collected, and the speed value is calculated to obtain the motor speed value, which is then transmitted to the vector control module; after receiving the user's control signal through the CAN bus, the received user's control signal is transmitted to the vector control module through the NIOS soft-core processor; in the vector control module, an outer loop P is performed based on the user's control signal and the reference value. After I-control, the input is fed into the Park inverse converter module. The set value and reference value are subjected to inner-loop PI control and then fed into the Park inverse converter module. After Park inverse conversion, the voltage value is obtained. This voltage value is then passed through the SVPWM module and output as a control signal to the drive unit. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit in the motor drive unit to drive the motor. Thus, by enabling the vector control module of the motor drive unit to use the FPGA as the control core and the CORDIC algorithm for calculation, and using the CAN bus and NIOS soft-core processor to receive the target speed set by the host computer, i.e., the given speed value of the motor, the vector control module determines the drive signal of the drive unit to control the motor based on the target speed, reference current value, and the sampled current value and sampled speed value of the motor, thereby improving the control effect of the motor.

[0021] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention.

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating an embodiment of the motor control method of the present invention;

[0024] Figure 2 This is a flowchart illustrating an embodiment of the method of the present invention for obtaining the rotational speed value of the motor and recording it as the sampled rotational speed value of the motor;

[0025] Figure 3 This is a schematic flowchart of an embodiment of the method of the present invention for obtaining the current value of the motor and recording it as the sampled current value of the motor;

[0026] Figure 4This is a schematic flowchart of an embodiment of the method of the present invention for obtaining the rotational speed value transmitted by the communication unit and recording it as the given rotational speed value of the motor;

[0027] Figure 5 This is a flowchart illustrating an embodiment of the method of the present invention for generating a control signal by combining a given speed value of the motor, a sampled speed value of the motor, and a sampled current value of the motor.

[0028] Figure 6 This is a flowchart illustrating an embodiment of the method of the present invention that communicates with a host computer via a communication unit;

[0029] Figure 7 This is a schematic diagram of the structure of an embodiment of the motor control device of the present invention;

[0030] Figure 8 A schematic diagram of the structure of an embodiment of a vector control system for a motor drive unit;

[0031] Figure 9 A schematic diagram of the control flow of an embodiment of a vector control system for a motor drive unit;

[0032] Figure 10 A schematic diagram illustrating the logical functions of the CAN bus and the NIOS II soft-core processor;

[0033] Figure 11 This diagram illustrates the relationship between the motor, control unit, drive unit, detection unit, and user.

[0034] Referring to the accompanying drawings, the reference numerals in the embodiments of the present invention are as follows:

[0035] 102 - Acquisition unit; 104 - Control unit. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0037] Considering that in related solutions, the vector control module of the motor drive unit (such as an asynchronous motor) uses a DSP as the control core, but DSP-based control is easily affected by motor parameters, especially the rotor resistance, which can affect the control effect. For example, in multi-motor control applications, a single DSP is no longer sufficient to meet design requirements; furthermore, DSP-based solutions are easily affected by motor parameters, especially rotor resistance, making it difficult to meet the requirements of practical applications.

[0038] The motor's drive unit is an AC servo controller. However, AC servo controllers are complex, involving numerous intricate calculations, including arctangent calculations for direct decoding of the resolver, sine and cosine calculations for Clark-Park transformation, and coordinate system transformations required for sector determination in Space Vector Pulse Width Modulation (SVPWM). These calculations are typically performed using lookup tables in DSPs. However, in applications requiring high precision, speed, and reliability, precise rotor position measurement and complex decoupling calculations are necessary. Commonly used DSP-based solutions are easily affected by motor parameters, especially rotor resistance, making it difficult to meet practical requirements.

[0039] Furthermore, DSPs are suitable for multi-condition processes at lower sampling rates, while FPGAs are suitable for system development with fixed tasks or repetitive situations at high sampling rates. In servo systems, where current sampling frequency is high and control logic in multi-motor control systems is repetitive, FPGAs are more suitable. Additionally, due to the slow computation speed and long development cycle of single-chip DSPs, this approach must be abandoned in some high-precision and high-stability applications. Compared to DSP control, FPGA control has the following three characteristics: 1. FPGAs process data using pure hardware, resulting in faster response times and higher precision control; 2. FPGA code is modular, enhancing the scalability of the motor drive system while significantly reducing costs; 3. Due to its regular internal logic block array and abundant linear resources, FPGA is particularly suitable for implementing fine-grained and highly parallel FIR filters, offering higher parallelism and scalability compared to general-purpose DSP chips dominated by serial computation.

[0040] Therefore, the present invention proposes a motor control method, specifically a vector control method for the drive unit of an asynchronous motor based on an FPGA. Based on a drive system using a three-phase asynchronous AC motor as the controlled object, IGBTs as the power unit, and vector control as the control strategy, the method employs an FPGA as the control core. The CORDIC algorithm is introduced to optimize the trigonometric function operations involved in the logic unit of the control strategy. FIR filtering of the A / D generated signals is added, improving the accuracy and reliability of the vector control system's control of the motor drive unit. Furthermore, a NIOS II soft-core processor and a Controller Area Network (CAN) IP core are incorporated. The CAN bus receives control signals from the PC and then passes them to the CPU for execution in the logic control section of the control strategy. This avoids the susceptibility of DSP-based control methods to the influence of motor parameters, especially the rotor resistance, thus improving the motor control effect.

[0041] Some solutions offer FPGA (Field-Programmable Gate Array)-based servo controllers, where the FPGA servo controller is composed of an FPGA chip, including an encoder module, a current sampling module, a position loop control module, a speed loop control module, and a current loop control module. However, this solution does not consider data interaction between the user and the servo controller, and cannot perform real-time data reading or writing via a PC. Servo drivers require setting servo parameters to control the motor, and these parameters are affected and change under different operating conditions, requiring timely adjustments. Without real-time parameter interaction, control parameters cannot be adjusted, affecting control performance. Simultaneously, users should be able to monitor motor parameter status in real time, such as motor speed and drive current.

[0042] The solution of this invention uses a NIOS II processor (i.e., a NIOS II series soft-core processor) to handle communication with a host PC. It receives data from the host PC via an interface and simultaneously reads the motor's parameter register values, sending them to the host PC for display. This allows users to monitor motor operating parameters on the PC, such as motor current commands, current feedback, speed commands, speed feedback, position commands, and position feedback. This improves the efficiency of technicians in adjusting motor parameters and enhances the motor's control performance.

[0043] Some solutions offer a DSP+FPGA-based servo system for multi-axis control of industrial robots. The FPGA acquires encoder data and sends it to the DSP via the EMIF (External Memory Interface). The DSP calculates the position control PI loop and speed control PI loop to obtain the set current, which is then sent back to the FPGA via the EMIF interface. However, this solution, due to the use of a DSP processor, results in a long delay between current sampling and pulse width modulation duty cycle updates. This leads to low control accuracy and slow dynamic response in the entire servo control system, and in severe cases, instability. Furthermore, the different command execution logic of the processors results in different command execution speeds; FPGAs are faster, while DSPs are slower.

[0044] Some solutions offer a control system for a multi-axis AC servo motor based on an FPGA chip. This control system includes a multi-axis AC servo motor, a trajectory generator, a trajectory and servo control module, a motor adjustment and drive module, and a three-phase inverter. However, this solution uses ROM (Read-Only Memory) lookup tables and polynomial approximation methods to calculate trigonometric functions, inverse trigonometric functions, hyperbolic functions, and other transcendental functions, consuming excessive logic resources of the FPGA chip. Since the number of logic resources on an FPGA chip is limited, it's best to use as few logic resources as possible to achieve the same function, leaving the remaining resources for other functions. In contrast, the solution of this invention, using the CORDIC algorithm (i.e., coordinate rotation digital calculation method), has the significant advantages of not requiring hardware multipliers, using pipelines, and being iterative. Furthermore, its calculation method conforms to the modular characteristics of hardware algorithms, thus facilitating implementation in an FPGA.

[0045] According to an embodiment of the present invention, a method for controlling a motor is provided, such as... Figure 1 The diagram shows a flowchart of an embodiment of the method of the present invention. The motor has a drive unit, such as a motor drive unit; the drive unit includes: a communication unit and an inverter control unit 104; the inverter control unit 104 includes: an inverter module composed of power switching transistors, a drive module for driving the inverter module, and a vector control module for controlling the drive module; the vector control module uses an FPGA as its control core and is loaded with a CORDIC algorithm. Specifically, Figure 8 This is a schematic diagram of an embodiment of a vector control system for a motor drive unit. Figure 8As shown, the vector control system of the motor drive unit mainly includes the following hardware platform: a rectifier module, a capacitor filter module, and an IGBT-based inverter unit, sequentially arranged between the AC power supply and the motor (e.g., a three-phase AC asynchronous motor). At the output of the IGBT-based inverter unit, an isolation transformer, a fast recovery diode module, a current detection module, a voltage sampling module, a control circuit, and a gate drive module are sequentially arranged. The output of the gate drive module is connected to the control terminal of the IGBT-based inverter unit. The control circuit is specifically an FPGA control module. The inverter module is as follows... Figure 8 The inverter unit based on IGBT shown has a drive module as follows: Figure 8 The gate drive module and vector control module shown are as follows: Figure 8 The control circuit shown.

[0046] The three-phase AC asynchronous motor serves as the power output device. Simultaneously, the motor transmits pulses to the FPGA control module via an installed photoelectric encoder. The FPGA control module is responsible for generating the logic signals required to control the motor and receiving commands from the user. Under the control of the FPGA control module's logic signals, the drive module (i.e., the gate drive module) outputs the corresponding voltage to the power inverter module to control the IGBTs' switching on and off. The power inverter module is a three-phase inverter unit composed of six IGBTs (i.e., an IGBT-based inverter unit). Driven by the drive module (i.e., the gate drive module), it follows the FPGA control module's logic signals to output the corresponding SVPWM wave. The voltage and current acquisition module (i.e., the current detection module and voltage sampling module) is responsible for acquiring the motor's current value and calculating the corresponding voltage value, which is then converted by an A / D converter and sent to the FPGA control module.

[0047] First, the voltage and current acquisition module acquires the current and voltage signals of the three-phase asynchronous motor. The analog signals acquired by the module are converted into digital signals by an A / D converter and sent to the FPGA control module. Then, the speed signal is acquired, and the physical quantity of the speed value is calculated. Specifically, the FPGA control module, based on the motor's current and speed signals and the user-sent adjustment signals, uses a vector control algorithm to obtain a control signal and outputs this control signal to the motor's drive unit. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit within the motor's drive unit.

[0048] In the solution of the present invention, such as Figure 1 As shown, the motor control method includes steps S110 to S120.

[0049] In step S110, after the motor is powered on and started, the vector control module acquires the motor's rotational speed value, denoted as the sampled rotational speed value; acquires the motor's current value, denoted as the sampled current value; and acquires the rotational speed value transmitted by the communication unit, denoted as the given rotational speed value. The given rotational speed value is a target rotational speed value issued by the host computer for adjusting the motor's rotational speed. The given rotational speed value may be, for example, the rotational speed value corresponding to a user-transmitted signal.

[0050] In some implementations, the vector control module also includes a photoelectric encoder and a speed calculator.

[0051] For details on the process of obtaining the motor speed value in step S110 and recording it as the sampled speed value of the motor, please refer to the following exemplary description.

[0052] The following is combined Figure 2 The schematic diagram shows an embodiment of the method of the present invention for obtaining the speed value of the motor and recording it as the sampled speed value of the motor. The specific process of obtaining the speed value of the motor and recording it as the sampled speed value of the motor in step S110 is further explained, including steps S210 to S220.

[0053] Step S210: Receive the motor speed signal sampled by the photoelectric encoder.

[0054] Step S220: The speed calculator calculates the speed signal of the motor to obtain the speed value corresponding to the speed signal of the motor, which is recorded as the sampled speed value of the motor.

[0055] Specifically, Figure 9 This is a schematic diagram of the control flow of an embodiment of a vector control system for a motor drive unit. Figure 9 As shown, the control flow of the vector control system for the motor drive unit includes:

[0056] Step 11: The speed signal is acquired by using a photoelectric encoder and the FPGA control module's equal-precision acquisition method. After recording the number of pulses, the physical quantity of the required speed value is calculated according to the corresponding formula.

[0057] Step 12: Input the control signal sent by the user (i.e., the signal transmitted by the user) and the calculated speed value into the outer loop PI regulator, compare them with the current value of the Clark-Park transformation, and input them into the inner loop PI.

[0058] In some embodiments, the vector control module further includes a current detection module, an A / D converter, an FIR filter, and a Clark-Park converter module.

[0059] For details on the process of obtaining the current value of the motor in step S110 and recording it as the sampled current value of the motor, please refer to the following exemplary description.

[0060] The following is combined with Figure 3 The schematic diagram shown is a flowchart of an embodiment of the method of the present invention for obtaining the current value of the motor and recording it as the sampled current value of the motor. The specific process of obtaining the current value of the motor and recording it as the sampled current value of the motor in step S110 is further explained, including steps S310 and S320.

[0061] Step S310: Receive the current signal of the motor detected by the current detection module.

[0062] Step S320: The current signal of the motor is converted by the A / D converter, filtered by the FIR filter, and then transformed by the Clark-Park transformation module using the CORDIC algorithm to obtain the current value corresponding to the current signal of the motor, which is recorded as the sampled current value of the motor.

[0063] Specifically, such as Figure 9 As shown, the control flow of the vector control system for the motor drive unit also includes:

[0064] In step 11, the motor current signal acquired by a current detection module such as a Hall sensor is filtered, and the control signal sent by the user is transmitted to the vector control module (i.e., the FPGA control module). The FIR filter used for filtering ensures strict linear phase frequency characteristics while maintaining arbitrary amplitude-frequency characteristics, and its unit sample response is finite, thus making the filter a stable system.

[0065] In step 12, the user-sent control signal (i.e., the user-transmitted signal) and the calculated speed value are input to the outer loop PI regulator, compared with the current value obtained from the Clark-Park transformation, and then input to the inner loop PI regulator. The system setpoint is also compared with another value obtained from the Clark-Park transformation and input to the inner loop PI regulator. The above two sets of results are used to obtain the voltage value through inverse Park transformation. The voltage value is then calculated and processed through SVPWM to obtain the control signal. The control signal is output to the motor drive unit, specifically to the gate drive module of the IGBT-based inverter unit in the motor drive unit.

[0066] In some embodiments, the communication unit includes a CAN bus and a NIOS soft-core processor; the CAN bus and the NIOS soft-core processor are located between the host computer and the vector control module.

[0067] For the specific process of obtaining the rotational speed value transmitted by the communication unit in step S110 and recording it as the given rotational speed value of the motor, please refer to the following exemplary description.

[0068] The following is combined Figure 4 The schematic diagram shows an embodiment of the method of the present invention in which the rotational speed value transmitted by the communication unit is obtained and recorded as the given rotational speed value of the motor. The specific process of obtaining the rotational speed value transmitted by the communication unit and recording it as the given rotational speed value of the motor in step S110 is further explained, including steps S410 to S420.

[0069] Step S410: Receive a speed control signal sent by the user via the host computer through the CAN bus; the speed control signal is used to adjust the speed of the motor.

[0070] Step S420: The NIOS soft-core processor processes the speed control signal received via the CAN bus and outputs the speed value corresponding to the speed control signal sent by the host computer, which is recorded as the given speed value of the motor.

[0071] Specifically, Figure 10 This is a schematic diagram illustrating the logical functions of the CAN bus and the NIOS II soft-core processor. Figure 10 As shown, the present invention also incorporates a NIOS II soft-core processor and a Controller Area Network (CAN) IP core. The CAN bus receives control signals from the PC and then passes them to the logic control section (i.e., the FPGA control module) for execution via the CPU loaded with the NIOS II soft-core processor. This achieves the design of a vector control system for the motor drive unit. The CAN bus module receives adjustment signals sent by the user, and the NIOS soft-core processor transmits these signals to the vector control module (i.e., the FPGA control module). The NIOS II soft-core processor is an IP core, essentially part of the software program, while the CPU is a hardware processor, and the software program resides within the CPU hardware processor.

[0072] See Figure 10 In the example shown, the CAN bus module is used to receive the adjustment signal sent by the user. The NIOS soft-core processor is used to transmit the adjustment signal sent by the user to the vector control module (i.e., the FPGA control module). Then, the vector control module is used to compare the adjustment signal sent by the user with the calculated speed value and input it to the outer loop PI regulator. This value, together with the system set value, is compared with the reference value obtained by filtering and Clark-Park transformation of the current value. Then, it is input to the inner loop PI regulator, and the voltage value is obtained by inverse Park transformation.

[0073] In step S120, the vector control module generates a control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, and outputs the control signal to the drive module so that the drive module controls the switching of the power switch in the inverter module under the control of the control signal, thereby controlling the motor.

[0074] The present invention provides a control scheme for a vector control system of a motor drive unit of an asynchronous motor based on an FPGA. This vector control system of the motor drive unit of the asynchronous motor based on an FPGA is a drive system that uses a three-phase asynchronous AC motor as the controlled object, IGBTs as the power unit, and vector control as the control strategy. It uses an FPGA as the control core, introduces the CORDIC algorithm to optimize the trigonometric function operations involved in the logic unit of the control strategy, and adds FIR filtering to the A / D generated signal, improving the accuracy and reliability of the vector control system for controlling the motor drive unit. It also incorporates a NIOS II soft-core processor and a Controller Area Network (CAN) IP core, using the CAN bus to receive control signals from the PC and then pass them to the CPU for execution by the logic control part of the control strategy. This avoids the susceptibility of DSP-based control methods to the influence of motor parameters, especially the rotor resistance of the motor, thus improving the control effect on the motor.

[0075] In this context, an IP core refers to a program that handles the Controller Area Network (CAN) bus. Specifically, it's a program that receives control signals from the PC via the CAN bus. Encapsulating this program into an IP core—essentially saving it as a specially formatted file—creates a functional IP core. The NIOS II soft-core processor is specifically designed to process these software IP cores. Therefore, encapsulating a specific program into a CAN bus function IP core requires initial software processing by the NIOS II soft-core processor before being handed over to the CPU for final processing.

[0076] In some implementations, the vector control module further includes a first comparator, a second comparator, a third comparator, a first PI controller, a second PI controller, a third PI controller, a Park inverse converter module, and an SVPWM module.

[0077] The specific process of generating a control signal by the vector control module in step S120, which combines the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, is illustrated in the following exemplary description.

[0078] The following is combined Figure 5 The schematic diagram shown is an embodiment of the method of the present invention for generating a control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor. It further illustrates the specific process of generating the control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor in step S120, including steps S510 to S540.

[0079] In step S510, the given speed value of the motor and the sampled speed value of the motor are passed through the first comparator and the first PI controller to output a first current value.

[0080] In step S520, the first current value and the sampled current value of the motor are passed through the second PI controller to output a first voltage value.

[0081] Step S530: The preset reference current value and the sampled current value of the motor are passed through the third comparator and the third PI controller to obtain the second voltage value. The preset reference current value is 0. In motor control, the control current is divided into two: the first current value is the q-axis circuit Iq, which is output after passing through the first comparator and the first PI controller based on the given speed value and the sampled speed value of the motor. The second current value is the d-axis current Id, which is initially set to 0 and used as the reference current value.

[0082] Step S540: The first voltage value and the second voltage value are processed by the Park inverse converter module and the SVPWM module to output a control signal.

[0083] Specifically, in Figure 9In the example shown, the control signal sent by the user (i.e., the user-transmitted signal) is input to the first input terminal of the first comparator; the photoelectric encoder collects the speed signal from the three-phase AC asynchronous motor M, and the speed signal, after being processed by the speed calculator, outputs the speed value corresponding to the speed regulation signal sent by the host computer to the second input terminal of the first comparator. The output terminal of the first comparator outputs the first PI processing result after passing through the first PI module. The first PI processing result is input to the first input terminal of the second comparator; the motor current signal detected by the current detection module is transformed by Clark-Park to obtain the current value corresponding to the motor current signal, which is input to the second input terminal of the second comparator. The output terminal of the second comparator outputs the second PI processing result after passing through the second PI module; the second PI processing result is input to the first input terminal of the Park inverse transform module. The system setting value is input to the first input terminal of the third comparator; the motor current signal detected by the current detection module is transformed by Clark-Park to obtain the current value corresponding to the motor current signal, which is also input to the second input terminal of the third comparator. The output terminal of the third comparator outputs the third PI processing result after passing through the third PI module. The third PI processing result is input to the second input terminal of the Park inverse transform module. The first output terminal and the second output terminal of the Park inverter module output control signals to the drive unit after passing through the SVPWM module. Specifically, the control signals are output to the gate drive module of the IGBT-based inverter unit in the motor drive unit.

[0084] In this invention, the NIOS II processor handles the communication module with the host PC and the CORDIC algorithm for processing trigonometric functions. Using the CORDIC algorithm (i.e., the coordinate rotation digital calculation method) offers significant advantages, including eliminating the need for hardware multipliers, enabling pipelined processing, and allowing for iterative iteration. Furthermore, its computational method aligns with the modular characteristics of hardware algorithms, facilitating implementation in an FPGA.

[0085] The core of vector control algorithms is to transform an AC motor into a DC motor through model conversion for control. To achieve this, the physical parameters of the AC motor need to be converted into those of the DC motor. Physically speaking, this requires transforming the three-phase stationary axis ABC coordinate system into a two-phase synchronous rotating axis MT coordinate system. The Clark and Park transformations are precisely the transformations used to achieve this goal.

[0086] In the actual performance of Clarke and Park transforms, the scheme of this invention adopts the CORDIC algorithm. Its core idea is to divide the rotation angle into several minimal angles and use an iterative method to approximate the desired angle. Let vector (X...) i Y i The rotation angle θ becomes a vector (X).j Y j ), which can be represented in matrix form as:

[0087] .

[0088] Here, we use an iterative approach to decompose a rotation angle into n minimum angles. The relationship between adjacent minimum angles can be expressed as:

[0089] .

[0090] After analyzing the vector (X) i Y i Further constraints on the rotation angle θ, including the unrotated angle Z0, and considering the limit approximation case with multiple iterations, when calculating the coordinate transformation, the input is:

[0091] .

[0092] Where X0, Y0, and Z0 are the initial input vector coordinates, and Z0 is specifically the initial input angle.

[0093] After multiple iterations, the final output is obtained:

[0094] .

[0095] Where K is the infinite approximation value of cosθn after countless iterations.

[0096] Compared to related schemes that use ROM lookup table methods and polynomial approximation methods to calculate trigonometric functions, inverse trigonometric functions, hyperbolic functions, and other transcendental functions, the CORDIC algorithm has significant advantages such as not requiring hardware multipliers, using pipelined methods, and being able to iterate cyclically. Furthermore, its computational method conforms to the modular characteristics of hardware algorithms, thus facilitating its implementation in FPGAs.

[0097] In some embodiments, the motor control method of the present invention further includes: a process of communicating with a host computer via a communication unit.

[0098] The following is combined Figure 6 The flowchart shown is a schematic diagram of an embodiment of the method of the present invention in which communication is performed between the communication unit and the host computer. The specific process of communication between the communication unit and the host computer is further explained, including steps S610 to S620.

[0099] Step S610: During the operation of the motor, the vector control module acquires the operating parameters of the motor.

[0100] In step S620, the vector control module uploads the motor's operating parameters to the host computer via the communication unit, so that the host computer can monitor the motor's operating parameters.

[0101] Specifically, Figure 11 This diagram illustrates the relationship between the motor, control unit 104, drive unit, detection unit, and user. In the present invention, the relationship between the three-phase asynchronous AC motor, drive unit, detection unit, control unit 104, and user interface is as follows: Figure 11 As shown. The detection unit is used to collect the current, voltage, and speed signals of the motor; the FPGA control unit 104 is used to obtain a control signal based on the current, voltage, and speed signals of the motor, combined with the adjustment signal sent by the user, using a vector control algorithm, and outputs the control signal to the drive unit, specifically to the gate drive module of the IGBT-based inverter unit in the motor drive unit; the motor drive unit is used to drive the motor to work according to the control signal, wherein the motor is connected to the detection unit and the drive unit respectively, and the FPGA control unit 104 is connected to the detection unit and the drive unit respectively.

[0102] In the present invention, the above embodiments are for a specific asynchronous motor. When the vector control system of the motor drive unit adopts a synchronous motor, the same control system can also be used.

[0103] In this invention, the CORDIC algorithm is introduced to optimize trigonometric function operations, and an IP core and a soft-core processor are added for communication with the PC. The CORDIC algorithm optimizes the trigonometric function operations involved in the logic unit of the control strategy and incorporates FIR filtering for the A / D generated signals, improving the accuracy and reliability of the vector control system for the motor drive unit's control. The NIOSII processor handles communication with the host PC, allowing parameters to be adjusted according to the application, expanding the applicability and enhancing the competitiveness of the servo motor in the market. In this invention, the NIOSII processor (i.e., the NIOSII series soft-core processor) handles communication with the host PC, receiving data from the host computer via an interface and simultaneously reading the motor's parameter register values, sending them to the host PC for display. This allows users to monitor motor operating parameters on the PC, such as motor current commands, current feedback, speed commands, speed feedback, position commands, and position feedback, improving the efficiency of technicians in adjusting motor parameters and enhancing the motor's control effect.

[0104] The technical solution of this embodiment involves setting up a CAN bus, a CPU control module with a NIOS soft-core processor (such as a NIOS II soft-core processor), and a vector control module with an FPGA as the control core and incorporating the CORDIC algorithm in the vector control system of the motor drive unit. When controlling the vector control system of the motor drive unit, the motor current signal is acquired, filtered, and then subjected to Clark-Park transformation to obtain a reference value, which is then transmitted to the vector control module. The motor speed signal is acquired, and the speed value is calculated to obtain the motor speed value, which is then transmitted to the vector control module. After receiving the user's control signal via the CAN bus, the NIOS soft-core processor transmits the received user's control signal to the vector control module. In the vector control module, an outer loop is performed based on the user's control signal and the reference value. After PI control, the input is fed into the Park inverse converter module. The set value and reference value are subjected to inner-loop PI control and then fed into the Park inverse converter module. After Park inverse conversion, the voltage value is obtained. This voltage value is then passed through the SVPWM module and output as a control signal to the drive unit. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit in the motor drive unit to drive the motor. Thus, by enabling the vector control module of the motor drive unit to use the FPGA as the control core and the CORDIC algorithm for calculation, and by using the CAN bus and NIOS soft-core processor to receive the target speed set by the host computer, i.e., the given speed value of the motor, the vector control module determines the drive signal of the drive unit to control the motor based on the target speed, the reference current value, and the sampled current and speed values ​​of the motor, thereby improving the control effect of the motor.

[0105] According to an embodiment of the present invention, a motor control device corresponding to the motor control method is also provided. See also Figure 7 The diagram shows a structural schematic of an embodiment of the device of the present invention. The motor has a drive unit, such as a motor drive unit; the drive unit includes: a communication unit and an inverter control unit 104; the inverter control unit 104 includes: an inverter module composed of power switching transistors, a drive module for driving the inverter module, and a vector control module for controlling the drive module; the vector control module uses an FPGA as its control core and is loaded with a CORDIC algorithm. Specifically, Figure 8 This is a schematic diagram of one embodiment of a vector control system for a motor drive unit. Figure 8As shown, the vector control system of the motor drive unit mainly includes the following hardware platform: a rectifier module, a capacitor filter module, and an IGBT-based inverter unit, sequentially arranged between the AC power supply and the motor (e.g., a three-phase AC asynchronous motor). At the output of the IGBT-based inverter unit, an isolation transformer, a fast recovery diode module, a current detection module, a voltage sampling module, a control circuit, and a gate drive module are sequentially arranged. The output of the gate drive module is connected to the control terminal of the IGBT-based inverter unit. The control circuit is specifically an FPGA control module. The inverter module is as follows... Figure 8 The inverter unit based on IGBT shown has a drive module as follows: Figure 8 The gate drive module and vector control module shown are as follows: Figure 8 The control circuit shown.

[0106] The three-phase AC asynchronous motor serves as the power output device. Simultaneously, the motor transmits pulses to the FPGA control module via an installed photoelectric encoder. The FPGA control module is responsible for generating the logic signals required to control the motor and receiving commands from the user. Under the control of the FPGA control module's logic signals, the drive module (i.e., the gate drive module) outputs the corresponding voltage to the power inverter module to control the IGBTs' switching on and off. The power inverter module is a three-phase inverter unit composed of six IGBTs (i.e., an IGBT-based inverter unit). Driven by the drive module (i.e., the gate drive module), it follows the FPGA control module's logic signals to output the corresponding SVPWM wave. The voltage and current acquisition module (i.e., the current detection module and voltage sampling module) is responsible for acquiring the motor's current value and calculating the corresponding voltage value, which is then converted by an A / D converter and sent to the FPGA control module.

[0107] First, the voltage and current acquisition module acquires the current and voltage signals of the three-phase asynchronous motor. The analog signals acquired by the module are converted into digital signals by an A / D converter and sent to the FPGA control module. Then, the speed signal is acquired, and the physical quantity of the speed value is calculated. Specifically, the FPGA control module, based on the motor's current and speed signals and the user-sent adjustment signals, uses a vector control algorithm to obtain a control signal and outputs this control signal to the motor's drive unit. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit within the motor's drive unit.

[0108] In the solution of the present invention, such as Figure 7 As shown, the motor control device includes: an acquisition unit 102 and a control unit 104.

[0109] The acquisition unit 102 is configured to, after the motor is powered on and started, enable the vector control module to acquire the motor's rotational speed value, denoted as the sampled rotational speed value; acquire the motor's current value, denoted as the sampled current value; and acquire the rotational speed value transmitted by the communication unit, denoted as the given rotational speed value. The given rotational speed value is a target rotational speed value issued by the host computer for adjusting the motor's rotational speed. The given rotational speed value may be, for example, the rotational speed value corresponding to a user-transmitted signal. For the specific functions and processing of the acquisition unit 102, please refer to step S110.

[0110] In some implementations, the vector control module also includes a photoelectric encoder and a speed calculator.

[0111] The acquisition unit 102 acquires the rotational speed value of the motor, which is recorded as the sampled rotational speed value of the motor, including:

[0112] The acquisition unit 102 is specifically configured to receive the motor speed signal sampled by the photoelectric encoder. The specific functions and processing of the acquisition unit 102 are further described in step S210.

[0113] The acquisition unit 102 is specifically configured to calculate the motor speed signal using the speed calculator to obtain a speed value corresponding to the motor speed signal, which is recorded as the sampled speed value of the motor. The specific functions and processing of this acquisition unit 102 are further described in step S220.

[0114] Specifically, Figure 9 This is a schematic diagram of the control flow of an embodiment of a vector control system for a motor drive unit. Figure 9 As shown, the control flow of the vector control system for the motor drive unit includes:

[0115] Step 11: The speed signal is acquired by using a photoelectric encoder and the FPGA control module's equal-precision acquisition method. After recording the number of pulses, the physical quantity of the required speed value is calculated according to the corresponding formula.

[0116] Step 12: Input the control signal sent by the user (i.e., the signal transmitted by the user) and the calculated speed value into the outer loop PI regulator, compare them with the current value of the Clark-Park transformation, and input them into the inner loop PI.

[0117] In some embodiments, the vector control module further includes a current detection module, an A / D converter, an FIR filter, and a Clark-Park converter module.

[0118] The acquisition unit 102 acquires the current value of the motor, which is recorded as the sampled current value of the motor, including:

[0119] The acquisition unit 102 is specifically configured to receive the current signal of the motor detected by the current detection module. The specific functions and processing of the acquisition unit 102 are further described in step S310.

[0120] The acquisition unit 102 is specifically configured to convert the motor current signal via the A / D converter, then filter it via the FIR filter, and finally perform a Clark-Park transform using the CORDIC algorithm via the Clark-Park transform module to obtain the current value corresponding to the motor current signal, which is recorded as the sampled current value of the motor. The specific functions and processing of this acquisition unit 102 are further described in step S320.

[0121] Specifically, such as Figure 9 As shown, the control flow of the vector control system for the motor drive unit also includes:

[0122] In step 11, the motor current signal acquired by a current detection module such as a Hall sensor is filtered, and the control signal sent by the user is transmitted to the vector control module (i.e., the FPGA control module). The FIR filter used for filtering ensures strict linear phase frequency characteristics while maintaining arbitrary amplitude-frequency characteristics, and its unit sample response is finite, thus making the filter a stable system.

[0123] In step 12, the user-sent control signal (i.e., the user-transmitted signal) and the calculated speed value are input to the outer loop PI regulator, compared with the current value obtained from the Clark-Park transformation, and then input to the inner loop PI regulator. The system setpoint is also compared with another value obtained from the Clark-Park transformation and input to the inner loop PI regulator. The above two sets of results are used to obtain the voltage value through inverse Park transformation. The voltage value is then calculated and processed through SVPWM to obtain the control signal. The control signal is output to the motor drive unit, specifically to the gate drive module of the IGBT-based inverter unit in the motor drive unit.

[0124] In some embodiments, the communication unit includes a CAN bus and a NIOS soft-core processor; the CAN bus and the NIOS soft-core processor are located between the host computer and the vector control module.

[0125] The acquisition unit 102 acquires the rotational speed value transmitted by the communication unit, and records it as the given rotational speed value of the motor, including:

[0126] The acquisition unit 102 is specifically configured to receive a speed control signal sent by the user through a host computer via the CAN bus; the speed control signal is used to adjust the speed of the motor. The specific functions and processing of the acquisition unit 102 are further described in step S410.

[0127] The acquisition unit 102 is specifically configured to process the speed control signal received via the CAN bus through the NIOS soft-core processor, and then output the speed value corresponding to the speed control signal sent by the host computer, which is recorded as the given speed value of the motor. The specific functions and processing of this acquisition unit 102 are further described in step S420.

[0128] Specifically, Figure 10 This is a schematic diagram illustrating the logical functions of the CAN bus and the NIOS II soft-core processor. Figure 10 As shown, the present invention also incorporates a NIOS II soft-core processor and a Controller Area Network (CAN) IP core. The CAN bus receives control signals from the PC and then passes them to the logic control section (i.e., the FPGA control module) for execution via the CPU loaded with the NIOS II soft-core processor. This achieves the design of a vector control system for the motor drive unit. The CAN bus module receives adjustment signals sent by the user, and the NIOS soft-core processor transmits these signals to the vector control module (i.e., the FPGA control module).

[0129] See Figure 10 In the example shown, the CAN bus module is used to receive the adjustment signal sent by the user. The NIOS soft-core processor is used to transmit the adjustment signal sent by the user to the vector control module (i.e., the FPGA control module). Then, the vector control module is used to compare the adjustment signal sent by the user with the calculated speed value and input it to the outer loop PI regulator. This value, together with the system set value, is compared with the reference value obtained by filtering and Clark-Park transformation of the current value. Then, it is input to the inner loop PI regulator, and the voltage value is obtained by inverse Park transformation.

[0130] The control unit 104 is configured to enable the vector control module to generate a control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, and to output the control signal to the drive module, so that the drive module controls the switching of the power switch in the inverter module under the control of the control signal, thereby controlling the motor. The specific functions and processing of the control unit 104 are described in step S120.

[0131] The present invention provides a control scheme for a vector control system of a motor drive unit of an asynchronous motor based on an FPGA. This vector control system of the motor drive unit of the asynchronous motor based on an FPGA is a drive system that uses a three-phase asynchronous AC motor as the controlled object, IGBTs as the power unit, and vector control as the control strategy. It uses an FPGA as the control core, introduces the CORDIC algorithm to optimize the trigonometric function operations involved in the logic unit of the control strategy, and adds FIR filtering to the A / D generated signal, improving the accuracy and reliability of the vector control system for controlling the motor drive unit. It also incorporates a NIOS II soft-core processor and a Controller Area Network (CAN) IP core, using the CAN bus to receive control signals from the PC and then pass them to the CPU for execution by the logic control part of the control strategy. This avoids the susceptibility of DSP-based control methods to the influence of motor parameters, especially the rotor resistance of the motor, thus improving the control effect on the motor.

[0132] In some implementations, the vector control module further includes a first comparator, a second comparator, a third comparator, a first PI controller, a second PI controller, a third PI controller, a Park inverse converter module, and an SVPWM module.

[0133] The control unit 104 enables the vector control module to generate a control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, including:

[0134] The control unit 104 is specifically configured to output a first current value after passing the given speed value of the motor and the sampled speed value of the motor through the first comparator and the first PI controller. The specific functions and processing of the acquisition unit 102 are further described in step S510.

[0135] The control unit 104 is specifically configured to output a first voltage value after the first current value and the sampled current value of the motor are passed through the second PI controller. The specific functions and processing of the acquisition unit 102 are further described in step S520.

[0136] The control unit 104 is specifically configured to obtain a second voltage value by passing a preset reference current value and the sampled current value of the motor through the third comparator and the third PI controller. The specific functions and processing of the acquisition unit 102 are further described in step S530.

[0137] The control unit 104 is specifically configured to output a control signal after the first voltage value and the second voltage value are processed by the Park inverse converter module and the SVPWM module. The specific functions and processing of the acquisition unit 102 are further described in step S540.

[0138] Specifically, in Figure 9 In the example shown, the control signal sent by the user (i.e., the user-transmitted signal) is input to the first input terminal of the first comparator; the photoelectric encoder collects the speed signal from the three-phase AC asynchronous motor M, and the speed signal, after being processed by the speed calculator, outputs the speed value corresponding to the speed regulation signal sent by the host computer to the second input terminal of the first comparator. The output terminal of the first comparator outputs the first PI processing result after passing through the first PI module. The first PI processing result is input to the first input terminal of the second comparator; the motor current signal detected by the current detection module is transformed by Clark-Park to obtain the current value corresponding to the motor current signal, which is input to the second input terminal of the second comparator. The output terminal of the second comparator outputs the second PI processing result after passing through the second PI module; the second PI processing result is input to the first input terminal of the Park inverse transform module. The system setting value is input to the first input terminal of the third comparator; the motor current signal detected by the current detection module is transformed by Clark-Park to obtain the current value corresponding to the motor current signal, which is also input to the second input terminal of the third comparator. The output terminal of the third comparator outputs the third PI processing result after passing through the third PI module. The third PI processing result is input to the second input terminal of the Park inverse transform module. The first output terminal and the second output terminal of the Park inverter module output control signals to the drive unit after passing through the SVPWM module. Specifically, the control signals are output to the gate drive module of the IGBT-based inverter unit in the motor drive unit.

[0139] In this invention, the NIOS II processor handles the communication module with the host PC and the CORDIC algorithm for processing trigonometric functions. Using the CORDIC algorithm (i.e., the coordinate rotation digital calculation method) offers significant advantages, including eliminating the need for hardware multipliers, enabling pipelined processing, and allowing for iterative iteration. Furthermore, its computational method aligns with the modular characteristics of hardware algorithms, facilitating implementation in an FPGA.

[0140] The core of vector control algorithms is to transform an AC motor into a DC motor through model conversion for control. To achieve this, the physical parameters of the AC motor need to be converted into those of the DC motor. Physically speaking, this requires transforming the three-phase stationary axis ABC coordinate system into a two-phase synchronous rotating axis MT coordinate system. The Clark and Park transformations are precisely the transformations used to achieve this goal.

[0141] In the actual performance of Clarke and Park transforms, the scheme of this invention adopts the CORDIC algorithm. Its core idea is to divide the rotation angle into several minimal angles and use an iterative method to approximate the desired angle. Let vector (X...) i Y i The rotation angle θ becomes a vector (X). j Y j ), which can be represented in matrix form as:

[0142] .

[0143] Here, we use an iterative approach to decompose a rotation angle into n minimum angles. The relationship between adjacent minimum angles can be expressed as:

[0144] .

[0145] After analyzing the vector (X) i Y i Further constraints on the rotation angle θ, including the unrotated angle Z0, and considering the limit approximation case with multiple iterations, when calculating the coordinate transformation, the input is:

[0146] .

[0147] After multiple iterations, the final output is obtained:

[0148] .

[0149] Where K is the infinite approximation value of cosθn after countless iterations.

[0150] Compared to related schemes that use ROM lookup table methods and polynomial approximation methods to calculate trigonometric functions, inverse trigonometric functions, hyperbolic functions, and other transcendental functions, the CORDIC algorithm has significant advantages such as not requiring hardware multipliers, using pipelined methods, and being able to iterate cyclically. Furthermore, its computational method conforms to the modular characteristics of hardware algorithms, thus facilitating its implementation in FPGAs.

[0151] In some embodiments, the motor control device of the present invention further includes a process of communicating with a host computer via a communication unit, as detailed below:

[0152] The acquisition unit 102 is further configured to enable the vector control module to acquire the operating parameters of the motor during the operation of the motor. The specific functions and processing of the acquisition unit 102 are further described in step S610.

[0153] The control unit 104 is further configured to enable the vector control module to upload the motor's operating parameters to the host computer via the communication unit, thereby enabling the host computer to monitor the motor's operating parameters. The specific functions and processing of this control unit 104 are further described in step S620.

[0154] Specifically, Figure 11 This diagram illustrates the relationship between the motor, control unit 104, drive unit, detection unit, and user. In the present invention, the relationship between the three-phase asynchronous AC motor, drive unit, detection unit, control unit 104, and user interface is as follows: Figure 11 As shown. The detection unit is used to collect the current, voltage, and speed signals of the motor; the FPGA control unit 104 is used to obtain a control signal based on the current, voltage, and speed signals of the motor, combined with the adjustment signal sent by the user, using a vector control algorithm, and outputs the control signal to the drive unit, specifically to the gate drive module of the IGBT-based inverter unit in the motor drive unit; the motor drive unit is used to drive the motor to work according to the control signal, wherein the motor is connected to the detection unit and the drive unit respectively, and the FPGA control unit 104 is connected to the detection unit and the drive unit respectively.

[0155] In the present invention, the above embodiments are for a specific asynchronous motor. When the vector control system of the motor drive unit adopts a synchronous motor, the same control system can also be used.

[0156] In this invention, the CORDIC algorithm is introduced to optimize trigonometric function operations, and an IP core and a soft-core processor are added for communication with the PC. The CORDIC algorithm optimizes the trigonometric function operations involved in the logic unit of the control strategy and incorporates FIR filtering for the A / D generated signals, improving the accuracy and reliability of the vector control system for the motor drive unit's control. The NIOSII processor handles communication with the host PC, allowing parameters to be adjusted according to the application, expanding the applicability and enhancing the competitiveness of the servo motor in the market. In this invention, the NIOSII processor (i.e., the NIOSII series soft-core processor) handles communication with the host PC, receiving data from the host computer via an interface and simultaneously reading the motor's parameter register values, sending them to the host PC for display. This allows users to monitor motor operating parameters on the PC, such as motor current commands, current feedback, speed commands, speed feedback, position commands, and position feedback, improving the efficiency of technicians in adjusting motor parameters and enhancing the motor's control effect.

[0157] Since the processing and functions implemented by the device in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned methods, any details not covered in the description of this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0158] The technical solution of this invention involves setting up a CAN bus, a CPU control module with a NIOS soft-core processor (such as a NIOS II soft-core processor), and a vector control module with an FPGA as the control core and incorporating the CORDIC algorithm in the vector control system of the motor drive unit. When controlling the vector control system of the motor drive unit, the motor current signal is acquired, filtered, and then subjected to Clark-Park transformation to obtain a reference value, which is then transmitted to the vector control module. The motor speed signal is acquired, and the speed value is calculated to obtain the motor speed value, which is then transmitted to the vector control module. After receiving the user's control signal via the CAN bus... The NIOS soft-core processor transmits the received user control signals to the vector control module. In the vector control module, the outer loop PI control based on the user's control signals and reference values ​​is input to the Park inverse converter module. The inner loop PI control based on the set value and reference value is then input to the Park inverse converter module. After the Park inverse converter module performs a Park inverse transformation, a voltage value is obtained. This voltage value is then output as a control signal to the drive unit via the SVPWM module. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit in the motor drive unit to drive the motor. This improves the efficiency of technicians in adjusting motor parameters and enhances the motor control effect.

[0159] According to an embodiment of the present invention, a motor corresponding to a control device for a motor is also provided. This motor may include the control device for the motor described above.

[0160] Since the processing and functions implemented by the motor in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned device, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0161] The technical solution of this invention involves setting up a CAN bus, a CPU control module with a NIOS soft-core processor (such as a NIOS II soft-core processor), and a vector control module with an FPGA as the control core and incorporating the CORDIC algorithm in the vector control system of the motor drive unit. When controlling the vector control system of the motor drive unit, the motor current signal is acquired, filtered, and then subjected to Clark-Park transformation to obtain a reference value, which is then transmitted to the vector control module. The motor speed signal is acquired, and the speed value is calculated to obtain the motor speed value, which is then transmitted to the vector control module. After receiving the user's control signal via the CAN bus, the signal is transmitted via the FPGA. The IOS soft-core processor transmits the received user control signals to the vector control module. In the vector control module, the outer loop PI control is performed based on the user's control signals and reference values, and then the signal is input to the Park inverse converter module. The inner loop PI control is performed based on the set value and reference value, and then the signal is input to the Park inverse converter module. After the Park inverse converter module performs the Park inverse transformation, a voltage value is obtained. This voltage value is then output as a control signal to the drive unit via the SVPWM module. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit in the motor drive unit, driving the motor to work. This improves the accuracy and reliability of the vector control system of the motor drive unit in controlling the motor drive unit.

[0162] According to an embodiment of the present invention, a storage medium corresponding to a motor control method is also provided, the storage medium including a stored program, wherein the program controls the device where the storage medium is located to execute the motor control method described above when it is executed.

[0163] Since the processing and functions implemented by the storage medium in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned methods, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0164] The technical solution of this invention involves setting up a CAN bus, a CPU control module with a NIOS soft-core processor (such as a NIOS II soft-core processor), and a vector control module using an FPGA as the control core and incorporating the CORDIC algorithm in the vector control system of the motor drive unit. When controlling the vector control system of the motor drive unit, the motor current signal is acquired, filtered, and then subjected to Clark-Park transformation to obtain a reference value, which is then transmitted to the vector control module. The motor speed signal is acquired, and the speed value is calculated to obtain the motor speed value, which is then transmitted to the vector control module. After receiving the user's control signal via the CAN bus, the NIOS soft-core processor... The processor transmits the received user control signals to the vector control module. In the vector control module, the outer loop PI control is performed based on the user's control signals and reference values, and then the signal is input to the Park inverse converter module. The inner loop PI control is performed based on the set value and reference value, and then the signal is input to the Park inverse converter module. After the Park inverse converter module performs the Park inverse transformation, a voltage value is obtained. This voltage value is then output as a control signal to the drive unit via the SVPWM module. Specifically, the control signal is output to the gate drive module of the IGBT-based inverter unit in the motor drive unit to drive the motor. This avoids the influence of motor parameters, especially the rotor resistance, which is easily affected by DSP-based control methods, thus improving the control effect on the motor.

[0165] In summary, it is readily understood by those skilled in the art that, without conflict, the aforementioned advantageous methods can be freely combined and superimposed.

[0166] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of the claims.

Claims

1. A method for controlling an electric motor, characterized in that, The motor has a drive unit; the drive unit includes a communication unit and an inverter control unit; the inverter control unit includes an inverter module composed of power switching transistors, a drive module for driving the inverter module, and a vector control module for controlling the drive module; the vector control module uses an FPGA as its control core and is loaded with a CORDIC algorithm; the motor control method includes: After the motor is powered on and started, the vector control module acquires the motor's rotational speed value, which is recorded as the sampled rotational speed value of the motor; acquires the motor's current value, which is recorded as the sampled current value of the motor; and acquires the rotational speed value transmitted by the communication unit, which is recorded as the given rotational speed value of the motor; the given rotational speed value is the target rotational speed value issued by the host computer for adjusting the rotational speed of the motor. The vector control module combines the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor to generate a control signal, and outputs the control signal to the drive module, so that the drive module controls the switching of the power switch in the inverter module under the control of the control signal, thereby controlling the motor.

2. The motor control method according to claim 1, characterized in that, The vector control module also includes a photoelectric encoder and a speed calculator; Obtain the motor's rotational speed value, denoted as the sampled rotational speed value of the motor, including: Receive the motor speed signal sampled by the photoelectric encoder; The speed calculator calculates the speed signal of the motor to obtain the speed value corresponding to the speed signal of the motor, which is recorded as the sampled speed value of the motor.

3. The motor control method according to claim 1, characterized in that, The vector control module also includes a current detection module, an A / D converter, an FIR filter, and a Clark-Park conversion module; Obtain the current value of the motor, denoted as the sampled current value of the motor, including: Receive the current signal of the motor detected by the current detection module; The motor current signal is converted by the A / D converter, filtered by the FIR filter, and then transformed by the Clark-Park transformation module using the CORDIC algorithm to obtain the current value corresponding to the motor current signal, which is recorded as the motor sampling current value.

4. The motor control method according to claim 1, characterized in that, The communication unit includes a CAN bus and a NIOS soft-core processor; the CAN bus and the NIOS soft-core processor are located between the host computer and the vector control module. Obtaining the rotational speed value transmitted by the communication unit, denoted as the given rotational speed value of the motor, includes: The system receives speed control signals sent by the user via a host computer through the CAN bus; these speed control signals are used to adjust the speed of the motor. The NIOS soft-core processor processes the speed control signal received via the CAN bus and outputs the speed value corresponding to the speed control signal sent by the host computer, which is recorded as the given speed value of the motor.

5. The motor control method according to any one of claims 1 to 4, characterized in that, The vector control module also includes a first comparator, a second comparator, a third comparator, a first PI controller, a second PI controller, a third PI controller, a Park inverse converter module, and an SVPWM module; The vector control module, combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, generates a control signal, including: The given speed value of the motor and the sampled speed value of the motor are passed through the first comparator and the first PI controller to output a first current value; The first current value and the sampled current value of the motor are combined and then processed by the second PI controller to output a first voltage value. The preset reference current value and the sampled current value of the motor are compared and then processed by the third comparator and the third PI controller to obtain a second voltage value. The first voltage value and the second voltage value are processed by the Park inverse converter module and the SVPWM module to output a control signal.

6. The motor control method according to claim 1, characterized in that, Also includes: During the operation of the motor, the vector control module acquires the operating parameters of the motor; The vector control module uploads the motor's operating parameters to the host computer via the communication unit, enabling the host computer to monitor the motor's operating parameters.

7. A control device for an electric motor, characterized in that, The motor has a drive unit; the drive unit includes a communication unit and an inverter control unit; the inverter control unit includes an inverter module composed of power switching transistors, a drive module for driving the inverter module, and a vector control module for controlling the drive module; the vector control module uses an FPGA as its control core and is loaded with a CORDIC algorithm; the motor control device includes: The acquisition unit is configured to, after the motor is powered on and started, cause the vector control module to acquire the motor's rotational speed value, denoted as the motor's sampled rotational speed value; acquire the motor's current value, denoted as the motor's sampled current value; and acquire the rotational speed value transmitted by the communication unit, denoted as the motor's given rotational speed value; the given rotational speed value is a target rotational speed value issued by the host computer for adjusting the motor's rotational speed; The control unit is configured to enable the vector control module to generate a control signal by combining the given speed value of the motor, the sampled speed value of the motor, and the sampled current value of the motor, and to output the control signal to the drive module, so that the drive module controls the switching of the power switch in the inverter module under the control of the control signal, thereby controlling the motor.

8. The motor control device according to claim 7, characterized in that, Also includes: The acquisition unit is further configured to enable the vector control module to acquire the operating parameters of the motor during the operation of the motor. The control unit is further configured to enable the vector control module to upload the motor's operating parameters to the host computer via the communication unit, so that the host computer can monitor the motor's operating parameters.

9. An electric motor, characterized in that, include: The motor control device as described in any one of claims 7 to 8.

10. A storage medium, characterized in that, The storage medium includes a stored program, wherein, when the program is executed, the device containing the storage medium is controlled to perform the motor control method according to any one of claims 1 to 6.

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