A transimpedance amplifier front-end circuit and a transimpedance amplifier

Abstract

The application discloses a trans-impedance amplifier front-end circuit and a trans-impedance amplifier, and relates to the technical field of optical communication equipment, which comprises a single-ended amplifier unit, a differential pair amplifier unit, a source follower unit, a first feedback and control unit, a second feedback and control unit and a bias adjustment unit; the output end of the single-ended amplifier is connected with the non-inverting input end of the differential pair amplifier unit; the non-inverting output end and the inverting output end of the differential pair amplifier unit are connected with the first input end and the second input end of the source follower unit; the first output end and the second output end of the source follower unit are connected with the non-inverting input end and the inverting input end of the first feedback and control unit and the second feedback and control unit; the second feedback and control unit is used for making the output signal amplitude of the first output end and the second output end of the source follower unit and the input signal amplitude of the input end of the single-ended amplifier unit present a linear relationship. The application omits a single-ended-to-differential circuit and realizes linear change of the output signal amplitude with the input signal amplitude.

Description

Technical Field

[0001] This invention relates to the field of optical communication equipment technology, and in particular to a transimpedance amplifier front-end circuit and a transimpedance amplifier. Background Technology

[0002] Currently, home broadband has fully transitioned from the early Kbps copper wire era to the hundred Mbps fiber optic era. The rise and widespread adoption of broadband services such as e-commerce and 4K high-definition video have propelled domestic broadband access networks into the fiber optic (Optical Access Network) era, seamlessly evolving and upgrading from G / EPON to 10G / EPON. The recent emergence of cloud computing, 8K video, autonomous driving, artificial intelligence (AI), and virtual reality (VR) has further driven operators to upgrade existing networks to achieve ultra-broadband to support real-time ultra-high-definition video transmission, low latency to support real-time monitoring and rapid response, and ultra-large capacity to support the coexistence of numerous real-time services. These demands have accelerated domestic operators' efforts to actively advance the standardization and prototype development of the next-generation 50G PON (optical access network), requiring optical module manufacturers to provide 50GPON optical modules and optical / electrical chip manufacturers to develop and provide related 50Gbps / 25Gbps optical and electrical chips.

[0003] Although 50G PON is currently in the standardization stage, and related IC chip manufacturers are still in the preliminary research and tracking phase, the existing standards have clearly stated that 50G PON uses NRZ (Non-return-to-zero) coding for downlink and a downlink data rate of 50Gbps. Furthermore, in the optical signal receiving channel on the Optical Network Unit (ONU) side, a DSP will be used to improve channel performance. The use of DSP means that the DSP's front-end circuit, the transimpedance amplifier (TIA), must be a linear circuit. That is, the 50G continuous optical receiver on the 50G PON ONU side needs to use a 50Gbps linear TIA.

[0004] Existing optical access network (G / EPON, 10G G / EPON, 25G EPON) optical modules and their standard-defined downlink modulation / reception methods use NRZ limiting. Therefore, the typical structure of existing transimpedance amplifiers for optical access networks involves setting a single-ended to differential circuit after the transimpedance amplifier's front-end circuit, employing NRZ limiting operation. There is a significant difference between NRZ limiting and NRZ linear methods: limiting means the output voltage amplitude of the optical receiver does not change with the input current amplitude; for example, when the input signal amplitude is greater than or equal to 30uA, the output voltage amplitude of the optical receiver remains at 300mV. Linear methods, on the other hand, require the output voltage amplitude of the optical receiver to change linearly with the input current amplitude; for example, the output voltage amplitude is 300mV when the input signal amplitude is 30uA, and 1000mV when the input signal amplitude is 100uA, with the ratio of the output voltage amplitude to the input signal amplitude remaining constant at 10. Therefore, it is urgent to improve existing transimpedance amplifiers to meet the linear signal reception requirements in ultra-high-speed scenarios such as 50G PON. Summary of the Invention

[0005] This invention provides a transimpedance amplifier front-end circuit and a transimpedance amplifier to solve the technical problem that existing transimpedance amplifier front-end circuits with single-ended to differential circuits on the back and NRZ limiting operating mode are difficult to meet the linear signal reception requirements in 50G PON ultra-high-speed scenarios.

[0006] In a first aspect, a transimpedance amplifier front-end circuit is provided, comprising: a single-ended amplification unit, a differential pair amplification unit, a source follower unit, a first feedback and control unit, a second feedback and control unit, and a bias adjustment unit;

[0007] The input terminal of the single-ended amplifier unit is the input terminal of the transimpedance amplifier front-end circuit, and the output terminal of the single-ended amplifier is connected to the non-inverting input terminal of the differential pair amplifier unit.

[0008] The non-inverting output terminal and the inverting output terminal of the differential pair amplifier unit are respectively connected to the first input terminal and the second input terminal of the source follower unit;

[0009] The first and second output terminals of the source follower unit are the non-inverting and inverting output terminals of the transimpedance amplifier front-end circuit, respectively, and are connected to the non-inverting and inverting input terminals of the first and second feedback and control units.

[0010] The feedback terminal of the first feedback and control unit is connected to the input terminal of the bias adjustment unit, the output terminal of the bias adjustment unit is connected to the inverting input terminal of the differential pair amplification module, and the feedback terminal of the second feedback and control unit is connected to the bias current control terminal of the differential pair amplification unit.

[0011] The second feedback and control unit is used to adjust the bias current of the differential pair amplifier unit by outputting a control signal at its feedback terminal based on the input signal information of its non-inverting input terminal and inverting input terminal, so that the output signal amplitude of the first output terminal and the second output terminal of the source follower unit is linearly related to the input signal amplitude of the input terminal of the single-ended amplifier unit.

[0012] In some embodiments, the differential pair amplification unit includes a differential pair amplification module, a first resistor, a second resistor, a third resistor, and a first NMOS transistor;

[0013] The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to the non-inverting output terminal of the differential pair amplifier module and the first input terminal of the source follower unit.

[0014] The first end of the second resistor is connected to the power supply, and the second end of the second resistor is connected to the inverting output terminal of the differential pair amplifier module and the second input terminal of the source follower unit.

[0015] The in-phase input terminal of the differential pair amplifier module is connected to the output terminal of the single-ended amplifier unit;

[0016] The first end of the third resistor is connected to the bias current terminal of the differential pair amplifier module, the second end of the third resistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to the feedback terminal of the second feedback and control unit.

[0017] In some embodiments, the first feedback and control unit includes a comparison and feedback control unit, a first low-pass filter, and a second low-pass filter;

[0018] The input terminals of the first low-pass filter and the second low-pass filter are respectively the non-inverting input terminal and the inverting input terminal of the second feedback and control unit;

[0019] The non-inverting input and inverting input of the comparison and feedback control unit are respectively connected to the output of the first low-pass filter and the output of the second low-pass filter.

[0020] The output of the comparison and feedback control unit is the feedback terminal of the first feedback and feedback control unit.

[0021] In some embodiments, the source follower unit includes a bias current unit, a first source follower, and a second source follower;

[0022] The power supply terminal of the bias current unit is connected to a power source.

[0023] The input terminal of the first source follower is connected to the non-inverting output terminal of the differential pair amplifier module, the power supply terminal of the first source follower is connected to the power supply, the output terminal of the first source follower is the non-inverting output terminal of the transimpedance amplifier front-end circuit, and the bias current control terminal of the first source follower is connected to the output terminal of the bias current unit.

[0024] The input terminal of the second source follower is connected to the inverting output terminal of the differential pair amplifier module, the power supply terminal of the second source follower is connected to the power supply, the output terminal of the second source follower is the inverting output terminal of the transimpedance amplifier front-end circuit, and the bias current control terminal of the second source follower is connected to the output terminal of the bias current unit.

[0025] In some embodiments, the bias current unit includes a first current source and a second NMOS transistor. The power supply terminal of the first current source is connected to a power supply, and the output terminal of the first current source is connected to the drain and gate of the second NMOS transistor to serve as the output terminal of the bias current unit.

[0026] The first source follower includes a first transistor and a third NMOS transistor. The collector of the first transistor is connected to the power supply, the base of the first transistor is connected to the non-inverting output terminal of the differential pair amplifier module, the emitter of the first transistor is the non-inverting output terminal of the transimpedance amplifier front-end circuit and is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is the bias current control terminal of the first source follower.

[0027] The second source follower includes a second transistor and a fourth NMOS transistor. The collector of the second transistor is connected to the power supply, the base of the second transistor is connected to the inverting output terminal of the differential pair amplifier module, the emitter of the second transistor is the inverting output terminal of the transimpedance amplifier front-end circuit and is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is the bias current control terminal of the second source follower.

[0028] The gates of the third NMOS transistor and the fourth NMOS transistor are connected to the output terminal of the first current source and the gate of the second NMOS transistor, and the sources of the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are grounded.

[0029] In some embodiments, the transimpedance amplifier front-end circuit further includes:

[0030] A feedback resistor unit, wherein the first input terminal of the feedback resistor unit is connected to the bias current terminal of the differential pair amplifier module, and the feedback terminal of the feedback resistor unit is connected to the input terminal of the single-ended amplifier unit.

[0031] The third feedback and control unit, wherein the input terminal of the third feedback and control unit is connected to the bias current terminal of the differential pair amplifier module;

[0032] The fifth NMOS transistor has its drain connected to the input terminal of the single-ended amplifier unit, its gate connected to the feedback terminal of the third feedback and control unit, and its source grounded.

[0033] In some embodiments, the transimpedance amplifier front-end circuit further includes:

[0034] The fourth feedback and control unit, wherein the input terminal of the fourth feedback and control unit is connected to the bias current terminal of the differential pair amplification module;

[0035] The third transistor has its collector connected to the input terminal of the single-ended amplifier unit, its base connected to the first feedback terminal of the fourth feedback and control unit, and its emitter grounded.

[0036] The second feedback terminal of the fourth feedback and control unit is connected to the second input terminal of the feedback resistor unit.

[0037] In some embodiments, the differential pair amplification module includes a fourth transistor and a fifth transistor;

[0038] The base of the fourth transistor is connected to the output of the single-ended amplifier unit as the non-inverting input of the differential pair amplifier module, and the collector of the fourth transistor is connected to the first input of the source follower unit as the non-inverting output of the differential pair amplifier module.

[0039] The base of the fifth transistor is connected to the output of the bias adjustment unit as the inverting input of the differential pair amplification module, and the collector of the fifth transistor is connected to the second input of the source follower unit as the inverting output of the differential pair amplification module.

[0040] The emitter of the fourth transistor is connected to the emitter of the fifth transistor as the bias current terminal of the differential pair amplifier module.

[0041] In some embodiments, the single-ended amplifier unit includes a sixth transistor and a fourth resistor;

[0042] The base of the sixth transistor serves as the input terminal of the single-ended amplifier unit, the collector of the sixth transistor serves as the output terminal of the single-ended amplifier unit, and is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the power supply, and the emitter of the sixth transistor is grounded.

[0043] Secondly, a transimpedance amplifier is provided, including the aforementioned transimpedance amplifier front-end circuit, and further including: a variable gain amplification unit, an output buffer unit, a DC-offset correction unit, and a signal strength detection and gain control signal generation unit;

[0044] The non-inverting and inverting output terminals of the transimpedance amplifier front-end circuit are connected to the non-inverting and inverting input terminals of the variable gain amplifier unit.

[0045] The non-inverting output terminal and the inverting output terminal of the variable gain amplifier unit are connected to the non-inverting input terminal and the inverting input terminal of the output buffer unit.

[0046] The non-inverting output terminal and the inverting output terminal of the output buffer unit serve as the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier, and are connected to the non-inverting input terminal and the inverting input terminal of the DC-offset correction unit and the signal strength detection and gain control signal generation circuit.

[0047] The in-phase output and out-of-phase output of the DC-offset correction unit are connected to the DC-offset feedback differential input of the variable gain amplifier unit.

[0048] The output of the signal strength detection and gain control signal generation unit is connected to the gain control input of the variable gain amplifier unit.

[0049] The beneficial effects of the technical solution provided by this invention include:

[0050] This invention provides a transimpedance amplifier front-end circuit and a transimpedance amplifier, which includes a single-ended amplification unit, a differential pair amplification unit, a source follower unit, a first feedback and control unit, a second feedback and control unit, and a bias adjustment unit. On one hand, this invention uses a single-ended amplification unit and a differential pair amplification unit in the transimpedance amplifier front-end circuit, combined with a source follower unit, a first feedback and control unit, and a bias adjustment unit, to directly achieve differential output, eliminating the need for the single-ended to differential circuit at the rear of the existing transimpedance amplifier front-end circuit. On the other hand, this invention also includes a second feedback and control unit between the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier front-end circuit and the bias current control terminal of the differential pair amplification unit, enabling the output signal amplitude of the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier front-end circuit to linearly change with the input signal amplitude of the input terminal of the single-ended amplification unit, meeting the linear signal reception requirements in ultra-high-speed scenarios such as 50G PON. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the front-end circuit of a transimpedance amplifier provided in an embodiment of the present invention;

[0053] Figure 2A This is a second circuit diagram of the differential pair amplifier unit provided in an embodiment of the present invention;

[0054] Figure 2B The third circuit diagram of the differential pair amplifier unit provided in the embodiment of the present invention;

[0055] Figure 3A This is a second circuit diagram of the source follower unit provided in an embodiment of the present invention;

[0056] Figure 3B The third circuit diagram of the source follower unit provided in the embodiment of the present invention;

[0057] Figure 3C This is a fourth circuit diagram of the source follower unit provided in an embodiment of the present invention;

[0058] Figure 4 This is a schematic diagram of the structure of a transimpedance amplifier provided in an embodiment of the present invention;

[0059] Figure 5A This is a first transient simulation diagram of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention;

[0060] Figure 5B A second transient simulation diagram of a transimpedance amplifier front-end circuit provided for an embodiment of the present invention;

[0061] Figure 5C A third transient simulation diagram of a transimpedance amplifier front-end circuit provided for an embodiment of the present invention;

[0062] Figure 5D This is a fourth transient simulation diagram of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention;

[0063] Figure 5E This is a fifth transient simulation diagram of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention.

[0064] Figure 5FThis is a sixth transient simulation diagram of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention.

[0065] Figure 5G This is a seventh transient simulation diagram of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention.

[0066] Figure 6 A group delay simulation diagram of the front-end circuit of a transimpedance amplifier provided in an embodiment of the present invention;

[0067] Figure 7A This is a simulation diagram of the first harmonic of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention;

[0068] Figure 7B A simulation diagram of the second harmonic of a transimpedance amplifier front-end circuit provided for an embodiment of the present invention;

[0069] Figure 7C A simulation diagram of the third harmonic of a transimpedance amplifier front-end circuit provided for an embodiment of the present invention;

[0070] Figure 7D This is a simulation diagram of the fourth harmonic of a transimpedance amplifier front-end circuit provided in an embodiment of the present invention. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0072] This invention provides a transimpedance amplifier front-end circuit that solves the technical problem that existing transimpedance amplifier front-end circuits, which use a single-ended to differential circuit on the back and employ NRZ limiting operation mode, are unable to meet the linear signal reception requirements in 50G PON ultra-high-speed scenarios.

[0073] See Figure 1 As shown, an embodiment of the present invention provides a transimpedance amplifier front-end circuit, including: a single-ended amplification unit, a differential pair amplification unit, a source follower unit, a first feedback and control unit, a second feedback and control unit, and a bias adjustment unit.

[0074] The input terminal IN of the single-ended amplifier unit is the input terminal of the front-end circuit of the transimpedance amplifier, and the output terminal IN of the single-ended amplifier is connected to the non-inverting input terminal INP of the differential pair amplifier unit.

[0075] The non-inverting output terminal OUTP and the inverting output terminal OUTN of the differential pair amplifier unit are respectively connected to the first input terminal and the second input terminal of the source follower unit.

[0076] The first and second output terminals of the source follower unit are the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn of the transimpedance amplifier front-end circuit, and are connected to the non-inverting input terminal and the inverting input terminal of the first feedback and control unit and the second feedback and control unit.

[0077] The feedback terminal of the first feedback and control unit is connected to the input terminal of the bias adjustment unit, the output terminal of the bias adjustment unit is connected to the inverting input terminal INN of the differential pair amplifier module, and the feedback terminal of the second feedback and control unit is connected to the bias current control terminal of the differential pair amplifier unit.

[0078] Specifically, see Figure 1 As shown, the first feedback and control unit monitors the difference in DC components between the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn of the transimpedance amplifier front-end circuit, and outputs a feedback control signal VDFB in real time at its feedback terminal based on the monitoring and comparison results. This changes the bias voltage signal output by the bias adjustment unit, thereby adjusting the DC voltage component of the inverting input terminal INN in the differential input pair of the differential pair amplifier unit in real time. Consequently, it adjusts the DC voltage component of the inverting output terminal OUTN in the differential output pair of the differential pair amplifier unit, and further adjusts the DC voltage component of the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit. This ensures that the DC voltage components of the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit are approximately equal in real time.

[0079] The second feedback and control unit is used to adjust the bias current of the differential pair amplifier unit by outputting a control signal at its feedback terminal based on the input signal information of its non-inverting input terminal and inverting input terminal, so that the output signal amplitude of the first output terminal and the second output terminal of the source follower unit is linearly related to the input signal amplitude of the input terminal of the single-ended amplifier unit.

[0080] Specifically, see Figure 1As shown, the second feedback and control unit monitors the signal strength of the non-inverting output terminal mTIAoutp and the signal strength of the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit, and adjusts the feedback control signal VAFB in real time according to the monitoring comparison results. This, in turn, adjusts the output signal amplitude of the non-inverting output terminal OUTP and the output signal amplitude of the inverting output terminal OUTN in the differential output pair of the differential amplifier unit in real time. This further adjusts the signal amplitude of the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit, maintaining the signal amplitude of the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit at approximately equal levels, and exhibiting a linear relationship with the input signal amplitude of the input terminal IN of the single-ended amplifier unit.

[0081] The transimpedance amplifier front-end circuit in this embodiment of the invention includes a single-ended amplification unit, a differential pair amplification unit, a source follower unit, a first feedback and control unit, a second feedback and control unit, and a bias adjustment unit. On one hand, by employing a single-ended amplification unit and a differential pair amplification unit in the transimpedance amplifier front-end circuit, and in conjunction with the source follower unit, the first feedback and control unit, and the bias adjustment unit, differential output is directly achieved, eliminating the need for the single-ended to differential circuit on the back side of the existing transimpedance amplifier front-end circuit (based on single-ended input and single-ended output). On the other hand, the invention also includes a second feedback and control unit between the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier front-end circuit and the bias current control terminal of the differential pair amplification unit. This enables the output signal amplitude of the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier front-end circuit to linearly change with the input signal amplitude of the input terminal of the single-ended amplification unit, meeting the linear signal reception requirements in ultra-high-speed scenarios such as 50G PON.

[0082] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the differential pair amplification unit includes a differential pair amplification module, a first resistor R1, a second resistor R2, a third resistor R3, and a first NMOS transistor MN1.

[0083] The first end of the first resistor R1 is connected to the power supply VCC, and the second end of the first resistor R1 is connected to the non-inverting output terminal OUTP of the differential pair amplifier module and the first input terminal of the source follower unit.

[0084] The first end of the second resistor R2 is connected to the power supply, and the second end of the second resistor is connected to the inverting output terminal OUTN of the differential pair amplifier module and the second input terminal of the source follower unit. The non-inverting input terminal INP of the differential pair amplifier module is connected to the output terminal OUT of the single-ended amplifier unit.

[0085] The first end of the third resistor R3 is connected to the bias current terminal IB of the differential pair amplifier module, the second end of the third resistor R3 is connected to the drain of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 is grounded, and the gate of the first NMOS transistor MN1 is connected to the feedback terminal of the second feedback and control unit.

[0086] Specifically, see Figure 1 As shown, the second feedback and control unit monitors the signal strength at the non-inverting output terminal mTIAoutp and the signal strength at the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit. Based on the monitoring and comparison results, it adjusts the feedback control signal VAFB in real time and changes the gate voltage of the first NMOS transistor MN1, thereby adjusting the current of the first NMOS transistor MN1 and the bias current of the differential pair amplifier module in real time. This, in turn, adjusts the current flowing through the two output branches of the differential pair amplifier module (connected to the first resistor R1 and the second resistor R2, respectively), and thus... The amplitudes of the output signals at the non-inverting output terminal OUTP and the inverting output terminal OUTN in the differential output pair of the differential pair amplifier unit are adjusted, thereby adjusting the amplitudes of the signals at the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit. This maintains the amplitudes of the signals at the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn in the differential output pair of the transimpedance amplifier front-end circuit at approximately equal levels, and these amplitudes are linearly related to the amplitude of the input signal at the input terminal IN of the single-ended amplifier unit.

[0087] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the first feedback and control unit includes a comparison and feedback control unit, a first low-pass filter, and a second low-pass filter.

[0088] The input terminals of the first low-pass filter and the second low-pass filter are respectively the non-inverting input terminal and the inverting input terminal of the second feedback and control unit. The first low-pass filter and the second low-pass filter are beneficial for obtaining the DC component in the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn of the transimpedance amplifier front-end circuit.

[0089] The non-inverting and inverting input terminals of the comparison and feedback control unit are respectively connected to the output terminals of the first low-pass filter and the second low-pass filter. The output terminal of the comparison and feedback control unit is the feedback terminal of the first feedback and control unit. Based on the difference in DC characteristics of the signals detected at its non-inverting and inverting input terminals, the comparison and feedback control unit controls the output bias voltage of the bias adjustment unit through its output terminal, so that the DC voltage components at the non-inverting output terminal mTIAoutp and the inverting output terminal mTIAoutn of the transimpedance amplifier front-end circuit are approximately equal.

[0090] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the source follower unit includes a bias current unit, a first source follower, and a second source follower.

[0091] The power supply terminal of the bias current unit is connected to the power supply VCC. The input terminal of the first source follower is connected to the non-inverting output terminal of the differential pair amplifier module, the power supply terminal of the first source follower is connected to the power supply VCC, the output terminal of the first source follower is the non-inverting output terminal of the transimpedance amplifier front-end circuit, and the bias current control terminal of the first source follower is connected to the output terminal of the bias current unit.

[0092] The input terminal of the second source follower is connected to the inverting output terminal of the differential pair amplifier module, the power supply terminal of the second source follower is connected to the power supply VCC, the output terminal of the second source follower is the inverting output terminal of the transimpedance amplifier front-end circuit, and the bias current control terminal of the second source follower is connected to the output terminal of the bias current unit.

[0093] Further, see Figure 1 As shown, the bias current unit includes a first current source Ib1 and a second NMOS transistor MN2. The power supply terminal of the first current source Ib1 is connected to the power supply VCC, and the output terminal of the first current source Ib1 is connected to the drain and gate of the second NMOS transistor MN2 to serve as the output terminal of the bias current unit.

[0094] The first source follower includes a first transistor Q1 and a third NMOS transistor MN3. The collector of the first transistor Q1 is connected to the power supply VCC, the base of the first transistor Q1 is connected to the non-inverting output terminal OUTP of the differential pair amplifier module, the emitter of the first transistor Q1 is the non-inverting output terminal of the transimpedance amplifier front-end circuit and is connected to the drain of the third NMOS transistor MN3, and the gate of the third NMOS transistor MN3 is the bias current control terminal of the first source follower.

[0095] The second source follower includes a second transistor Q2 and a fourth NMOS transistor MN4. The collector of the second transistor Q2 is connected to the power supply VCC, the base of the second transistor Q2 is connected to the inverting output terminal OUTN of the differential pair amplifier module, the emitter of the second transistor Q2 is the inverting output terminal of the transimpedance amplifier front-end circuit and is connected to the drain of the fourth NMOS transistor MN4, and the gate of the fourth NMOS transistor MN4 is the bias current control terminal of the second source follower.

[0096] The gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the output terminal of the first current source Ib1 and the gate of the second NMOS transistor MN2, and the sources of the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded.

[0097] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the front-end circuit of the transimpedance amplifier also includes: a feedback resistor unit, a third feedback and control unit, and a fifth NMOS transistor MN5.

[0098] The first input terminal of the feedback resistor unit is connected to the bias current terminal IB of the differential pair amplifier module, and the feedback terminal of the feedback resistor unit is connected to the input terminal IN of the single-ended amplifier unit.

[0099] The input terminal of the third feedback and control unit is connected to the bias current terminal IB of the differential pair amplification module.

[0100] The drain of the fifth NMOS transistor MN5 is connected to the input terminal IN of the single-ended amplifier unit, the gate of the fifth NMOS transistor MN5 is connected to the feedback terminal of the third feedback and control unit, and the source of the fifth NMOS transistor MN5 is grounded.

[0101] Specifically, see Figure 1 As shown, the third feedback and control unit outputs a feedback control voltage signal to adjust the current flowing through the fifth NMOS transistor MN5 based on the input signal information (such as the magnitude of DC current) detected at its input terminal, so that the current adjustment range of the fifth NMOS transistor MN5 is approximately 0 to several hundred μA. The main function of the feedback resistor unit, the third feedback and control unit, and the fifth NMOS transistor MN5 is to adjust the output feedback control voltage VIFB1 of the feedback terminal of the third feedback and control unit in real time according to the monitoring result of the output signal of the single-ended amplifier unit when the input terminal IN of the single-ended amplifier unit is under medium / small amplitude input current. This adjustment is achieved by using the branch current flowing through the drain of the fifth NMOS transistor MN5 to ground to cancel out the DC component in the medium / small amplitude input current.

[0102] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the transimpedance amplifier front-end circuit also includes: a fourth feedback and control unit and a third transistor Q3.

[0103] The input terminal of the fourth feedback and control unit is connected to the bias current terminal IB of the differential pair amplification module.

[0104] The collector of the third transistor Q3 is connected to the input terminal IN of the single-ended amplifier unit, the base of the third transistor Q3 is connected to the first feedback terminal of the fourth feedback and control unit, and the emitter of the third transistor Q3 is grounded.

[0105] The second feedback terminal of the fourth feedback and control unit is connected to the second input terminal of the feedback resistor unit.

[0106] Specifically, the fourth feedback and control unit adjusts the current flowing through the third transistor Q3 by outputting a first feedback control voltage signal through its first feedback terminal based on the input signal information (such as DC magnitude, signal amplitude, signal power, etc.) at its input terminal. This adjusts the current of the third transistor Q3 within a range of approximately 0 to several mA. The second feedback control voltage signal is then output through the second feedback terminal to adjust the resistance value of the feedback resistor unit. The main function of the feedback resistor unit, the fourth feedback and control unit, and the third transistor Q3 is to adjust the second feedback control voltage VIFB2 output from the second feedback terminal in real time, based on the monitoring results of the output signal of the single-ended amplifier unit, when the input terminal IN of the single-ended amplifier unit experiences a large input current. This adjustment is achieved by using the branch current flowing from the collector of the third transistor Q3 to ground to offset the DC component in the large input current. The control loop formed by the third and fourth feedback and control units works together to achieve a large dynamic range for the single-ended amplifier unit, ensuring its normal operation under large / medium / small input current conditions.

[0107] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the differential pair amplification module includes a fourth transistor Q4 and a fifth transistor Q5, and has a simple and practical structure.

[0108] The base of the fourth transistor Q4 is connected to the output terminal OUT of the single-ended amplifier unit as the non-inverting input terminal INP of the differential pair amplifier module. The collector of the fourth transistor Q4 is connected to the first input terminal of the source follower unit as the non-inverting output terminal OUTP of the differential pair amplifier module.

[0109] The base of the fifth transistor Q5 is connected to the output of the bias adjustment unit as the inverting input terminal INN of the differential pair amplifier module, and the collector of the fifth transistor Q5 is connected to the second input terminal of the source follower unit as the inverting output terminal OUTN of the differential pair amplifier module.

[0110] The emitter of the fourth transistor Q4 is connected to the emitter of the fifth transistor Q5 as the bias current terminal IB of the differential pair amplifier module.

[0111] As an optional implementation, in one embodiment of the invention, the single-ended amplification unit includes a sixth transistor Q6 and a fourth resistor R4, which has a simple and practical structure.

[0112] The base of the sixth transistor Q6 serves as the input terminal IN of the single-ended amplifier unit, the collector of the sixth transistor Q6 serves as the output terminal OUT of the single-ended amplifier unit, and is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the power supply VCC, and the emitter of the sixth transistor Q6 is grounded.

[0113] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 2A As shown, the differential pair amplifier module may further include: a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a thirteenth transistor Q10, a fifth resistor R5, a first PMOS transistor MP1, a second PMOS transistor MP2, and a second current source Ib2.

[0114] In this differential amplifier module, the emitter of transistor Q7 and the emitter of transistor Q8 are shorted together to serve as the bias current terminal IB. The base of transistor Q7 serves as the non-inverting input INP of the differential amplifier module, and the base of transistor Q8 serves as the inverting input INN. The collector of transistor Q7 is connected to the emitter of transistor Q9, and the collector of transistor Q9 serves as the non-inverting output OUTP of the differential amplifier module. The collector of transistor Q8 is connected to the emitter of transistor Q10, and the collector of transistor Q10 serves as the inverting output OUTN of the differential amplifier module. The bases of transistors Q9 and Q10 are shorted and connected to the first terminal of resistor R5 and the drain of PMOS transistor MP1. The drain of PMOS transistor MP1 provides bias voltage and bias current to the bases of transistors Q9 and Q10. The second terminal of resistor R5 is grounded. The source of PMOS transistor MP1 is connected to power supply VCC. The gate and drain of PMOS transistor MP2 are shorted and connected to the gate of PMOS transistor MP1, and simultaneously connected to the first terminal (output port) of the second current source Ib2. The source of PMOS transistor MP2 is connected to power supply VCC, and the second terminal of the second current source Ib2 is grounded.

[0115] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 2B As shown, the differential pair amplification module may further include: eleventh transistor Q11, twelfth transistor Q12, thirteenth transistor Q13, fourteenth transistor Q14, fifteenth transistor Q15, sixteenth transistor Q16, sixth resistor R6, and seventh resistor R7.

[0116] In this configuration, the emitters of transistors 11, 12, 13, and 14 are shorted together to serve as the bias current terminal IB of the differential amplifier module. The bases of transistors 11 and 13 are shorted together to serve as the non-inverting input terminal INP of the differential amplifier module. The bases of transistors 12 and 14 are shorted together to serve as the inverting input terminal INN of the differential amplifier module. The collectors of transistors 11 and 14 are shorted together and connected to the emitter of transistor Q15. The collector of the fifteenth transistor Q15 serves as the non-inverting output (OUTP) of the differential pair amplifier module. The collectors of the twelfth transistor Q12 and the thirteenth transistor Q13 are shorted and connected to the emitter of the sixteenth transistor Q16. The collector of the sixteenth transistor Q16 serves as the inverting output (OUTN) of the differential pair amplifier module. The bases of the fifteenth transistor Q15 and the sixteenth transistor Q16 are shorted and connected to the first terminals of the sixth resistor R6 and the seventh resistor R7. The second terminal of the sixth resistor R6 is grounded, and the second terminal of the seventh resistor R7 is connected to the power supply VCC. The seventh resistor R7 and the sixth resistor R6 provide bias voltage and bias current to the bases of the fifteenth transistor Q15 and the sixteenth transistor Q16 in a voltage divider configuration.

[0117] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 3A As shown, the source follower unit may further include: a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twenty-third transistor Q20, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a third current source Ib3.

[0118] The bias current unit consists of a third current source Ib3 and a sixth NMOS transistor MN6. The first terminal of the third current source Ib3 is connected to the power supply VCC, and the second terminal of the third current source Ib3 is connected to the drain and gate of the sixth NMOS transistor MN6. The source of the sixth NMOS transistor MN6 is grounded. The gate of the sixth NMOS transistor MN6 serves as the output terminal Ibias21 of the bias current unit, and is also connected to the gate of the seventh NMOS transistor MN7 and the gate of the eighth NMOS transistor MN8, providing bias voltage and bias current for the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8.

[0119] The first source follower consists of transistors Q17 (seventeenth generation), Q19 (nineteenth generation), and MN7 (seventh generation NMOS transistor). The second source follower consists of transistors Q18 (eighteenth generation), Q20 (twenty-third generation), and MN8 (eighth generation NMOS transistor). The first and second source followers are connected using a cross-negative feedback configuration. The base of transistor Q17 serves as the input of the first source follower, and is also connected to the non-inverting output OUTP of the differential pair amplifier module and the collector of transistor Q19. The collector of transistor Q17 is connected to the power supply VCC. The emitter of transistor Q17 serves as the output mTIAoutp of the first source follower, and is also connected to the drain of NMOS transistor MN7 and the base of transistor Q19. The source of NMOS transistor MN7 is grounded. The emitter of transistor Q19 serves as the cross-negative feedback output of the first source follower, and is connected to the emitter of transistor Q18. The base of the eighteenth transistor Q18 serves as the input terminal of the second source follower, and is simultaneously connected to the inverting output terminal OUTN of the differential pair amplifier module and the collector of the twenty-third transistor Q20; the collector of the eighteenth transistor Q18 is connected to the power supply VCC; the emitter of the eighteenth transistor Q18 serves as the output terminal mTIAoutn of the second source follower, and is simultaneously connected to the drain of the eighth NMOS transistor MN8 and the base of the twenty-third transistor Q20; the source of the eighth NMOS transistor MN8 is grounded; the emitter of the twenty-third transistor Q20 serves as the cross-negative feedback output terminal of the second source follower, and is connected to the emitter of the seventeenth transistor Q17. In the above structure, the connection of transistors Q17 (17th generation) and Q19 (19th generation) forms a negative feedback loop, improving the stability of the output voltage signal of the first source follower: when the voltage at the input of the first source follower (i.e., the base of transistor Q17) rises, the voltage at the emitter of transistor Q17 (also the output of the first source follower) rises accordingly, and the base voltage of transistor Q19 also rises accordingly. This, in turn, causes the voltage at the collector of transistor Q19 (also the base of transistor Q17) to fall (transistor Q19 is connected as an inverting amplifier), which in turn causes the emitter voltage of transistor Q17 to fall. Similarly, the connection of transistors Q18 (18th generation) and Q20 (23rd generation) also forms a negative feedback loop, improving the stability of the output voltage signal of the second source follower.Furthermore, the cross-negative feedback connection of the first and second source followers improves the consistency of the output voltage signal mTIAoutp of the first source follower and the output voltage signal mTIAoutn of the second source follower: the voltage at the emitter of the seventeenth transistor Q17 (which is also the output mTIAoutp of the first source follower) rises, causing the base voltage of the nineteenth transistor Q19 to rise as well, which in turn causes the voltage at the emitter of the nineteenth transistor Q19 (which is also the cross-negative feedback output of the first source follower) to rise as well, which in turn causes the voltage at the emitter of the eighteenth transistor Q18 (which is also the output mTIAoutn of the second source follower) to rise along with the voltage at mTIAoutp.

[0120] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 3B As shown, the source follower unit may further include: a 21st transistor Q21, a 22nd transistor Q22, a 23rd transistor Q23, a 24th transistor Q24, a 9th NMOS transistor MN9, a 10th NMOS transistor MN10, an 11th NMOS transistor MN11, a 12th NMOS transistor MN12, a 13th NMOS transistor MN13, and a fourth current source Ib4.

[0121] The bias current unit consists of a fourth current source Ib4 and a ninth NMOS transistor MN9. The first terminal of the fourth current source Ib4 is connected to the power supply VCC, and the second terminal of the fourth current source Ib4 is connected to the drain and gate of the ninth NMOS transistor MN9. The source of the ninth NMOS transistor MN9 is grounded. The gate of the ninth NMOS transistor MN9 serves as the output terminal Ibias21 of the bias current unit, and is also connected to the gates of the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, and the thirteenth NMOS transistor MN13, providing bias voltage and bias current to the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, and the thirteenth NMOS transistor MN13. The first source follower consists of transistor Q21 (21st generation), transistor Q23 (23rd generation), NMOS transistor MN10 (10th generation), and NMOS transistor MN12 (12th generation). The base of transistor Q21 serves as the input of the first source follower, and is also connected to the non-inverting output OUTP of the differential pair amplifier module and the collector of transistor Q23. The collector of transistor Q21 is connected to the power supply VCC. The emitter of transistor Q21 serves as the output mTIAoutp of the first source follower, and is also connected to the drain of NMOS transistor MN10 and the base of transistor Q23. The source of NMOS transistor MN10 is grounded. The emitter of transistor Q23 is connected to the drain of NMOS transistor MN12. The source of NMOS transistor MN12 is grounded. The second source follower consists of transistors Q22 (22nd), Q24 (24th), MN11 (11th), and MN13 (13th). The base of transistor Q22 serves as the input of the second source follower, and is also connected to the inverting output OUTN of the differential pair amplifier module and the collector of transistor Q24. The collector of transistor Q22 is connected to the power supply VCC. The emitter of transistor Q22 serves as the output mTIAoutn of the second source follower, and is also connected to the drain of MN11 and the base of transistor Q24. The source of MN11 is grounded. The emitter of transistor Q24 is connected to the drain of MN13. The source of MN13 is grounded.In the above structure, the connection between transistors Q21 (21st generation) and Q23 (23rd generation) forms a negative feedback loop, improving the stability of the output voltage signal of the first source follower: when the voltage at the input of the first source follower (i.e., the base of transistor Q21) rises, the voltage at the emitter of transistor Q21 (also the output of the first source follower) rises accordingly, and the base voltage of transistor Q23 also rises accordingly. This, in turn, causes the voltage at the collector of transistor Q23 (also the base of transistor Q21) to fall (transistor Q23 is connected as an inverting amplifier), which in turn causes the emitter voltage of transistor Q21 to fall. Similarly, the connection between transistors Q22 (22nd generation) and Q24 (24th generation) also forms a negative feedback loop, improving the stability of the output voltage signal of the second source follower. Figure 3A compared to, Figure 3B The first and second source followers are independent of each other and do not use cross-negative feedback connection.

[0122] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 3C As shown, the source follower unit may further include: a 25th transistor Q25, a 26th transistor Q26, an 8th resistor R8, a 9th resistor R9, a 14th NMOS transistor MN14, a 15th NMOS transistor MN15, a 16th NMOS transistor MN16, and a 5th current source Ib5.

[0123] The bias current unit consists of a fifth current source Ib5 and a fourteenth NMOS transistor MN14. The first terminal of the fifth current source Ib5 is connected to the power supply VCC, and the second terminal of the fifth current source Ib5 is connected to the drain and gate of the fourteenth NMOS transistor MN14. The source of the fourteenth NMOS transistor MN14 is grounded. The gate of the fourteenth NMOS transistor MN14 serves as the output terminal Ibias21 of the bias current unit, and is also connected to the gate of the fifteenth NMOS transistor MN15 and the gate of the sixteenth NMOS transistor MN16, providing bias voltage and bias current for the fifteenth NMOS transistor MN15 and the sixteenth NMOS transistor MN16. The first source follower consists of the 25th transistor Q25, the 8th resistor R8, and the 15th NMOS transistor MN15. The base of the 25th transistor Q25 serves as the input terminal of the first source follower and is connected to the non-inverting output terminal OUTP of the differential pair amplifier module. The collector of the 25th transistor Q25 is connected to the power supply VCC. The emitter of the 25th transistor Q25 serves as the output terminal mTIAoutp of the first source follower and is connected to the first terminal of the 8th resistor R8. The second terminal of the 8th resistor R8 is connected to the drain of the 15th NMOS transistor MN15. The source of the 15th NMOS transistor MN15 is grounded. The second source follower consists of a 26th transistor Q26, a 9th resistor R9, and a 16th NMOS transistor MN16. The base of the 26th transistor Q26 serves as the input terminal of the second source follower and is connected to the inverting output terminal OUTN of the differential pair amplifier module. The collector of the 26th transistor Q26 is connected to the power supply VCC. The emitter of the 26th transistor Q26 serves as the output terminal mTIAoutn of the second source follower and is connected to the first terminal of the 9th resistor R9. The second terminal of the 9th resistor R9 is connected to the drain of the 16th NMOS transistor MN16. The source of the 16th NMOS transistor MN16 is grounded. Figure 3C and Figure 1 The difference in the circuit structure shown is that an eighth resistor R8 and a ninth resistor R9 are added. Their main function is to reduce the influence of the parasitic parameters of the fifteenth NMOS transistor MN15 and the sixteenth NMOS transistor MN16 on the bandwidth of the output terminal mTIAoutp of the first source follower and the output terminal mTIAoutn of the second source follower.

[0124] join Figure 4 As shown, this embodiment of the invention also provides a transimpedance amplifier, including the aforementioned transimpedance amplifier front-end circuit, and further including: a variable gain amplification unit, an output buffer unit, a DC-offset correction unit, and a signal strength detection and gain control signal generation unit.

[0125] The input terminal of the transimpedance amplifier front-end circuit is connected to the anode of an external photodetector PD, and the cathode of the photodetector PD is connected to a voltage source VPD. The non-inverting and inverting output terminals of the transimpedance amplifier front-end circuit are connected to the non-inverting and inverting input terminals of the variable gain amplifier unit, respectively.

[0126] The non-inverting and inverting output terminals of the variable gain amplifier unit are connected to the non-inverting and inverting input terminals of the output buffer unit.

[0127] The non-inverting and inverting output terminals of the output buffer unit serve as the non-inverting and inverting output terminals of the transimpedance amplifier, and are connected to the non-inverting and inverting input terminals of the DC-offset correction unit and the signal strength detection and gain control signal generation circuit.

[0128] The in-phase and out-of-phase output terminals of the DC-offset correction unit are connected to the DC-offset feedback differential input terminal of the variable gain amplifier unit.

[0129] The output of the signal strength detection and gain control signal generation unit is connected to the gain control input of the variable gain amplifier unit.

[0130] In the above structure, the signal strength detection and gain control signal generation unit adjusts and outputs the gain control signal Vgain in real time according to the monitored signal strength, thereby adjusting the gain of the variable gain amplifier unit in real time to keep the differential output signal of the transimpedance amplifier always in a linear state.

[0131] The invention will be further illustrated below with specific simulation examples. Figures 5A to 5G yes Figure 1 The transient simulation results of the front-end circuit of a transimpedance amplifier are shown.

[0132] in, Figure 5A The results are transient simulations with an average input current signal of 40µA and an extinction ratio of 4. The simulation duration is 150µs, and the operating speed is 25GBaud / s. Figure 5A In this diagram, Iinp is the input current signal, V(CEout) is the collector output voltage signal of the transistor connected to the input terminal of the single-ended amplifier unit, V(CECBout) is the output voltage signal of the single-ended amplifier unit, mTIAoutp is the non-inverting output voltage signal of the transimpedance amplifier front-end circuit, mTIAoutn is the inverting output voltage signal of the transimpedance amplifier front-end circuit, and (mTIAoutp-mTIAoutn) is the differential output signal of the transimpedance amplifier front-end circuit.

[0133] Depend on Figure 5AIt can be seen that in the initial stage, the DC voltage component of mTIAoutp is approximately 1.88V, and the DC voltage component of mTIAoutn is approximately 2.10V. After the first feedback and control unit detects the difference in the DC voltage components of mTIAoutp and mTIAoutn, it begins to adjust the feedback control signal VDFB output from its feedback terminal, thereby increasing the bias voltage signal output by the bias adjustment unit and the DC voltage component of the inverting input terminal INN of the differential pair amplifier module, which in turn decreases the DC voltage component of the inverting output terminal OUTN of the differential pair amplifier module, thus causing the DC voltage component of mTIAoutn to decrease accordingly; at the same time, the third feedback and control unit and the fourth feedback and control unit, based on the detected input terminal ( The signal information at the bias current terminal IB of the differential pair amplifier module also begins to decrease the feedback signals VIFB1 and VIFB2 output from its feedback terminal to adjust the current flowing through the fifth NMOS transistor MN5 and the third transistor Q3. That is, the DC current component in the input current signal Iinp flows to ground through the fifth NMOS transistor MN5 and the third transistor Q3, thereby extracting the DC current component in the input current signal Iinp. The decrease in VIFB1 and VIFB2 will increase the DC voltage component at the input terminal IN of the single-ended amplifier unit, and consequently decrease the output terminal OUT of the single-ended amplifier unit. Figure 5A The DC voltage component of CECBout (i.e., the non-inverting input terminal INP of the differential pair amplifier module) increases, which in turn increases the DC voltage component of the non-inverting output terminal OUTP of the differential pair amplifier module, leading to a corresponding increase in the DC voltage component of mTIAoutp. After approximately 5µs of adjustment, the DC voltage components of both mTIAoutp and mTIAoutn are adjusted to approximately 1.95V, achieving a state where their DC voltage components are approximately equal. Subsequently, the first, third, and fourth feedback and control units continue to adjust the magnitude of the feedback control signals output from their respective feedback terminals in real time based on the real-time monitored input signal information, maintaining the DC voltage components of mTIAoutp and mTIAoutn in a state of approximately equality.

[0134] Depend on Figure 5AIt is also known that: while the first feedback and control unit, the third feedback and control unit, and the fourth feedback and control unit are working, the signal amplitudes of the differential output pairs mTIAoutp and mTIAoutn are also changing accordingly. The process of this change is controlled by the second feedback and control unit: the second feedback and control unit outputs a feedback signal VAFB that changes in real time based on the difference in signal strength between mTIAoutp and mTIAoutn, and adjusts the gate voltage and current of the NMOS transistor MN1 in real time, that is, adjusts the bias current of the differential pair amplification module in real time, thereby changing the signal amplitudes of the output terminals OUTP and OUTN of the differential pair amplification module in real time, and thus adjusting the signal amplitudes of the differential output pairs mTIAoutp and mTIAoutn accordingly in real time; after about 45us, the signal amplitudes of mTIAoutp and mTIAoutn are basically in a state of approximately equalness.

[0135] After approximately 80µs, mTIAoutp and mTIAoutn reached a steady state, with both exhibiting a DC voltage component of approximately 1.87V (from...). Figure 5B (obtained), the signal amplitude of both is approximately 100mV (from Figure 5B The calculated amplitude is approximately 1.92V - 1.82V = 0.1V = 100mV, which achieves the goal of maintaining the DC voltage components and signal amplitudes of mTIAoutp and mTIAoutn at approximately equal levels.

[0136] Figure 5B yes Figure 5A The transient simulation waveform shown is the transient waveform in the range of 149.97µs to 150µs. Figure 5B It can be seen that the waveforms of the non-inverting output voltage signal mTIAoutp, the inverting output voltage signal mTIAoutn, and the differential output signal (mTIAoutp-mTIAoutn) in the embodiment of the linear transimpedance amplifier front-end circuit are completely consistent with the waveform of the input current signal Iinp, and no signal distortion occurs. The linear transimpedance amplifier front-end circuit realizes the complete linear conversion of the input current Iinp into the output voltage signal.

[0137] Figure 5C It is the cumulative superposition eye diagram of the input current signal Iinp in the range of 140us to 150us @ 25GBaud / s.

[0138] Figure 5D It is the cumulative superposition eye diagram of the output voltage signal V(CECBout) of the single-ended amplifier unit in the range of 140us to 150us @ 25GBaud / s.

[0139] Figure 5EIt is the cumulative superposition eye diagram of the non-inverting output voltage signal mTIAoutp in the range of 140us to 150us @ 25GBaud / s.

[0140] Figure 5F It is the cumulative superposition eye diagram of the inverted output voltage signal mTIAoutn in the range of 140us to 150us @ 25GBaud / s.

[0141] Figure 5G It is the cumulative superposition eye diagram of the differential output voltage signals (mTIAoutp-mTIAoutn) in the range of 140us to 150us @ 25GBaud / s.

[0142] Figure 6 yes Figure 1 The simulation results of the group delay of the front-end circuit of the transimpedance amplifier are shown.

[0143] Wherein, groupDelay(mTIAoutp), groupDelay(mTIAoutn), and groupDelay(mTIAoutp-mTIAoutn) are the group delay simulation results for the non-inverting output voltage signal mTIAoutp, the inverting output voltage signal mTIAoutn, and the differential output voltage signal (mTIAoutp-mTIAoutn), respectively. Figure 6 It can be seen that the output group delay of the transimpedance amplifier front-end circuit fluctuates very little in the range of 1GHz to 20GHz, within ±2ps.

[0144] Figures 7A to 7D yes Figure 1 The harmonic simulation results of the front-end circuit of the transimpedance amplifier shown are presented. Figure 7A The results are transient simulations of a sine wave with an amplitude of 20 uApp and a frequency of 1 GHz as the input current signal, with a simulation duration of 150 μs.

[0145] exist Figure 7A In this diagram, Iinp is the input current signal, V(CEout) is the collector output voltage signal of the transistor connected to the input terminal of the single-ended amplifier unit, V(CECBout) is the output voltage signal of the single-ended amplifier unit, mTIAoutp is the non-inverting output voltage signal of the transimpedance amplifier front-end circuit, mTIAoutn is the inverting output voltage signal of the transimpedance amplifier front-end circuit, and (mTIAoutp-mTIAoutn) is the differential output signal of the transimpedance amplifier front-end circuit.

[0146] Figure 7B yes Figure 7A The transient simulation waveform shown is the transient waveform in the range of 149.9us to 150us.

[0147] Figure 7C The result is the harmonic analysis of the cumulative signal of the input current signal Iinp in the range of 140us to 150us using the Hamming window.

[0148] Figure 7D The result is the harmonic analysis of the cumulative signal of the differential output voltage signal (mTIAoutp-mTIAoutn) in the range of 140us to 150us using the Hamming window.

[0149] In summary, the transimpedance amplifier front-end circuit in this embodiment of the invention employs a single-ended amplification unit and a differential pair amplification unit, along with a source follower unit, a first feedback and control unit, and a bias adjustment unit, directly achieving differential output. This eliminates the need for the single-ended to differential conversion circuit at the rear of existing transimpedance amplifier front-end circuits (based on single-ended input and single-ended output). Furthermore, this invention also includes a second feedback and control unit between the non-inverting and inverting output terminals of the transimpedance amplifier front-end circuit and the bias current control terminal of the differential pair amplification unit. This ensures that the output signal amplitudes of the non-inverting and inverting output terminals of the transimpedance amplifier front-end circuit linearly follow the input signal amplitude of the single-ended amplification unit, meeting the linear reception requirements in ultra-high-speed scenarios such as 50G PON.

[0150] It not only innovatively designs and adopts a single-ended input, differential output circuit structure, directly realizing differential output and eliminating the single-ended to differential circuit in the existing customer-side TIA structure (a TIA structure based on a single-ended input, single-ended output front-end circuit), thus achieving high-quality ultra-high-speed signal transmission; but also meets the 50Gbps linear TIA requirements for customer-side applications such as 50G PON, solving the problem that the current customer-side TIA clipping architecture does not meet the linear reception requirements in ultra-high-speed scenarios such as 50G PON.

[0151] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0152] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0153] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A front-end circuit for a transimpedance amplifier, characterized in that, include: Single-ended amplification unit, differential pair amplification unit, source follower unit, first feedback and control unit, second feedback and control unit, and bias adjustment unit; The input terminal of the single-ended amplifier unit is the input terminal of the transimpedance amplifier front-end circuit, and the output terminal of the single-ended amplifier is connected to the non-inverting input terminal of the differential pair amplifier unit. The non-inverting output terminal and the inverting output terminal of the differential pair amplifier unit are respectively connected to the first input terminal and the second input terminal of the source follower unit; The first output terminal of the source follower unit is the non-inverting output terminal of the transimpedance amplifier front-end circuit, and is connected to the non-inverting input terminal of the first feedback and control unit and the second feedback and control unit; the second output terminal of the source follower unit is the inverting output terminal of the transimpedance amplifier front-end circuit, and is connected to the inverting input terminal of the first feedback and control unit and the second feedback and control unit. The feedback terminal of the first feedback and control unit is connected to the input terminal of the bias adjustment unit, the output terminal of the bias adjustment unit is connected to the inverting input terminal of the differential pair amplification module, and the feedback terminal of the second feedback and control unit is connected to the bias current control terminal of the differential pair amplification unit. The first feedback and control unit is used to monitor the difference in DC components between the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier front-end circuit, and outputs a feedback control signal in real time at its feedback terminal according to the monitoring comparison result, thereby changing the bias voltage signal output by the bias adjustment unit, adjusting the DC voltage component of the inverting input terminal in the differential input pair of the differential pair amplifier unit in real time, thereby adjusting the DC voltage component of the inverting output terminal in the differential output pair of the differential pair amplifier unit, and thus adjusting the DC voltage component of the inverting output terminal in the differential output pair of the transimpedance amplifier front-end circuit. The second feedback and control unit is used to adjust the bias current of the differential pair amplifier unit by outputting a control signal at its feedback terminal based on the input signal information of its non-inverting input terminal and inverting input terminal, so that the output signal amplitude of the first output terminal and the second output terminal of the source follower unit is linearly related to the input signal amplitude of the input terminal of the single-ended amplifier unit.

2. The transimpedance amplifier front-end circuit according to claim 1, characterized in that: The differential pair amplification unit includes a differential pair amplification module, a first resistor, a second resistor, a third resistor, and a first NMOS transistor; The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to the non-inverting output terminal of the differential pair amplifier module and the first input terminal of the source follower unit. The first end of the second resistor is connected to the power supply, and the second end of the second resistor is connected to the inverting output terminal of the differential pair amplifier module and the second input terminal of the source follower unit. The in-phase input terminal of the differential pair amplifier module is connected to the output terminal of the single-ended amplifier unit; The first end of the third resistor is connected to the bias current terminal of the differential pair amplifier module, the second end of the third resistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to the feedback terminal of the second feedback and control unit.

3. The transimpedance amplifier front-end circuit according to claim 2, characterized in that: The first feedback and control unit includes a comparison and feedback control unit, a first low-pass filter, and a second low-pass filter; The input terminals of the first low-pass filter and the second low-pass filter are respectively the non-inverting input terminal and the inverting input terminal of the second feedback and control unit; The non-inverting input and inverting input of the comparison and feedback control unit are respectively connected to the output of the first low-pass filter and the output of the second low-pass filter. The output of the comparison and feedback control unit is the feedback terminal of the first feedback and feedback control unit.

4. The transimpedance amplifier front-end circuit according to claim 2, characterized in that: The source follower unit includes a bias current unit, a first source follower, and a second source follower; The power supply terminal of the bias current unit is connected to a power source. The input terminal of the first source follower is connected to the non-inverting output terminal of the differential pair amplifier module, the power supply terminal of the first source follower is connected to the power supply, the output terminal of the first source follower is the non-inverting output terminal of the transimpedance amplifier front-end circuit, and the bias current control terminal of the first source follower is connected to the output terminal of the bias current unit. The input terminal of the second source follower is connected to the inverting output terminal of the differential pair amplifier module, the power supply terminal of the second source follower is connected to the power supply, the output terminal of the second source follower is the inverting output terminal of the transimpedance amplifier front-end circuit, and the bias current control terminal of the second source follower is connected to the output terminal of the bias current unit.

5. The transimpedance amplifier front-end circuit according to claim 4, characterized in that: The bias current unit includes a first current source and a second NMOS transistor. The power supply terminal of the first current source is connected to a power supply, and the output terminal of the first current source is connected to the drain and gate of the second NMOS transistor to serve as the output terminal of the bias current unit. The first source follower includes a first transistor and a third NMOS transistor. The collector of the first transistor is connected to the power supply, the base of the first transistor is connected to the non-inverting output terminal of the differential pair amplifier module, the emitter of the first transistor is the non-inverting output terminal of the transimpedance amplifier front-end circuit and is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is the bias current control terminal of the first source follower. The second source follower includes a second transistor and a fourth NMOS transistor. The collector of the second transistor is connected to the power supply, the base of the second transistor is connected to the inverting output terminal of the differential pair amplifier module, the emitter of the second transistor is the inverting output terminal of the transimpedance amplifier front-end circuit and is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is the bias current control terminal of the second source follower. The gates of the third NMOS transistor and the fourth NMOS transistor are connected to the output terminal of the first current source and the gate of the second NMOS transistor, and the sources of the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are grounded.

6. The transimpedance amplifier front-end circuit according to claim 2, characterized in that, Also includes: A feedback resistor unit, wherein the first input terminal of the feedback resistor unit is connected to the bias current terminal of the differential pair amplifier module, and the feedback terminal of the feedback resistor unit is connected to the input terminal of the single-ended amplifier unit. The third feedback and control unit, wherein the input terminal of the third feedback and control unit is connected to the bias current terminal of the differential pair amplifier module; The fifth NMOS transistor has its drain connected to the input terminal of the single-ended amplifier unit, its gate connected to the feedback terminal of the third feedback and control unit, and its source grounded.

7. The transimpedance amplifier front-end circuit according to claim 6, characterized in that, Also includes: The fourth feedback and control unit, wherein the input terminal of the fourth feedback and control unit is connected to the bias current terminal of the differential pair amplification module; The third transistor has its collector connected to the input terminal of the single-ended amplifier unit, its base connected to the first feedback terminal of the fourth feedback and control unit, and its emitter grounded. The second feedback terminal of the fourth feedback and control unit is connected to the second input terminal of the feedback resistor unit.

8. The transimpedance amplifier front-end circuit according to claim 2, characterized in that: The differential pair amplification module includes a fourth transistor and a fifth transistor; The base of the fourth transistor is connected to the output of the single-ended amplifier unit as the non-inverting input of the differential pair amplifier module, and the collector of the fourth transistor is connected to the first input of the source follower unit as the non-inverting output of the differential pair amplifier module. The base of the fifth transistor is connected to the output of the bias adjustment unit as the inverting input of the differential pair amplification module, and the collector of the fifth transistor is connected to the second input of the source follower unit as the inverting output of the differential pair amplification module. The emitter of the fourth transistor is connected to the emitter of the fifth transistor as the bias current terminal of the differential pair amplifier module.

9. The transimpedance amplifier front-end circuit according to claim 1, characterized in that: The single-ended amplifier unit includes a sixth transistor and a fourth resistor; The base of the sixth transistor serves as the input terminal of the single-ended amplifier unit, the collector of the sixth transistor serves as the output terminal of the single-ended amplifier unit, and is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the power supply, and the emitter of the sixth transistor is grounded.

10. A transimpedance amplifier, characterized in that, The transimpedance amplifier front-end circuit according to any one of claims 1-9 further includes: a variable gain amplification unit, an output buffer unit, a DC-offset correction unit, and a signal strength detection and gain control signal generation unit; The non-inverting and inverting output terminals of the transimpedance amplifier front-end circuit are connected to the non-inverting and inverting input terminals of the variable gain amplifier unit. The non-inverting output terminal and the inverting output terminal of the variable gain amplifier unit are connected to the non-inverting input terminal and the inverting input terminal of the output buffer unit. The non-inverting output terminal and the inverting output terminal of the output buffer unit serve as the non-inverting output terminal and the inverting output terminal of the transimpedance amplifier, and are connected to the non-inverting input terminal and the inverting input terminal of the DC-offset correction unit and the signal strength detection and gain control signal generation circuit. The in-phase output and out-of-phase output of the DC-offset correction unit are connected to the DC-offset feedback differential input of the variable gain amplifier unit. The output of the signal strength detection and gain control signal generation unit is connected to the gain control input of the variable gain amplifier unit.

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