A low error rate asynchronous counter circuit for photon time of flight measurements

Abstract

The application discloses a low error code rate asynchronous counter circuit applied to a photon time of flight measurement, comprising a clock synchronization circuit, a delay matching chain 1, a delay matching chain 2 and a regression sampling asynchronous counter, and belongs to the technical field of single photon detection imaging; the low error code rate asynchronous counter can avoid the error code problem caused by the delay of the asynchronous counter itself under the condition of the increase of the counting bit width and the increase of the clock frequency, and can avoid the counting error code problem caused by the metastable state response of the D flip-flop; in addition, the application has the advantages of simple structure, strong migration and applicability to most TOF measurement circuits based on a phase-locked loop or a delay phase-locked loop.

Description

Technical Field

[0001] This invention relates to the field of lidar ranging technology, specifically to a low bit error rate asynchronous counter circuit applied to photon time-of-flight measurement. Background Technology

[0002] The time-of-flight (TOF) measurement circuit is a crucial component of pulsed lidar detectors, playing a decisive role in radar performance. Currently, TOF measurement circuits are primarily implemented using a time-to-digital converter (TDC), which quantizes analog time using discrete digital codes. TDC circuits are not only used in radar detection systems but also widely applied in other fields such as physical particle lifetime detection, automated detection equipment, and medical image scanning. Therefore, to meet the application needs of different fields, the structure of TDC circuits is becoming increasingly diversified.

[0003] TDC (Transient Distance Measurement) is divided into coarse timing and fine timing. Coarse timing typically uses a counter, while fine timing can utilize interpolation with a phase-splitting clock. However, due to the resolution and bit error rate issues of TDC, errors will occur during the ranging process. To address the resolution problem, a TDC with sub-gate delay or an interpolator can be used to improve resolution. Regarding bit error rate, since the coarse timing circuit plays a dominant role in ranging, measures must be taken to avoid bit errors. Coarse timing measurement circuits typically employ binary asynchronous counters, binary synchronous counters, and pseudo-random sequence counters based on linear feedback shift registers (LFSRs). Synchronous counters have all stages of flip-flops driven by the same clock, resulting in high operating speed due to simultaneous flip-flop switching. However, the output of a synchronous counter requires combinational logic circuitry to convert it into binary code. As the counting bit width increases, the transcoding circuit becomes more complex, leading to higher power consumption and larger circuit area, which in turn reduces the pixel fill factor. Pseudo-random sequence counters have the advantage of being easily configurable for serial data transmission, but their output counting sequence is not binary, requiring a lookup table to determine the corresponding count value. Traditional asynchronous counter circuits are simple in structure and low in power consumption. However, because the subsequent D flip-flops in an asynchronous counter are driven by the output of the previous stage instead of operating synchronously, the propagation delay increases with the increase of the counting bit width and clock frequency. In TDC circuits, this increased propagation delay can cause counting errors. Therefore, this invention proposes a novel asynchronous counter circuit structure to solve the bit error problem caused by the delay in asynchronous counters. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the above-mentioned problems, the present invention is proposed.

[0006] A first aspect of the present invention provides a low bit error rate asynchronous counter circuit for photon time-of-flight measurement, comprising a clock synchronization circuit, a delay matching chain 1, a delay matching chain 2, and a regression sampling asynchronous counter;

[0007] The clock synchronization circuit has its input terminal start connected to an external timing start signal start, its input terminal RST connected to an external reset signal RST, and its input terminal CLK_CNT connected to an external clock CLK_CNT. The clock synchronization circuit's output terminal CLK_OUT is connected to the input terminal CLK_1 of the delay matching chain 1 and the input terminal CLK of the regression sampling asynchronous counter.

[0008] The output terminal CLK of the delay matching chain 1 <0> ~CLK <n>The input terminal CK of the corresponding regression sampling asynchronous counter is connected. <0> ~CK <n>The output terminal CLK_full of the delay matching chain 1 is connected to the input terminal CK_full of the regression sampling asynchronous counter;

[0009] The input terminal stop of the delay matching chain 2 is connected to an external timing stop signal stop, and the output terminal stop of the delay matching chain 2 is connected to the external timing stop signal stop. <0> ~stop <n>The corresponding input terminal IN is connected to the asynchronous regression sampling counter. <0> ~IN <n>The output terminal stop_full of the delay matching chain 2 is connected to the input terminal IN_full of the regression sampling asynchronous counter;

[0010] The input terminal R of the regression sampling asynchronous counter is connected to an external reset signal RST, and the input terminal stop of the regression sampling asynchronous counter is connected to an external timing stop signal stop. The output terminal of the regression sampling asynchronous counter is DOUT. <0> ~DOUT <n>And CNT_full.

[0011] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, the clock synchronization circuit includes a NAND gate, two NOT gates INV1 and INV2, two buffers BufferA and BufferB, and four NOR gates NOR1, NOR2, NOR3, and NOR4.

[0012] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, it further includes:

[0013] The clock synchronization circuit has its input terminal RST connected to an external reset signal RST. The external reset signal RST is connected to the input terminal of NOT gate INV1. The output terminal of NOT gate INV1 is connected to one input terminal of NOR gate NOR2. The input terminal of NOR gate NOR1 is connected to an external timing start signal start and the output terminal of NOR gate NOR2. The output terminal of NOR gate NOR1 is connected to the other input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 is connected to the input terminal of buffer BufferA. The output terminal of buffer BufferA is connected to one input terminal of NAND gate NAND.

[0014] The input of NOR3 is connected to the external clock signal CLK_CNT and the GND signal. The output of NOR3 is connected to one input of NOR4. The other input of NOR4 is connected to the GND signal. The output of NOR4 is connected to the input of buffer B. The output of buffer B is connected to the other input of NAND.

[0015] The output of the NAND gate is connected to the input of the NOT gate INV2, and the output of the NOT gate INV2 is CLK_OUT.

[0016] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, wherein: the delay matching chain 1 includes buffers Buffer1 to Buffern and buffer_F;

[0017] The input of buffer Buffer1 is the CLK_1 signal. The output of buffer Buffer1 is connected to the input of buffer Buffer2. The output of buffer Buffer2 is connected to the input of buffer Buffer3, and so on. The output of buffer Buffern is connected to the input of buffer_F. The buffers are cascaded to form a delay matching chain 1.

[0018] The output of the delay matching chain 1 is CLK. <0> ~CLK <n>The signal and the CLK_full signal are used as the input clock for secondary sampling.

[0019] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, wherein: the delay matching chain 2 includes buffers Buffer1 to Buffern and buffer_F;

[0020] The input to buffer Buffer1 in the delay matching chain 2 is the timing stop signal (stop). The buffers are cascaded to form a delay matching chain 2, and the output of delay matching chain 2 is the stop signal. <0> ~stop <n>The signal and the stop_full signal serve as the input clock for the final output.

[0021] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, it includes:

[0022] The delay matching chain 1 and the delay matching chain 2 serve as the delay line for the synchronous clock signal CLK_OUT and the delay line for the timing stop signal, respectively, so that the timing start signal and the timing stop signal are sent to each D flip-flop for time synchronization.

[0023] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, the regression sampling asynchronous counter includes 3n+3 D flip-flops;

[0024] The asynchronous counter includes n+1 D flip-flops, namely D flip-flops DFF1~DFFn and D flip-flop DFFU. The regression sampling part includes 2n+2 D flip-flops, namely D flip-flops DFF_R1~DFF_Rn, D flip-flop DFF_RU, D flip-flops DFF_D1~DFF_D1 and D flip-flop DFF_DU.

[0025] As a preferred embodiment of the low bit error rate asynchronous counter circuit for photon time-of-flight measurement described in this invention, it further includes:

[0026] The input terminals Reset of D flip-flops DFF1 to DFFn are connected to the reset signal RST. The input terminal Clk of D flip-flop DFF1 is connected to the CLK signal. The input terminal D of D flip-flop DFF1 is connected to the input terminal Clk of D flip-flop DFF2. The input terminals Clk of D flip-flops DFF3 to DFFn are all connected to the input terminal D of the previous D flip-flop. The input terminal D of D flip-flop DFFU is connected to the power supply voltage VDD. The output terminals Q of D flip-flops DFF1 to DFFn and D flip-flop DFFU are correspondingly connected to the input terminals D of D flip-flops DFF_R1 to DFF_Rn and D flip-flop DFF_RU.

[0027] The input terminal Clk of the D flip-flops DFF_R1 to DFF_Rn is connected to the output terminal CLK of the delay matching chain 1. <0> ~CLK <n>The input terminal Clk of the D flip-flop DFF_RU is connected to the output terminal CLK_full of the delay matching chain 1. The input terminals Reset of the D flip-flops DFF_R1~DFF_Rn and D flip-flop DFF_RU are connected to the reset signal RST. The output terminals Q of the D flip-flops DFF_R1~DFF_Rn and D flip-flop DFF_RU are correspondingly connected to the input terminals D of the D flip-flops DFF_D1~DFF_D1 and D flip-flop DFF_DU.

[0028] The input terminals Reset of the D flip-flops DFF_D1 to DFF_D1 and DFF_DU are connected to the reset signal RST, and the input terminals Clk of the D flip-flops DFF_D1 to DFF_D1 and DFF_DU are correspondingly connected to the output terminal stop of the delay matching chain 2. <0> ~stop <n>And stop_full, the output signal of the D flip-flops DFF_D1~DFF_D1 and D flip-flop DFF_DU is DOUT. <0> ~DOUT <n>And CNT_full.

[0029] A second aspect of the present invention provides a low bit error rate asynchronous counter measurement method for photon time-of-flight measurement, comprising:

[0030] Before counting begins, the reset signal RST is set to 0, the output of the asynchronous counter is cleared to zero, and then the reset signal RST is set to 1, the asynchronous counter enters the counting state;

[0031] When the external timing start signal (start) and the reference clock signal (CLK_CNT) are input to the start and CLK_CNT terminals of the clock synchronization circuit, the clock synchronization circuit outputs a synchronization clock signal (CLK_OUT), which is provided to the input terminal (CLK_1) of the delay matching chain 1 and the input terminal (CLK) of the regression sampling asynchronous counter. The output terminal (CLK) of the delay matching chain 1... <0> ~CLK <n>CLK_full is connected to the input terminal CK of the regression sampling asynchronous counter. <0> ~CK <n>CK_full and CLK serve as the input clock signals for the regression sampling asynchronous counter, at which point the asynchronous counter begins counting;

[0032] The output terminal OUT of the asynchronous counter <0> ~OUT <n>The delay matched chain 1 is connected to the inputs D of the next-stage D flip-flops DFF_R1 to DFF_Rn and DFF_RU, and the output CLK is connected to the next-stage D flip-flop. <0> ~CLK <n>CLK_full is also connected to the input terminal CLK of the next-stage D flip-flops DFF_R1~DFF_Rn and DFF_RU. The next-stage D flip-flops first register the counting result, then perform a second sampling, and use the output result of the second sampling as the sample quantity of the final output.

[0033] As a preferred embodiment of the low bit error rate asynchronous counter measurement method for photon time-of-flight measurement described in this invention, it further includes:

[0034] The outputs of D flip-flops DFF_R1 to DFF_Rn and DFF_RU are connected to the inputs D of D flip-flops DFF_D1 to DFF_Dn and DFF_DU, respectively. An externally input stop signal is connected as a timing stop signal to the input stop of the delay matching chain 2. The output stop of the delay matching chain 2 is also connected to the delay matching chain 2. <0> ~stop <n>The corresponding input terminal Clk of D flip-flops DFF_D1~DFF_Dn and D flip-flop DFF_DU is connected to stop_full as the clock sampling signal for the final output result;

[0035] The output terminal of the delay matching chain 2 is stop <0> ~stop <n>Upon the arrival of the stop_full signal, the D flip-flops DFF_D1~DFF_Dn and DFF_DU sample the outputs of the D flip-flops DFF_R1~DFF_Rn and DFF_RU, and the final output is DOUT. <0> ~DOUT <n>and the CNT_full signal;

[0036] Final output result DOUT <0> ~DOUT <n>The binary code corresponds to the decimal value, which is the number of rising edges N of the synchronous clock CLK_OUT between start and stop. If the output of the CNT_full signal is high, it means that the measurement range exceeds the range and the measurement result must be discarded.

[0037] The beneficial effects of this invention are:

[0038] ①The regression sampling asynchronous counter method of the present invention is simple and easy to implement, and can effectively eliminate the bit error caused by asynchronous counter delay and D flip-flop metastability;

[0039] ② The asynchronous counter for coarse counting of TDC proposed in this invention has a wide range of applications. The number of bits can be changed according to one's own needs to achieve counting accuracy under different dynamic ranges. At the same time, the range of clock requirements is also very large. It is applicable to TDC ranging based on delay phase-locked loop (DLL) or phase-locked loop (PLL).

[0040] ③ The regression sampling asynchronous counter proposed in this invention can be widely used in various TDC time ranging applications, and has the advantages of high accuracy, low power consumption and strong portability. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0042] Figure 1 An overall circuit diagram of a low bit error rate asynchronous counter circuit for photon time-of-flight measurement provided by the present invention;

[0043] Figure 2 A schematic diagram illustrating the error generation caused by a conventional asynchronous counter in a low bit error rate asynchronous counter circuit for photon time-of-flight measurement, provided by this invention.

[0044] Figure 3 A clock synchronization circuit diagram for a low bit error rate asynchronous counter circuit applied to photon time-of-flight measurement provided by the present invention;

[0045] Figure 4 The circuit diagram of delay matching chain 1 of a low bit error rate asynchronous counter circuit for photon time-of-flight measurement provided by the present invention;

[0046] Figure 5 The circuit diagram of delay matching chain 2 of a low bit error rate asynchronous counter circuit for photon time-of-flight measurement provided by the present invention;

[0047] Figure 6 An asynchronous counter circuit diagram for a low bit error rate asynchronous counter circuit applied to photon time-of-flight measurement is provided for this invention;

[0048] Figure 7 A comparison of overall simulation results for a specific embodiment of a low bit error rate asynchronous counter circuit for photon time-of-flight measurement provided by the present invention;

[0049] Figure 8 The simulation comparison diagram shows a low bit error rate asynchronous counter circuit for photon time-of-flight measurement provided by the present invention, under different clock frequencies and different intervals between start and stop. Detailed Implementation

[0050] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0052] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0053] This invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of this invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0054] Furthermore, in the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0056] Example 1

[0057] Reference Figures 1-6 As one embodiment of the present invention, a low bit error rate asynchronous counter circuit for photon time-of-flight measurement is provided. The invention will be further described in detail below with reference to the accompanying drawings.

[0058] like Figure 2 As shown, this is the main reason why asynchronous counters are prone to bit errors during the counting process, and it is also the problem that this invention aims to solve. First, as... Figure 2 As shown in a), the asynchronous flip-flop is composed of multiple cascaded D flip-flops, therefore, D flip-flop metastability can occur. D flip-flop metastability refers to the fact that the time quantization of the digital time-diode (TDC) primarily determines time information by latching the signal at the stop of the timing using the D flip-flops. If, at the end of the timing, the output signal of the TDC does not meet the setup and hold times of the D flip-flops—that is, if changes occur within the window of the setup time (tsetup) and hold time (thold)—then metastability will occur in the D flip-flops. Figure 2 b) is the metastable timing diagram of the D flip-flop. Figure 2 a) During the level transition process of a digital circuit, there is a region that cannot be recognized by the circuit, called the metastable region. When metastability occurs, the output of the D flip-flop will oscillate for a period of time, and after the oscillation ends, it will randomly return to the "0" or "1" state, thus causing bit errors in the TDC. The metastability problem of the D flip-flop can be solved by registering a signal using a second D flip-flop. Secondly, because the subsequent D flip-flop of the asynchronous counter is driven by the output of the previous stage, rather than working synchronously, as the counting bit width increases, the propagation delay of the circuit becomes larger, and the operating speed is lower. In the TDC circuit, a large propagation delay can cause counting errors; for example... Figure 2 As shown in c), in practice, considering the delay issue, the data 100 may not appear when a certain clock rising edge arrives, resulting in data loss and thus bit errors. The regression sampling technique proposed in this paper can eliminate the bit error problem caused by asynchronous delay.

[0059] like Figure 1 As shown, this invention proposes a low bit error rate asynchronous counter circuit for photon time-of-flight measurement to address the impact of delays caused by traditional asynchronous counters in TDCs on the final count of bit errors. The circuit includes a clock synchronization circuit, a delay matching chain 1, a delay matching chain 2, and a regression sampling asynchronous counter.

[0060] Specifically, the clock synchronization circuit's input terminal `start` is connected to the external timing start signal `start`, its input terminal `RST` is connected to the external reset signal `RST`, and its input terminal `CLK_CNT` is connected to the external clock signal `CLK_CNT`. The clock synchronization circuit's output terminal `CLK_OUT` is connected to the input terminal `CLK_1` of delay matching chain 1 and the input terminal `CLK` of the regression sampling asynchronous counter; the output terminal `CLK` of delay matching chain 1... <0> ~CLK <n>The corresponding input terminal CK is connected to the regression sampling asynchronous counter. <0> ~CK <n>The output terminal CLK_full of delay matching chain 1 is connected to the input terminal CK_full of the regression sampling asynchronous counter; the input terminal stop of delay matching chain 2 is connected to the external timing stop signal, and the output terminal stop of delay matching chain 2 is connected to the external timing stop signal. <0> ~stop <n>The corresponding input terminal IN is connected to the regression sampling asynchronous counter. <0> ~IN <n>The output terminal stop_full of delay matching chain 2 is connected to the input terminal IN_full of the regression sampling asynchronous counter; the input terminal R of the regression sampling asynchronous counter is connected to the external reset signal RST, the input terminal stop of the regression sampling asynchronous counter is connected to the external timing stop signal stop, and the output terminal DOUT of the regression sampling asynchronous counter is connected to DOUT. <0> ~DOUT <n>and CNT_full;

[0061] It should be noted that the final output result is DOUT. <0> ~DOUT <n>The binary code corresponds to the decimal value, which is the number of rising edges N of the synchronous clock CLK_OUT between start and stop. The CLK_full and stop_full signals are also the last stage clock signals that reflect whether the counter is full or over the range. If the output of the CNT_full signal is high, it means that the measurement range exceeds the range and the measurement result must be discarded.

[0062] Furthermore, such as Figure 3 As shown, the clock synchronization circuit includes a NAND gate, two NOT gates INV1 and INV2, two buffers BufferA and BufferB, and four NOR gates NOR1, NOR2, NOR3, and NOR4.

[0063] Specifically, the clock synchronization circuit's input RST is connected to the external reset signal RST, which in turn is connected to the input of NOT gate INV1. The output of NOT gate INV1 is connected to one input of NOR gate NOR2. The input of NOR gate NOR1 is connected to the external timing start signal start and the output of NOR gate NOR2. The output of NOR gate NOR1 is connected to the other input of NOR gate NOR2. The output of NOR gate NOR2 is connected to the input of buffer BufferA. The output of buffer BufferA is connected to one input of NAND gate NAND. The input of NOR gate NOR3 is connected to the external clock signal CLK_CNT and the GND signal. The output of NOR gate NOR3 is connected to one input of NOR gate NOR4. The other input of NOR gate NOR4 is connected to the GND signal. The output of NOR gate NOR4 is connected to the input of buffer BufferB. The output of buffer BufferB is connected to the other input of NAND gate NAND. The output of NAND gate NAND is connected to the input of NOT gate INV2, and the output of NOT gate INV2 is CLK_OUT.

[0064] It should be noted that the clock synchronization circuit is used primarily to avoid the randomness of the start signal arrival. If the timing start signal happens to be aligned with the reference clock CLK_CNT signal, bit errors will occur. This is because the rising edge of the reference clock CLK_CNT signal arrives precisely at the moment the timing start signal flips from 0 to 1, resulting in uncertainty of either 0 or 1. Therefore, the clock synchronization circuit ensures that the timing start signal and the reference clock signal CLK_CNT become synchronized, thus avoiding the uncertainty of sampling at the arrival of the first rising edge of the clock.

[0065] Furthermore, such as Figure 4 As shown, delay matching chain 1 includes buffers Buffer1 to Buffern and buffer_F;

[0066] Specifically, the input of buffer Buffer1 is the CLK_1 signal. The output of buffer Buffer1 is connected to the input of buffer Buffer2, the output of buffer Buffer2 is connected to the input of buffer Buffer3, and so on. The output of buffer Buffern is connected to the input of buffer Buffer_F. These buffers are cascaded to form a delay matching chain 1. The output of delay matching chain 1 is CLK_1. <0> ~CLK <n>The signal and the CLK_full signal are used as the input clock for the second sampling;

[0067] Furthermore, such as Figure 5 As shown, delay matching chain 2 includes buffers Buffer1 to Buffern and buffer_F;

[0068] Specifically, the input to buffer Buffer1 in delay matching chain 2 is the timing stop signal. The buffers are cascaded to form delay matching chain 2, and the output of delay matching chain 2 is the stop signal. <0> ~stop <n>The signal and the stop_full signal serve as the input clock for the final output;

[0069] It should be noted that delay matching chain 1 and delay matching chain 2 serve as the delay lines for the synchronous clock signal CLK_OUT and the timing stop signal, respectively, ensuring that the timing start signal and timing stop signal are sent to each D flip-flop for time synchronization. At the same time, they also enhance the driving capability, effectively reduce clock signal jitter and noise, and ensure signal quality. In addition, CLK_full and stop_full are also the last stage clock signals that reflect whether the counter is full or over-range.

[0070] Furthermore, such as Figure 6 As shown, the regression sampling asynchronous counter includes 3n+3 D flip-flops, of which the asynchronous counter includes n+1 D flip-flops, namely D flip-flops DFF1~DFFn and D flip-flop DFFU. The regression sampling part includes 2n+2 D flip-flops, namely D flip-flops DFF_R1~DFF_Rn, D flip-flop DFF_RU, D flip-flops DFF_D1~DFF_D1 and D flip-flop DFF_DU.

[0071] Specifically, the Reset input of D flip-flops DFF1 to DFFn is connected to the reset signal RST; the Clk input of DFF1 is connected to the CLK signal; the D input of DFF1 is connected to the Clk input of DFF2; the Clk inputs of DFF3 to DFFn are all connected to the D input of the previous D flip-flop; the D input of DFU is connected to the power supply voltage VDD; the Q outputs of DFF1 to DFFn and DFU are connected to the D inputs of DFF_R1 to DFF_Rn and DFF_RU, respectively; and the Clk input of DFF_R1 to DFF_Rn is connected to the output CLK of delay matching chain 1. <0> ~CLK <n>The input Clk of D flip-flop DFF_RU is connected to the output CLK_full of delay matching chain 1. The input Reset of D flip-flops DFF_R1~DFF_Rn and DFF_RU is connected to the reset signal RST. The output Q of D flip-flops DFF_R1~DFF_Rn and DFF_RU is connected to the input D of D flip-flops DFF_D1~DFF_D1 and DFF_DU. The input Reset of D flip-flops DFF_D1~DFF_D1 and DFF_DU is connected to the reset signal RST. The input Clk of D flip-flops DFF_D1~DFF_D1 and DFF_DU is connected to the output stop of delay matching chain 2. <0> ~stop <n>The output signals of D flip-flops DFF_D1 to DFF_D1 and D flip-flop DFF_DU are DOUT. <0> ~DOUT <n>and CNT_full;

[0072] It should be noted that DOUT <0> ~DOUT <n>It is the final output of the regression sampling asynchronous counter. The output result is binary and corresponds to the number of clock rising edges N between start and stop. The total flight time TOF = N*T, where T refers to the period of clock CLK_CNT.

[0073] A second aspect of the present invention provides a low bit error rate asynchronous counter measurement method for photon time-of-flight measurement, comprising:

[0074] Before counting begins, the reset signal RST is set to 0, clearing the output of the asynchronous counter. Then, the reset signal RST is set to 1, and the asynchronous counter enters the counting state. When the external timing start signal and the reference clock signal CLK_CNT are input to the start and CLK_CNT terminals of the clock synchronization circuit, the clock synchronization circuit outputs a synchronous clock signal CLK_OUT, which is provided to the input terminal CLK_1 of delay matching chain 1 and the input terminal CLK of the regression sampling asynchronous counter. The output terminal CLK of delay matching chain 1... <0> ~CLK <n>CLK_full is connected to the input terminal CK of the regression sampling asynchronous counter. <0> ~CK <n>CK_full and CLK serve as the input clock signals for the regression sampling asynchronous counter, at which point the asynchronous counter begins counting; the output terminal OUT of the asynchronous counter... <0> ~OUT <n>The inputs D of the D flip-flops DFF_R1 to DFF_Rn and DFF_RU of the next stage are connected to FULL, and the output CLK of the delay matched chain 1 is connected to FULL. <0> ~CLK <n>The CLK_full signal is also connected to the input CLK of the next-stage D flip-flops DFF_R1~DFF_Rn and DFF_RU. The next-stage D flip-flops first register the counting result, then perform a second sampling, and use the output of the second sampling as the final output sample. This can avoid the bit errors caused by the delay problem of the asynchronous counter. In addition, it can also solve the metastability problem of D flip-flops and the bit errors caused by insufficient setup and hold times. The outputs of D flip-flops DFF_R1~DFF_Rn and DFF_RU are connected to the inputs D of D flip-flops DFF_D1~DFF_Dn and DFF_DU, respectively. The externally input stop signal is connected as the timing stop signal to the input stop of delay matching chain 2, and the output stop of delay matching chain 2 is also connected. <0> ~stop <n>The stop_full signal is connected to the input Clk of D flip-flops DFF_D1~DFF_Dn and D flip-flop DFF_DU, respectively, as the clock sampling signal for the final output; the output stop of delay matching chain 2... <0> ~stop <n>After the stop_full signal arrives, D flip-flops DFF_D1~DFF_Dn and DFF_DU sample the outputs of D flip-flops DFF_R1~DFF_Rn and DFF_RU, and the final output is DOUT. <0> ~DOUT <n>And the CNT_full signal, the final output result is DOUT. <0> ~DOUT <n>The binary code corresponds to the decimal value, which is the number of rising edges N of the synchronous clock CLK_OUT between start and stop. If the output of the CNT_full signal is high, it means that the measurement range exceeds the range and the measurement result must be discarded.

[0075] It should be noted that: ① The regression sampling asynchronous counter method of the present invention is simple and easy to implement, and can effectively eliminate the influence of asynchronous counter delay and D flip-flop metastability on bit errors; ② The asynchronous counter proposed in this invention for TDC coarse counting has a wide range of applications. The number of bits can be changed according to needs to achieve counting accuracy under different dynamic ranges. At the same time, the clock requirement range is also very large, and it is applicable to both TDC ranging based on delay phase-locked loop (DLL) and phase-locked loop (PLL); ③ The regression sampling asynchronous counter proposed in this invention can be widely used in various TDC time ranging applications, and has the advantages of high accuracy, low power consumption and strong portability.

[0076] Example 2

[0077] Reference Figures 7-8 This is a second embodiment of the present invention, which differs from the first embodiment in that it provides a verification test for a low bit error rate asynchronous counter circuit applied to photon time-of-flight measurement, to verify and explain the technical effects used in this method.

[0078] This embodiment uses a 9-bit asynchronous counter. Only the accuracy of the final count is listed when the clock frequency is 200MHz, 800MHz and 1GHz, and the start and stop time interval is 100ns and 210ns.

[0079] Taking a 9-bit asynchronous counter with a clock frequency of 1GHz as an example, this embodiment proposes to compare the overall simulation results of a low bit error rate asynchronous counter with the results of a traditional asynchronous counter. The results are as follows: Figure 7 As shown, given a time difference of 100ns between start and stop, the final output is DOUT. <0> ~DOUT <8> The corresponding binary bit is 001100100, and the corresponding decimal value is 100. That is, the number of rising edges N = 100. The period corresponding to the 1GHz frequency is 1ns, so TOF = 100 * 1ns = 100ns, which is the same as the given value, and the counting function is correct.

[0080] The following is a simulation comparison of asynchronous counters using regression sampling technology and ordinary asynchronous counters under different clock frequencies and with different intervals between start and stop, as shown in the figure. Figure 8 As shown, the counting is initially performed at a 200MHz clock speed, with a 100ns interval between start and stop. From... Figure 8 As can be seen, the binary output of a normal asynchronous counter is 000010101, corresponding to a decimal value of 21, which is the number of rising edges N (only the decimal result is shown here for ease of observation). The period corresponding to 200MHz is 5ns, so TOF = 21 * 5ns = 105ns. It can be seen that the delay of the asynchronous counter causes bit errors, leading to a final counting error that deviates from the actual value by 1 LSB. This is a significant error for laser ranging based on TDC, and therefore must be avoided. Below is an asynchronous counter using the regression sampling technology of this invention. It can be seen that the binary output of the counter is 000010100, corresponding to a decimal value of 20, which is the number of rising edges N. Therefore, the measured total TOF = 20 * 5ns = 100ns, which matches the actual value. This shows that the circuit provided by this invention effectively solves the problem of asynchronous counter delay bit errors.

[0081] Next, we change the clock frequency to 800MHz, while keeping the start and stop interval at 100ns. We can then see the binary output DOUT of the ordinary asynchronous counter. <0> ~DOUT <8> The value is 001010001, corresponding to a decimal value of 81, which represents the number of rising edges N (only the decimal result is shown). The period corresponding to 800MHz is 1.25ns, so TOF = 81 * 1.25ns = 101.25ns. It can be seen that the delay of the asynchronous counter causes bit errors, resulting in a final count error that deviates from the actual value by 1 LSB. Below is the output result of the asynchronous counter using regression sampling technology. It can be seen that the binary output DOUT of the counter... <0> ~DOUT <8> The value is 001010000, which corresponds to the decimal value 80, representing the number of rising edges N. Therefore, the measured total TOF is 80 * 1.25 ns = 100 ns, which matches the actual value.

[0082] By changing the clock frequency to 1GHz and the interval between start and stop to 210ns, it can be seen that the binary output DOUT of the ordinary asynchronous counter... <0> ~DOUT <8> The value is 011010011, corresponding to a decimal value of 2^11, which represents the number of rising edges, N. Only the decimal result is shown. 1 GHz corresponds to a period of 1 ns, so TOF = 2^11 * 1 ns = 2^11 ns. It can be seen that the delay of the asynchronous counter causes bit errors, resulting in a final count error that deviates from the actual value by 1 LSB. Comparing this with the output of the asynchronous counter using regression sampling technology, we can see that the binary output DOUT of the counter... <0> ~DOUT <8> The value is 011010010, which corresponds to a decimal value of 210, representing the number of rising edges N. Therefore, the measured total TOF is 210 * 1ns = 210ns, which matches the actual value.

[0083] In summary, taking a 9-bit asynchronous counter as an example, the clock operating frequency range is 0-1GHz, and the number of counter bits is determined by both the dynamic range and the clock frequency. Simulation results show that the low bit error rate asynchronous counter proposed in this paper can avoid bit errors caused by asynchronous counter delay and bit errors caused by metastability of D flip-flops.

[0084] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A low bit error rate asynchronous counter circuit for photon time-of-flight measurement, characterized in that, It includes a clock synchronization circuit, delay matching chain 1, delay matching chain 2, and a regression sampling asynchronous counter; The clock synchronization circuit has its input terminal start connected to an external timing start signal start, its input terminal RST connected to an external reset signal RST, and its input terminal CLK_CNT connected to an external clock CLK_CNT. The clock synchronization circuit's output terminal CLK_OUT is connected to the input terminal CLK_1 of the delay matching chain 1 and the input terminal CLK of the regression sampling asynchronous counter. The output terminal CLK of the delay matching chain 1 <0> ~CLK <n>The input terminal CK of the corresponding regression sampling asynchronous counter is connected. <0> ~CK <n> The output terminal CLK_full of the delay matching chain 1 is connected to the input terminal CK_full of the regression sampling asynchronous counter;< / n> < / n> The input terminal stop of the delay matching chain 2 is connected to an external timing stop signal stop, and the output terminal stop of the delay matching chain 2 is connected to an external timing stop signal stop. <0> ~stop <n>The corresponding input terminal IN is connected to the asynchronous regression sampling counter. <0> ~IN <n> The output terminal stop_full of the delay matching chain 2 is connected to the input terminal IN_full of the regression sampling asynchronous counter;< / n> < / n> The input terminal R of the regression sampling asynchronous counter is connected to an external reset signal RST, and the input terminal stop of the regression sampling asynchronous counter is connected to an external timing stop signal stop. The output terminal of the regression sampling asynchronous counter is DOUT. <0> ~DOUT <n> and CNT_full;< / n> The regression sampling asynchronous counter includes 3n+3 D flip-flops; The asynchronous counter includes n+1 D flip-flops, namely D flip-flops DFF1~DFFn and D flip-flops DFFU, and the regression sampling part includes 2n+2 D flip-flops, namely D flip-flops DFF_R1~DFF_Rn, D flip-flops DFF_RU, D flip-flops DFF_D1~DFF_Dn and D flip-flops DFF_DU. The input terminals Reset of D flip-flops DFF1~DFFn are connected to the reset signal RST. The input terminal Clk of D flip-flop DFF1 is connected to the CLK signal. The input terminal D of D flip-flop DFF1 is connected to the input terminal Clk of D flip-flop DFF2. The input terminals Clk of D flip-flops DFF3~DFFn are all connected to the input terminal D of the previous D flip-flop. The input terminal D of D flip-flop DFFU is connected to the power supply voltage VDD. The output terminals Q of D flip-flops DFF1~DFFn and D flip-flop DFFU are correspondingly connected to the input terminals D of D flip-flops DFF_R1~DFF_Rn and D flip-flop DFF_RU. The input terminal Clk of the D flip-flops DFF_R1~DFF_Rn is connected to the output terminal CLK of the delay matching chain 1. <0> ~CLK <n> The input terminal Clk of the D flip-flop DFF_RU is connected to the output terminal CLK_full of the delay matching chain 1. The input terminals Reset of the D flip-flops DFF_R1~DFF_Rn and DFF_RU are connected to the reset signal RST. The output terminals Q of the D flip-flops DFF_R1~DFF_Rn and DFF_RU are correspondingly connected to the input terminals D of the D flip-flops DFF_D1~DFF_Dn and DFF_DU.< / n> The input terminals Reset of the D flip-flops DFF_D1~DFF_Dn and DFF_DU are connected to the reset signal RST, and the input terminals Clk of the D flip-flops DFF_D1~DFF_Dn and DFF_DU are correspondingly connected to the output terminal stop of the delay matching chain 2. <0> ~stop <n>And stop_full, the output signal of the D flip-flops DFF_D1~DFF_Dn and D flip-flop DFF_DU is DOUT. <0> ~DOUT <n> And CNT_full.< / n> < / n> 2. The low bit error rate asynchronous counter circuit for photon time-of-flight measurement as described in claim 1, characterized in that: The clock synchronization circuit includes a NAND gate, two NOT gates INV1 and INV2, two buffers BufferA and BufferB, and four NOR gates NOR1, NOR2, NOR3, and NOR4.

3. The low bit error rate asynchronous counter circuit for photon time-of-flight measurement as described in claim 2, characterized in that: It also includes, The clock synchronization circuit has its input terminal RST connected to an external reset signal RST. The external reset signal RST is connected to the input terminal of NOT gate INV1. The output terminal of NOT gate INV1 is connected to one input terminal of NOR gate NOR2. The input terminal of NOR gate NOR1 is connected to an external timing start signal start and the output terminal of NOR gate NOR2. The output terminal of NOR gate NOR1 is connected to the other input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 is connected to the input terminal of buffer BufferA. The output terminal of buffer BufferA is connected to one input terminal of NAND gate NAND. The input of NOR3 is connected to the external clock signal CLK_CNT and the GND signal. The output of NOR3 is connected to one input of NOR4. The other input of NOR4 is connected to the GND signal. The output of NOR4 is connected to the input of buffer B. The output of buffer B is connected to the other input of NAND. The output of the NAND gate is connected to the input of the NOT gate INV2, and the output of the NOT gate INV2 is CLK_OUT.

4. The low bit error rate asynchronous counter circuit for photon time-of-flight measurement as described in claim 1, characterized in that: The delay matching chain 1 includes buffers Buffer1~Buffern and buffer_F; The input of buffer Buffer1 is the CLK_1 signal. The output of buffer Buffer1 is connected to the input of buffer Buffer2. The output of buffer Buffer2 is connected to the input of buffer Buffer3, and so on. The output of buffer Buffern is connected to the input of buffer_F. The buffers are cascaded to form a delay matching chain 1. The output of the delay matching chain 1 is CLK. <0> ~CLK <n> The signal and the CLK_full signal are used as the input clock for secondary sampling.< / n> 5. The low bit error rate asynchronous counter circuit for photon time-of-flight measurement as described in claim 4, characterized in that: The delay matching chain 2 includes buffers Buffer1~Buffern and Buffer_F buffer; The input to buffer Buffer1 in the delay matching chain 2 is the timing stop signal (stop). The buffers are cascaded to form a delay matching chain 2, and the output of delay matching chain 2 is the stop signal. <0> ~stop <n> The signal and the stop_full signal serve as the input clock for the final output.< / n> 6. The low bit error rate asynchronous counter circuit for photon time-of-flight measurement as described in claim 5, characterized in that: include, The delay matching chain 1 and the delay matching chain 2 serve as the delay line for the synchronous clock signal CLK_OUT and the delay line for the timing stop signal, respectively, so that the timing start signal and the timing stop signal are sent to each D flip-flop for time synchronization.

7. A method for using a low bit error rate asynchronous counter circuit for photon time-of-flight measurement based on any one of claims 1 to 6, characterized in that, include: Before counting begins, the reset signal RST is set to 0, the output of the asynchronous counter is cleared to zero, and then the reset signal RST is set to 1, the asynchronous counter enters the counting state; When the external timing start signal (start) and the reference clock signal (CLK_CNT) are input to the start and CLK_CNT terminals of the clock synchronization circuit, the clock synchronization circuit outputs a synchronization clock signal (CLK_OUT), which is provided to the input terminal (CLK_1) of the delay matching chain 1 and the input terminal (CLK) of the regression sampling asynchronous counter. The output terminal (CLK) of the delay matching chain 1... <0> ~CLK <n>CLK_full is connected to the input terminal CK of the regression sampling asynchronous counter. <0> ~CK <n> CK_full and CLK serve as the input clock signals for the regression sampling asynchronous counter, at which point the asynchronous counter begins counting;< / n> < / n> The output terminal OUT of the asynchronous counter <0> ~OUT <n>The delay matched chain 1 is connected to the inputs D of the next-stage D flip-flops DFF_R1~DFF_Rn and DFF_RU, and the output CLK is connected to the next-stage D flip-flop. <0> ~CLK <n> CLK_full is also connected to the input terminal CLK of the next-level D flip-flops DFF_R1~DFF_Rn and DFF_RU. The next-level D flip-flops first register the counting result, then perform a second sampling, and use the output result of the second sampling as the sample quantity of the final output.< / n> < / n> 8. The low bit error rate asynchronous counter measurement method for photon time-of-flight measurement as described in claim 7, characterized in that: It also includes, The outputs of D flip-flops DFF_R1~DFF_Rn and DFF_RU are connected to the inputs D of D flip-flops DFF_D1~DFF_Dn and DFF_DU, respectively. An externally input stop signal is connected as a timing stop signal to the input stop of the delay matching chain 2. The output stop of the delay matching chain 2 is also connected to the delay matching chain 2. <0> ~stop <n>The corresponding input terminal Clk of D flip-flops DFF_D1~DFF_Dn and D flip-flop DFF_DU is connected to stop_full as the clock sampling signal for the final output result;< / n> The output terminal of the delay matching chain 2 is stop <0> ~stop <n>Upon the arrival of the stop_full signal, the D flip-flops DFF_D1~DFF_Dn and DFF_DU sample the outputs of the D flip-flops DFF_R1~DFF_Rn and DFF_RU, and the final output is DOUT. <0> ~DOUT <n> and the CNT_full signal;< / n> < / n> Final output result DOUT <0> ~DOUT <n> The binary code corresponds to the decimal value, which is the number of rising edges N of the synchronous clock CLK_OUT between start and stop. If the output of the CNT_full signal is high, it means that the measurement range exceeds the range and the measurement result must be discarded.< / n>

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