Reference level generation circuit and method for generating reference level in analog-to-digital converters

Abstract

This application relates to a reference level generation circuit and a method for generating a reference level in an analog-to-digital converter (ADC). The reference level generation circuit includes a charge pump, a control voltage generation unit, and a transmission unit. The charge pump is connected to the control voltage generation unit to provide an enable voltage to the control voltage generation unit. The control voltage generation unit is connected to the transmission unit to provide a control voltage to the transmission unit. The transmission unit is connected to the comparator of the ADC to provide a reference level to the comparator. According to the scheme of this application, during the sampling phase, the reference level generation circuit provides common-mode levels to the positive and negative terminals of the comparator respectively, and controls whether to provide a reference level to the positive and negative terminals of the comparator via a switch. Its internal resistance is relatively constant, which improves the linearity of the ADC, thereby improving the ADC performance. Furthermore, it solves the problems of charge injection and reduces clock feedthrough effects.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a reference level generation circuit and a method for generating a reference level in an analog-to-digital converter. Background Technology

[0002] Successive approximation analog-to-digital converters (ADCs) are used for medium-to-high precision applications with low to medium sampling rates. Due to their advantages such as simple structure, small size, and low power consumption, they have a wide range of applications, including portable instruments, pen input quantizers, industrial control, and data / signal acquisition.

[0003] To achieve analog-to-digital conversion, existing solutions include... Figure 1 As shown. In Figure 1 In this diagram, the analog-to-digital converter (ADC) is a three-bit ADC. The ADC includes a digital-to-analog converter (DAC), a comparator (COMP), and successive approximation logic (SAR_LOGIC). The DAC includes capacitors C1, C2, C3, and C4. The DAC has N-terminals and P-terminals, with a switch S1 between them.

[0004] In the sampling phase, the digital-to-analog converter (DAC) is used to sample the input voltage, and in the comparison phase, it provides the input voltage for the comparator. The comparator is used to compare the output voltage of the DAC with the reference voltage and output the comparison result. The successive approximation logic is used to receive the output result of the comparator, instruct the DAC to modify the output voltage according to the result, and output the result of the analog-to-digital converter.

[0005] like Figure 1 As shown, V IN V REF GND and GND represent the analog input voltage, reference voltage, and ground, respectively. Assume V IN =V REF During the sampling phase, the digital-to-analog converter (DAC) performs the sampling. The N terminal of the DAC is connected to GND, and the positive plate of the capacitor array is connected to the input signal V. IN After sampling, the N terminal of the digital-to-analog converter (DAC) is disconnected from GND, and the positive plate of the capacitor array is connected to V. IN After disconnecting the capacitors, a weighted charge of the input voltage is obtained on the capacitor array. Then, the positive plates of all capacitors are connected to GND, making the N-terminal of the digital-to-analog converter (DAC) a negative voltage -V. REF As the first step in the successive approximation algorithm, the positive plate of capacitor C1 is disconnected from GND and connected to V. REF This causes the voltage at the N-terminal of the digital-to-analog converter (DAC) to increase by (1 / 2)V. REF , is -(1 / 2)V REFThis voltage is compared with the GND potential, and the comparator output is logic 1. Through successive approximation logic, capacitor C1 is kept connected to V. REF Then disconnect capacitor C2 from GND and connect it to V. REF This causes the N-terminal voltage of the digital-to-analog converter (DAC) to increase by (1 / 4)V. REF , is -(1 / 4)V REF This voltage is compared with the GND potential, and the comparator output is logic 1. Through successive approximation logic, capacitor C2 is also kept connected to V. REF Then disconnect capacitor C3 from GND and connect it to V. REF And so on, until the analog level V is reached. REF Convert the digital level to 111 and output it. Summary of the Invention

[0006] The analog-to-digital converter (ADC) circuits described above can convert analog signals to digital signals. However, a major problem is that the voltage at the N-terminal of the comparator is constantly changing due to external interference. For switch S1, its on-resistance is a function of the overdrive voltage, and this on-resistance also changes continuously during sampling, affecting the linearity of the ADC. Furthermore, the sampling process is also affected by non-ideal factors such as clock feedthrough and channel charge injection. Existing ADC circuits cannot overcome these problems to achieve optimal performance.

[0007] Based on this, this application provides a reference level generation circuit that can be used in an analog-to-digital converter (ADC). During the sampling phase, the reference level generation circuit provides common-mode levels to the positive and negative terminals of the comparator, and controls whether to provide a reference level switch to the positive and negative terminals of the comparator. Its internal resistance is relatively constant, which improves the linearity of the ADC and thus enhances its performance.

[0008] According to a first aspect of this application, a reference level generation circuit for an analog-to-digital converter is provided, comprising: a charge pump, a control voltage generation unit, and a transmission unit, wherein:

[0009] A charge pump is connected to the control voltage generating unit and is used to provide an activation voltage to the control voltage generating unit;

[0010] The control voltage generating unit and the transmission unit are used to provide control voltage to the transmission unit;

[0011] The transmission unit is connected to the comparator of the analog-to-digital converter and is used to provide a reference level for the comparator.

[0012] According to a second aspect of this application, a method for generating a reference level according to the reference level generating circuit of the first aspect is provided, comprising:

[0013] The charge pump provides an activation voltage to the control voltage generating unit;

[0014] In response to the turn-on voltage, the control voltage generating unit provides a control voltage to the transmission unit; and

[0015] In response to the control voltage, the transmission unit provides a reference level for the comparator of the analog-to-digital converter. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings, without exceeding the scope of protection claimed by this application.

[0017] Figure 1 This is a schematic diagram of the circuit structure of an analog-to-digital converter in the prior art.

[0018] Figure 2 This is a schematic diagram of a reference level generation circuit applied to an analog-to-digital converter according to an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the reference level generation circuit according to an embodiment of this application.

[0020] Figure 4 This is a flowchart of a method for generating a reference level according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Figure 2 This is a schematic diagram illustrating the application of a reference level generation circuit to an analog-to-digital converter according to an embodiment of this application. Figure 1 The difference is, Figure 2 It also includes the reference level generation circuit VCM_GEN. For example... Figure 2 As shown, the N terminal of the reference level generation circuit is connected to the negative plate of the DAC capacitor array and the negative terminal of the comparator COMP, while the P terminal of the reference level generation circuit is connected to the positive terminal of the comparator COMP.

[0023] Figure 3 This is a schematic diagram of the reference level generation circuit according to an embodiment of this application. Figure 3 As shown, the reference level generation circuit includes a charge pump 100, a control voltage generation unit 200, and a transmission unit 300. The charge pump 100 is connected to the control voltage generation unit 200 and is used to provide a turn-on voltage. The control voltage generation unit 200 is connected to the charge pump 100 and the transmission unit 300. Using the turn-on voltage provided by the charge pump, it attempts to provide the transmission unit 300 with a voltage that is always higher than the common-mode level VCM generated by the reference level generation circuit by a fixed level, and then provides the voltage to the transmission unit 300. The transmission unit 300 is connected to the control voltage generation circuit 200 and is used to provide the common-mode level VCM (i.e., the reference voltage) generated by the reference level generation circuit to the positive and negative inputs of the comparator.

[0024] exist Figure 3 In the charge pump 100, a first NMOS transistor NM1, a second NMOS transistor NM2, a first capacitor C1, a second capacitor C2, and an inverter INV1 are included. The source of the first NMOS transistor NM1 is connected to the power supply VDD, and its gate is connected to the drain of the second NMOS transistor NM2 and the positive plate of the second capacitor C2. The drain of the first NMOS transistor NM1 is connected to the positive plate of the first capacitor C1, the gate of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3 of the control voltage generation unit 200. The source of the second NMOS transistor NM2 is connected to the power supply VDD, and its gate is connected to the positive plate of the first capacitor C1. The drain of the first NMOS transistor NM1 and the gate of the third NMOS transistor NM3 of the control voltage generation unit 200 are connected. The drain is connected to the positive plate of the second capacitor C2 and the gate of the first NMOS transistor NM1. The positive plate of the first capacitor C1 is connected to the drain of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3 of the control voltage generation unit 200. The negative plate of the first capacitor C1 is connected to the clock signal CK and the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the negative plate of the second capacitor C2.

[0025] The charge pump 100 provides a turn-on voltage to the reference level generation unit 200, which must at least reach the level of the NMOS transistor in the control voltage generation unit 200 that receives the turn-on voltage. Figure 3 The source voltage of the third NMOS transistor (NM3) in the control voltage generation unit 200 is the sum of its source voltage and VTH, where VTH is the threshold voltage of the MOS transistor. This is necessary to turn on the third NMOS transistor NM3. Typically, this turn-on voltage is close to twice the power supply voltage VDD.

[0026] exist Figure 3In the control voltage generation unit 200, there are a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a first PMOS transistor PM1, a second PMOS transistor PM2, a third capacitor C3, a first resistor R1, and a second resistor R2. In this configuration, the source of the third NMOS transistor NM3 is connected to the power supply VDD, and its gate is connected to the drain of the first NMOS transistor NM1 in the charge pump 100 and the positive plate of the third capacitor C3. Its drain is connected to the source of the second PMOS transistor PM2. The source of the fourth NMOS transistor NM4 is connected to the negative plate of the third capacitor C3, the drain of the ninth NMOS transistor NM9, the source of the fifth NMOS transistor NM5, and the source of the sixth NMOS transistor NM6. Its gate is connected to the input signal CK_NN, and its drain is grounded. The source of the fifth NMOS transistor NM5 is connected to the negative plate of the third capacitor C3, the source of the fourth NMOS transistor NM4, and the source of the sixth NMOS transistor NM6. The source of NMOS transistor NM6 and the drain of NMOS transistor NM9 are connected. The gate of NMOS transistor NM9 is connected to the drain of PMOS transistor PM2, the source of PMOS transistor NM7, and the gate of PMOS transistor PM2. The drain of NMOS transistor NM9 is connected to the drain of PMOS transistor NM6, the drain of PMOS transistor PM1, and the gate of PMOS transistor PM2. The source of PMOS transistor NM6 is connected to the negative plate of capacitor C3, the source of NMOS transistor NM4, the source of NMOS transistor NM5, and the drain of NMOS transistor NM9. The gate input signal is CK_NNN. The drain is connected to the fifth... The drain of NMOS transistor NM5, the drain of the first PMOS transistor PM1, and the gate of the second PMOS transistor PM2 are connected; the source of the seventh NMOS transistor NM7 is connected to the drain of the second PMOS transistor PM2, the gate of the fifth NMOS transistor NM5, and the gate of the ninth NMOS transistor NM9, with the gate connected to power supply VDD and the drain connected to the source of the eighth NMOS transistor NM8 to reduce the drain voltage of the eighth NMOS transistor NM8; the source of the eighth NMOS transistor NM8 is connected to the drain of the seventh NMOS transistor NM7, the gate is connected to the CK signal, and the drain is grounded; the source of the ninth NMOS transistor NM9 is connected to the drain of the first PMOS transistor PM2. The second end of resistor R1 is connected to the first end of the second resistor R2. The gate of the second resistor R1 is connected to the gate of the fifth NMOS transistor NM5, the drain of the second PMOS transistor PM2, and the source of the seventh NMOS transistor NM7. The drain of the second PMOS transistor PM1 is connected to the negative plate of the third capacitor C3, the source of the fourth NMOS transistor NM4, the source of the fifth NMOS transistor NM5, and the source of the sixth NMOS transistor NM6. The source of the first PMOS transistor PM1 is connected to the power supply VDD. The gate of PM1 is input with the CK_NNN signal. The drain of PM1 is connected to the drain of the fifth NMOS transistor NM5, the drain of the sixth NMOS transistor NM6, and the gate of the second PMOS transistor PM2.The source of the second PMOS transistor PM2 is connected to the drain of the third NMOS transistor NM3 and the positive plate of the third capacitor C3. Its gate is connected to the drain of the fifth NMOS transistor NM5 and the drain of the sixth NMOS transistor NM6. Its drain is connected to the source of the seventh NMOS transistor NM7, the gate of the fifth NMOS transistor NM5, and the gate of the ninth NMOS transistor NM9. The positive plate of the third capacitor C3 is connected to the drain of the third NMOS transistor NM3 and the source of the second PMOS transistor PM2. The negative plate of the third capacitor C3 is connected to the source of the fourth NMOS transistor NM4, the drain of the ninth NMOS transistor NM9, the source of the fifth NMOS transistor NM5, and the source of the sixth NMOS transistor NM6. The first terminal of the first resistor R1 is connected to the power supply VDD. The second terminal of the first resistor R1 is connected to the source of the ninth NMOS transistor NM9 and the first terminal of the second resistor R2. The first terminal of the second resistor R2 is connected to the source of the ninth NMOS transistor NM9, and the second terminal of the second resistor R2 is grounded.

[0027] The control voltage generating unit 200 is used to generate a control voltage, corresponding to Figure 3 The sample voltage in the sample changes in real time with the common-mode level VCM, maintaining a fixed level with VCM. Specifically, the control voltage is a preset constant value higher than the common-mode level VCM (reference level). Figure 3 In this context, CK signal is the clock signal, CK_NN signal is the in-phase signal of CK signal after passing through the buffer gate, and CK_NNN signal is the in-phase signal of CK_NN signal.

[0028] exist Figure 3 In the transmission unit 300, there are a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, and a fourth capacitor C4. The source of the tenth NMOS transistor NM10 is connected to the second terminal of the first resistor R1, the first terminal of the second resistor R2, and the source of the eleventh NMOS transistor NM11. The gate receives the control voltage from the control voltage generation unit 200, and the drain is connected to the output N terminal of the reference level generation circuit. The source of the eleventh NMOS transistor NM11 is connected to the second terminal of the first resistor R1, the first terminal of the second resistor R2, and the source of the tenth NMOS transistor NM10. The gate receives the control voltage from the control voltage generation unit 200, and the drain is connected to the positive plate of the fourth capacitor C4 and the output P terminal of the reference level generation circuit. The positive plate of the capacitor C4 is connected to the drain of the eleventh NMOS transistor NM11 and the output P terminal of the reference level generation circuit, and the negative plate is grounded.

[0029] The tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 receive the output voltage V from the control voltage generation unit 200. sample(i.e., the voltage of line SAMPLE) ensures that its internal resistance remains almost constant during the sampling phase. Furthermore, the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are turned off before the sampling switch is turned off, that is, before the positive plate of the digital-to-analog converter capacitor array is connected to GND. Turning off the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 effectively avoids charge injection. The fourth capacitor C4 is charged to VCM during the sampling phase, providing a stable reference voltage for the positive terminal of the subsequent comparator during the conversion phase, and reducing the clock feedthrough effect to a certain extent.

[0030] The present application will now be described in further detail with reference to specific embodiments.

[0031] First of all, Figure 2 In the sampling phase, one end of the digital-to-analog converter sampling array (i.e., capacitor array) is connected to V. IN One end connected to V CM The power consumption of the sampling array is:

[0032] Q = 8C(V) IN -V CM )

[0033] During the conversion phase, capacitor C1 is connected to V. REF Capacitors C2, C3, and C4 are connected to GND. At this time, the charge on the sampling array is...

[0034] Q1 = 4C(V) REF -V N )+4C(V GND -V N )

[0035] Among them, V GND V is the voltage at GND. N Voltage at point N

[0036] If V IN =V REF VCM = V REF / 2, from Q=Q1, we can get,

[0037] V N =0

[0038] V P =VCM=1 / 2V REF >V N Therefore, the comparator outputs 1, and capacitor C1 remains connected to V. REF .

[0039] Then connect capacitors C1 and C2 to VREF, and capacitors C3 and C4 to GND, to obtain

[0040] V N=1 / 4V REF

[0041] V P =VCM=1 / 2V REF >V N Therefore, the comparator outputs 1, and capacitors C1 and C2 remain connected to VREF.

[0042] And so on, until the analog level V is reached. REF Convert to the numeric value 111.

[0043] Next, in Figure 3 In the process, after several cycles, the gate of the third NMOS transistor NM3 is charged to the turn-on voltage. Before sampling, the input CK is pulled low, and CK_NN is also pulled low, fixing the charge of the third capacitor C3. CK_NNN is pulled high, the first PMOS transistor PM1 is turned off, the sixth NMOS transistor NM6 is turned on, and the gate voltage of the second PMOS transistor PM2 is equal to the voltage of the negative plate of C3. The second PMOS transistor PM2 is turned on, making the gate voltage of the ninth NMOS transistor NM9 equal to the voltage of the positive plate of the third capacitor C3. The ninth NMOS transistor NM9 is turned on, and the voltage of the negative plate of the third capacitor C3 is equal to VCM (generated by the voltage division of the first resistor R1 and the second resistor R2). Thus, the ninth NMOS transistor... The difference between the gate voltage and source voltage of MOSFET NM9 is fixed as the voltage difference between the positive and negative plates of the third capacitor C3. The gate voltages of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are equal to the gate voltage of the ninth NMOS transistor NM9, and the source voltages of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are equal to VCM. Thus, the difference between the gate voltage and source voltage of NM10 and NM11 is also fixed as the voltage difference between the positive and negative plates of the third capacitor C3. Finally, the sampling switch is turned on and sampling begins. During the sampling phase, regardless of how VCM changes, the internal resistance of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 remains relatively fixed.

[0044] In existing analog-to-digital converters (ADCs), the N-terminal voltage is constantly changing due to external interference, and the on-resistance of switch S1 also changes continuously during sampling, which affects the linearity of the ADC. According to the solution in this application, the reference level generation circuit provides common-mode levels to the positive and negative terminals of the comparator during the sampling phase and controls whether to provide reference levels to the positive and negative terminals of the comparator. A reference level is provided during sampling, but during comparison, no reference level is provided at the N-terminal; the P-terminal is provided by the fourth capacitor C4. The internal resistances of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are relatively constant, which improves the linearity of the ADC, thereby improving its performance. Furthermore, it also solves the problem of charge injection and reduces clock feedthrough effects.

[0045] exist Figure 2 and Figure 3 Based on the embodiments shown, this application also provides a method for generating a reference level according to a reference level generation circuit. Figure 4 This is a flowchart of a method for generating a reference level according to an embodiment of this application. For example... Figure 4 As shown, the method includes the following steps.

[0046] In step S401, the charge pump provides an activation voltage to the control voltage generation unit.

[0047] like Figure 3 As shown, the charge pump 100 is used to provide a turn-on voltage (the gate voltage of NM3) to the reference level generation unit 200. The turn-on voltage provided to the reference level generation unit 200 must at least reach the level of the NMOS transistor in the control voltage generation unit 200 that receives the turn-on voltage. Figure 3 The source voltage of the third NMOS transistor (NM3) in the control voltage generation unit 200 is the sum of the source voltage and VTH, where VTH is the threshold voltage of the MOS transistor. This is necessary to turn on the third NMOS transistor NM3 of the control voltage generation unit 200.

[0048] In step S402, in response to the turn-on voltage, the control voltage generating unit provides a control voltage to the transmission unit.

[0049] like Figure 3 As shown, the control voltage generating unit 200 is used to generate a control voltage, corresponding to Figure 3 The sample voltage in the sample changes in real time with the common-mode level VCM, and remains at a fixed level with VCM.

[0050] In step S403, in response to the control voltage, the transmission unit provides a reference level for the comparator of the analog-to-digital converter.

[0051] like Figure 3 As shown, the transmission unit 300 is connected to the control voltage generation circuit 200 and is used to provide the common-mode level VCM (i.e., reference voltage) generated by the reference level generation circuit to the positive and negative inputs of the comparator.

[0052] According to the scheme of this application, the reference level generation circuit provides common-mode levels to the positive and negative terminals of the comparator respectively during the sampling stage, and controls whether to provide reference levels to the positive and negative terminals of the comparator. Its internal resistance is relatively constant, which can improve the linearity of the analog-to-digital converter and thus improve the performance of the analog-to-digital converter.

[0053] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this application, and on the specific implementation methods and application scope of this application, are all within the scope of protection of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A reference level generation circuit for an analog-to-digital converter, comprising: The unit comprises a charge pump, a control voltage generation unit, and a transmission unit, wherein: The charge pump is connected to the control voltage generating unit and is used to provide an activation voltage to the control voltage generating unit; The control voltage generating unit is connected to the transmission unit and is used to provide control voltage to the transmission unit; The transmission unit is connected to the comparator of the analog-to-digital converter and is used to provide a reference level for the comparator; In the sampling phase, the reference level generation circuit provides a common-mode level to the positive and negative terminals of the comparator respectively, and controls whether to provide a reference level to the positive and negative terminals of the comparator. A reference level is provided for both terminals during sampling. During the comparison phase, no reference level is provided for the negative terminal, and a reference level is provided for the positive terminal.

2. The reference level generating circuit as described in claim 1, wherein, The charge pump includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first capacitor C1, a second capacitor C2, and an inverter INV1; wherein: The source of the first NMOS transistor NM1 is connected to the power supply VDD, and its gate is connected to the drain of the second NMOS transistor NM2 and the positive plate of the second capacitor C2. The drain is connected to the positive plate of the first capacitor C1, the gate of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3 of the control voltage generation unit. The source of the second NMOS transistor NM2 is connected to the power supply VDD, and its gate is connected to the positive plate of the first capacitor C1, the drain of the first NMOS transistor NM1, and the gate of the third NMOS transistor NM3 of the control voltage generation unit. Its drain is connected to the positive plate of the second capacitor C2 and the gate of the first NMOS transistor NM1. The negative plate of the first capacitor C1 is connected to the CK signal and the input terminal of the inverter INV1; the output terminal of the inverter INV1 is connected to the negative plate of the second capacitor C2.

3. The reference level generation circuit as described in claim 2, wherein, The control voltage generating unit includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a first PMOS transistor PM1, a second PMOS transistor PM2, a third capacitor C3, a first resistor R1, and a second resistor R2, wherein: The source of the third NMOS transistor NM3 is connected to the power supply VDD, the gate is connected to the drain of the first NMOS transistor NM1 of the charge pump and the positive plate of the third capacitor C3, and the drain is connected to the source of the second PMOS transistor PM2. The source of the fourth NMOS transistor NM4 is connected to the negative plate of the third capacitor C3, the drain of the ninth NMOS transistor NM9, the source of the fifth NMOS transistor NM5, and the source of the sixth NMOS transistor NM6. The gate is input with the CK_NN signal, and the drain is grounded. The source of the fifth NMOS transistor NM5 is connected to the negative plate of the third capacitor C3, the source of the fourth NMOS transistor NM4, the source of the sixth NMOS transistor NM6, and the drain of the ninth NMOS transistor NM9. The gate of the NMOS transistor NM5 is connected to the drain of the second PMOS transistor PM2, the source of the seventh NMOS transistor NM7, and the gate of the ninth NMOS transistor NM9. The drain of the NMOS transistor NM5 is connected to the drain of the sixth NMOS transistor NM6, the drain of the first PMOS transistor PM1, and the gate of the second PMOS transistor PM2. The source of the sixth NMOS transistor NM6 is connected to the negative plate of the third capacitor C3, the source of the fourth NMOS transistor NM4, the source of the fifth NMOS transistor NM5, and the drain of the ninth NMOS transistor NM9. The gate is input with the CK_NNN signal, and the drain is connected to the drain of the fifth NMOS transistor NM5, the drain of the first PMOS transistor PM1, and the gate of the second PMOS transistor PM2. The source of the seventh NMOS transistor NM7 is connected to the drain of the second PMOS transistor PM2, the gate of the fifth NMOS transistor NM5, and the gate of the ninth NMOS transistor NM9. The gate is connected to the power supply VDD, and the drain is connected to the source of the eighth NMOS transistor NM8. The source of the eighth NMOS transistor NM8 is connected to the drain of the seventh NMOS transistor NM7, the gate is connected to the CK signal, and the drain is grounded. The source of the ninth NMOS transistor NM9 is connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2. The gate is connected to the gate of the fifth NMOS transistor NM5, the drain of the second PMOS transistor PM2, and the source of the seventh NMOS transistor NM7. The drain is connected to the negative plate of the third capacitor C3, the source of the fourth NMOS transistor NM4, the source of the fifth NMOS transistor NM5, and the source of the sixth NMOS transistor NM6. The source of the first PMOS transistor PM1 is connected to the power supply VDD, the gate is input with the CK_NNN signal, and the drain is connected to the drain of the fifth NMOS transistor NM5, the drain of the sixth NMOS transistor NM6, and the gate of the second PMOS transistor PM2. The source of the second PMOS transistor PM2 is connected to the drain of the third NMOS transistor NM3 and the positive plate of the third capacitor C3, and the gate is connected to the drain of the fifth NMOS transistor NM5 and the drain of the sixth NMOS transistor NM6. The drain is connected to the source of the seventh NMOS transistor NM7, the gate of the fifth NMOS transistor NM5 and the gate of the ninth NMOS transistor NM9. The positive plate of the third capacitor C3 is connected to the drain of the third NMOS transistor NM3 and the source of the second PMOS transistor PM2, and the negative plate of the third capacitor C3 is connected to the source of the fourth NMOS transistor NM4, the drain of the ninth NMOS transistor NM9, the source of the fifth NMOS transistor NM5 and the source of the sixth NMOS transistor NM6. The first end of the first resistor R1 is connected to the power supply VDD, and the second end is connected to the source of the ninth NMOS transistor NM9 and the first end of the second resistor R2. The first end of the second resistor R2 is connected to the source of the ninth NMOS transistor NM9, and the second end is grounded.

4. The reference level generating circuit as described in claim 1 or 2, wherein, The transmission unit includes a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, and a fourth capacitor C4, wherein: The source of the tenth NMOS transistor NM10 is connected to the second terminal of the first resistor R1, the first terminal of the second resistor R2, and the source of the eleventh NMOS transistor NM11. The gate receives the control voltage from the control voltage generation unit, and the drain is connected to the output N terminal of the reference level generation circuit. The source of the eleventh NMOS transistor NM11 is connected to the second terminal of the first resistor R1, the first terminal of the second resistor R2, and the source of the tenth NMOS transistor NM10. The gate receives the control voltage from the control voltage generation unit, and the drain is connected to the positive plate of the fourth capacitor C4 and the output P terminal of the reference level generation circuit. The positive plate of capacitor C4 is connected to the drain of the eleventh NMOS transistor NM11 and the output P terminal of the reference level generation circuit, while the negative plate is grounded.

5. The reference level generating circuit as described in claim 1 or 2, wherein, The turn-on voltage must be at least the sum of the source voltage of the NMOS transistor receiving the turn-on voltage in the control voltage generation unit and VTH, where VTH is the threshold voltage of the MOS transistor.

6. The reference level generating circuit as described in claim 1 or 2, wherein, The control voltage is higher than the reference level by a preset constant value.

7. The reference level generating circuit as described in claim 3, wherein, The CK signal is a clock signal, the CK_NN signal is the in-phase signal of the CK signal after passing through a buffer gate, and the CK_NNN signal is the in-phase signal of the CK_NN signal.

8. A method for generating a reference level using a reference level generation circuit according to any one of claims 1 to 7, comprising: The charge pump provides an activation voltage to the control voltage generating unit; In response to the turn-on voltage, the control voltage generating unit provides a control voltage to the transmission unit; In response to the control voltage, the transmission unit provides a reference level for the comparator of the analog-to-digital converter.

9. The method of claim 8, wherein, The turn-on voltage must be at least the sum of the source voltage of the NMOS transistor receiving the turn-on voltage in the control voltage generation unit and VTH, where VTH is the threshold voltage of the MOS transistor.

10. The method of claim 8, wherein, The control voltage is higher than the reference level by a preset constant value.

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