A multi-bit quantization hardware multiplexed extended counting analog-to-digital converter

Abstract

This invention provides a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter (ADC) comprising: a sampling module, a control module, an arithmetic module, a chopper operational amplifier, a multi-bit quantizer, a counter and digital logic processing unit, and a DAC module. The sampling module, control module, and arithmetic module are time-division multiplexed under the control of multiple clock signals, allowing the multi-bit quantization hardware multiplexing extended counting ADC to alternately operate in Sigma-Delta ADC mode and cyclic ADC mode. This invention combines the high precision of Sigma-Delta ADC with the relatively high speed of Nyquist-Rate ADC, and improves upon Extended Counting ADC by introducing multi-bit quantization technology, dual sampling technology, and chopper technology, thereby significantly reducing the overall power consumption of the ADC while maintaining high precision and a certain speed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter. Background Technology

[0002] With the advancement of modern CMOS integrated circuit technology and the rapid development of communication technology, microelectronics has become the foundation of modern information society. Many traditional analog signal processing circuits are gradually being replaced by digital circuits. In integrated circuit systems, analog-to-digital converters (ADCs) serve as the interface between analog signals and digital systems, and improvements in their performance will have a significant impact on the development of electronic systems.

[0003] Analog-to-digital converters (ADCs) are currently widely used in automotive electronics and are the core components in battery pack detectors for multi-cell batteries. Current ADCs achieve battery distribution in automobiles by cyclically detecting battery voltage. Existing ADCs used in battery pack detectors typically employ the traditional Sigma-Delta structure, which requires at least a third-order structure to function properly. This method usually requires multi-stage amplifiers and multi-stage capacitor arrays, resulting in problems such as large chip area, high power consumption, long conversion time, and environmental and process interference affecting conversion accuracy. Furthermore, with the development of automotive electronics, to ensure the safety and stability of battery packs, there will be higher requirements for the accuracy and speed of ADCs, causing the power consumption and area of ​​traditional Sigma-Delta ADCs to increase exponentially. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a multi-bit quantization hardware multiplexing extended counter analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter, comprising: a sampling module, a control module, an arithmetic module, a chopper operational amplifier, a multi-bit quantizer, a counter and digital logic processing, and a DAC module;

[0006] The outputs of the sampling module and the control module are both connected to the input of the chopper operational amplifier. The output of the chopper operational amplifier is connected to the input of the multi-bit quantizer. The output of the multi-bit quantizer is connected to the input of the counter, digital logic processing, and DAC module. The output of the DAC module is fed back to the sampling module, the control module, and the arithmetic module. The sampling module, the control module, and the arithmetic module are controlled by multiple clock signals and are time-division multiplexed, so that the multi-bit quantization hardware multiplexed extended counting analog-to-digital converter alternately operates in Sigma-Delta ADC mode and cyclic ADC mode.

[0007] 1. This invention enables a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter to alternately operate in Sigma-Delta ADC mode and cyclic ADC mode through hardware time-division multiplexing. The cyclic ADC mode retains the advantage of the simple structure of a first-order incremental ADC, and the structure is simplified by multiplexing some modules of the Sigma-Delta ADC mode. Furthermore, the time-division multiplexing is controlled by a clock, thus greatly reducing the area.

[0008] 2. The Sigma-Delta ADC operating mode of this invention adds a reset control terminal compared to the traditional Sigma-Delta ADC. After each data conversion, the integrator and digital filter can be cleared using the reset function. This makes it more adaptable to sensor applications.

[0009] 3. The n1 most significant bits of this invention are obtained through the Sigma-Delta ADC operating mode, and the accuracy does not depend on the component matching degree; the conversion accuracy of the cyclic ADC operating mode is determined by the component matching accuracy, but the impact of the error caused by component mismatch on the overall conversion is reduced by 2. n1 .

[0010] 4. When the required conversion accuracy is n = n1 + n2 bits, the extended incremental ADC requires 2 n1 +n² cycles. Compared to existing dual-slope ADCs or basic first-order incremental ADCs that require 2... n The present invention requires fewer clock cycles for the conversion process, thereby alleviating the bandwidth requirements of analog circuits and reducing power consumption.

[0011] 5. This invention employs a dual-sampling integrator, which effectively reduces the power consumption of the operational amplifier and better solves the capacitor mismatch problem. Furthermore, by using a 2.5-bit quantizer, the conversion cycle is shortened while providing the same accuracy in Sigma-Delta ADC mode; in cyclic ADC mode, the 2.5-bit quantizer provides a higher number of effective bits per conversion compared to 1-bit quantization, significantly reducing the conversion cycle.

[0012] 6. This invention employs redundant digital outputs, which reduces the circuit's requirements for comparator accuracy and offset. This reduced requirement for accuracy and offset voltage means that low-power dynamic latch comparators can be used in the design, significantly reducing power consumption. Simultaneously, the use of chopping technology effectively reduces low-frequency flicker noise, thereby significantly improving the overall circuit accuracy and reliability.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a first-order incremental Sigma-Delta ADC provided in an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the extended counting analog-to-digital converter provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the structure of the cyclic ADC provided in the embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of the overall structure of a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter provided in an embodiment of the present invention;

[0018] Figure 5 Provided by the embodiments of the present invention Figure 4 The timing diagram of the extended counting analog-to-digital converter circuit shown;

[0019] Figure 6 The circuit structure of the Sigma-Delta ADC in operating mode provided in the embodiments of the present invention;

[0020] Figure 7 The circuit structure of the cyclic ADC operating mode provided in the embodiment of the present invention;

[0021] Figure 8 The conversion relationship diagram of the 2.5-bit quantizer provided in the embodiment of the present invention;

[0022] Figure 9 This is a diagram of the chopper circuit structure provided in an embodiment of the present invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0024] Combination Figures 1 to 6 The present invention provides a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter including: a sampling module, a control module, an arithmetic module, a chopper operational amplifier, a multi-bit quantizer, a counter and digital logic processing, and a DAC module;

[0025] The outputs of the sampling module and the control module are both connected to the input of the chopper operational amplifier. The output of the chopper operational amplifier is connected to the input of the multi-bit quantizer. The output of the multi-bit quantizer is connected to the input of the counter, digital logic processing, and DAC module. The output of the DAC module is fed back to the sampling module, the control module, and the arithmetic module. The sampling module, the control module, and the arithmetic module are controlled by multiple clock signals and are time-division multiplexed, so that the multi-bit quantization hardware multiplexed extended counting analog-to-digital converter alternately operates in Sigma-Delta ADC mode and cyclic ADC mode.

[0026] This invention utilizes hardware time-division multiplexing to enable a multi-bit quantization hardware multiplexed extended counting analog-to-digital converter to alternately operate in Sigma-Delta ADC mode and cyclic ADC mode. The cyclic ADC mode retains the advantage of a simple first-order incremental ADC structure, and by multiplexing some modules of the Sigma-Delta ADC mode, the structure remains simple. Furthermore, time-division multiplexing, controlled by a clock, can significantly reduce the area.

[0027] Combination Figure 1 and Figure 2 As shown, the Extended Counting ADC is an improvement on the first-order incremental Sigma-Delta ADC. Figure 1 It is a first-order incremental Sigma-Delta ADC structure. Figure 2 To extend the structure of the counting analog-to-digital converter, the integrator and counter are reset before conversion at each sampling point. Assuming the input signal is a DC signal Vin, then:

[0028] V[i]=V[i-1]+Vin-d[i-1]×Vref (1);

[0029] Where V[i] represents the output voltage of the chopper operational amplifier in the i-th operation of the Sigma-Delta ADC, V[i-1] represents the output voltage of the chopper operational amplifier in the (i-1)-th operation of the Sigma-Delta ADC, d[i-1] represents the output of the 2.5-bit quantizer in the (i-1)-th operation of the Sigma-Delta ADC, and Vref represents the reference voltage.

[0030] After N1 cycles, we have:

[0031]

[0032] Where V[N1] represents the output voltage of the chopper operational amplifier in the N1th operation of the Sigma-Delta ADC operating mode, and d[i] represents the output of the 2.5-bit quantizer in the i-th operation of the Sigma-Delta ADC operating mode;

[0033] therefore,

[0034]

[0035] For a first-order modulator, the following equation always holds:

[0036] -Vref <V[N1]<Vref (4);

[0037] As can be seen from the above two equations, the digital output of Vin can be obtained by accumulating d[i] using a counter. And note that the integrator's output V[N1] is a varying residual. The precision of the conversion is determined by the number of accumulation cycles N1. To obtain n1 bits of precision, 2^(N1-N) cycles are required. n1 .

[0038] These n1 bits are the most significant bits, as mentioned earlier, V[N1] is the residual. The signal is already a large signal at N1 times its original value, so it does not need to be amplified further. The output of the integrator, V[N1]-d[N1]×Vref, is then transformed to obtain the output of the least significant bit. The most significant bit and the least significant bit are then combined to form the Extended Counting ADC.

[0039] The n1 most significant bits of this invention are obtained through the Sigma-Delta ADC operating mode, and the accuracy is independent of the component matching degree; the conversion accuracy of the cyclic ADC operating mode is determined by the component matching accuracy, but the impact of the error caused by component mismatch on the overall conversion is reduced by 2. n1 When the required conversion accuracy is n = n1 + n2 bits, the extended incremental ADC requires 2 n1 +n² cycles. Compared to existing dual-slope ADCs or basic first-order incremental ADCs that require 2... n The present invention requires fewer clock cycles for the conversion process, thereby alleviating the bandwidth requirements of analog circuits and reducing power consumption.

[0040] refer to Figure 3 , Figure 3To implement the cyclic ADC working mode, the analog input to be converted is first compared with the reference level, and the comparison result is used as the first output. Depending on the comparison result, the level is multiplied by 2 and then added or subtracted from Vref to obtain a new level to be compared. The new level to be compared is then compared with the reference level to obtain the next output. The above process is then repeated continuously to obtain the output results of each least significant bit.

[0041] From the above description and Figure 3 It can be seen that the following formula is true:

[0042] Vres[i]=2×Vres[i-1]-Dout[i-1]×Vref (5);

[0043] Where Vres[i] represents the output voltage of the subtractor in the i-th operation of the cyclic ADC, Vres[i-1] represents the output voltage of the subtractor in the (i-1)-th operation of the cyclic ADC, and Dout[i-1] represents the output of the 2.5-bit quantizer in the (i-1)-th operation of the cyclic ADC.

[0044] From equation (5), we can obtain the following after N2 clock cycles:

[0045]

[0046] Where Vres[N2] represents the output voltage of the subtractor in the N2th operation under cyclic ADC operating mode.

[0047] It can be seen that the residual Vs generated after the counting process was quantized after N2 cycles, and the quantization error was...

[0048] Cyclic ADCs and first-order Sigma-Delta ADCs can use the same circuit structure, including sampling circuits, chopper operational amplifiers, and quantizers.

[0049] Extended Counting ADCs combine a first-order incremental Sigma-Delta ADC with a traditional Nyquist-Rate ADC, integrating the high accuracy of Sigma-Delta ADCs with the relatively high speed of Nyquist-Rate ADCs. The identical structure in both types of ADCs simplifies the overall design, making it ideal for sensor applications. This invention improves upon the Extended Counting ADC by introducing multi-bit quantization, dual sampling, and chopping techniques, significantly reducing overall power consumption while maintaining high accuracy and a certain speed.

[0050] The Sigma-Delta ADC operating mode of this invention adds a reset control terminal compared to the traditional Sigma-Delta ADC. After each data conversion, the integrator and digital filter can be cleared using the reset function. This makes it more adaptable to sensor applications.

[0051] like Figure 4 As shown, Figure 4 This is a schematic diagram of the overall structure of a multi-bit quantization hardware multiplexing extended counting analog-to-digital converter provided by the present invention. Figure 4 The sampling module in this invention includes capacitors CS11 and CS11, and switches S11, S12, S21, S22, S101, S102, S131, S132, S111, S112, S31, S32, S41, and S42.

[0052] Specifically, the first terminal of switch S11 is connected to the first terminal of switch S22 and serves as the negative input terminal VIN-; the second terminal of switch S11 is connected to the first terminals of switch S21, switch S101, switch S131, and capacitor CS11; the second terminal of switch S101 is connected to the negative feedback signal VB-; the second terminal of switch S131 is connected to the negative output signal Vout-; the second terminal of switch S21 is connected to the first terminal of switch S12 and serves as the positive input terminal VIN+; the second terminal of switch S22 is connected to the second terminal of switch S21, the first terminal of switch S102, switch S132, and capacitor CS12; the second terminal of switch S102 is connected to... Connect the positive feedback signal VB+; connect the second terminal of switch S132 to the positive output signal Vout+; connect the second terminal of capacitor CS11 to the first terminal of switch S31, the first terminal of switch S111, and the first terminal of switch S41; connect the second terminal of switch S31 to the second terminal of switch S42, and connect the output to the first input terminal of the chopper operational amplifier; connect the second terminal of capacitor CS12 to the second terminal of switch S112, the first terminal of switch S42, and the first terminal of switch S32; connect the second terminal of switch S32 to the second terminal of switch S41, and connect the output to the second input terminal of the chopper operational amplifier; connect the second terminal of switch S111 to the first terminal of switch S112, and connect the common-mode signal VCM.

[0053] The control module includes: capacitors CS21 and CS21, and switches S51, S52, S61, S62, S121, S122, S141, S142, S123, S124, S71, S72, S81, and S82.

[0054] Specifically, the first terminal of switch S51 is connected to the first terminal of switch S62 and is connected to the positive feedback output signal VB+; the second terminal of switch S51 is connected to the first terminals of switch S61, switch S121, switch S141, and capacitor CS21; the second terminal of switch S141 is connected to the positive output signal; the second terminal of switch S61 is connected to the first terminal of switch S52 and is connected to the negative feedback signal VB-; the second terminal of switch S62 is connected to the second terminal of switch S52, the first terminal of switch S122, switch S142, and capacitor CS22; the second terminal of switch S142 is connected to the negative output signal Vout-; and the second terminal of switch S132 is connected to the positive output signal Vout-. The second terminal of capacitor CS21 is connected to the first terminal of switch S71, the first terminal of switch S123, and the first terminal of switch S81. The second terminals of switch S71 and S82 are connected to the first input terminal of the chopper operational amplifier. The second terminal of capacitor CS22 is connected to the second terminal of switch S124, the first terminal of switch S72, and the first terminal of switch S82. The second terminal of switch S72 is connected to the second terminal of switch S81, and its output is connected to the second input terminal of the chopper operational amplifier. The second terminal of switch S121 is connected to the first terminal of switch S122, and is connected to the common-mode signal VCM. The second terminal of switch S123 is connected to the first terminal of switch S124, and is connected to the common-mode signal VCM.

[0055] The operation module includes a symmetrical upper sub-module and a lower sub-module. The upper sub-module includes switches SF11, SF21, SF31, SF41, SF61, S91, S133, and S103; and capacitors CF11 and CF21.

[0056] Specifically, the first terminals of switches SF11, SF31, and S91 are all connected to the first input terminal of the chopper operational amplifier; the second terminal of switch SF11 is connected to the first terminal of capacitor CF11; the second terminal of capacitor CF11 is connected to the first terminals of switches SF61 and SF21; the second terminal of switch SF61 is connected to the common-mode signal VCM; the second terminal of switch SF31 is connected to the first terminal of switch S103 and capacitor CF21; the second terminal of switch S103 is connected to the common-mode signal VCM; the second terminal of switch CF21 is connected to the first terminals of switches S133 and SF41; the second terminal of switch S133 is connected to the positive feedback signal VB+; the second terminals of switches SF21, SF41, and S91 are all used as output terminals and connected to the positive input terminal of the multi-bit quantizer.

[0057] The sub-modules include switches SF12, SF22, SF32, SF42, SF62, S92, S134, and S104; and capacitors CF12 and CF22.

[0058] Specifically, the first terminals of switches SF12, SF32, and S92 are all connected to the second input terminal of the chopper operational amplifier; the second terminal of switch SF12 is connected to the first terminal of capacitor CF12; the second terminal of capacitor CF12 is connected to the first terminals of switches SF22 and SF62; the second terminal of switch SF62 is connected to the common-mode signal VCM; the second terminal of switch SF32 is connected to the first terminal of switch S104 and capacitor CF22, and the second terminal of switch S104 is connected to the common-mode signal VCM; the second terminal of switch CF22 is connected to the first terminals of switches S134 and SF42; the second terminal of switch S134 is connected to the negative feedback signal VB-; the second terminals of switches SF22, SF42, and S92 are all used as output terminals and connected to the negative input terminal of the multi-bit quantizer.

[0059] The chopper operational amplifier includes: one operational amplifier and two chopper switches;

[0060] In this configuration, the first input terminal of the first chopper switch serves as the first input terminal of the chopper operational amplifier, and the second input terminal of the first chopper switch serves as the second input terminal of the chopper operational amplifier. The first output terminal of the first chopper switch is connected to the first input terminal of the operational amplifier, and the second output terminal of the first chopper switch is connected to the second input terminal of the operational amplifier. The first output terminal of the operational amplifier is connected to the first input terminal of the second chopper switch, and the second output terminal of the operational amplifier is connected to the second input terminal of the second chopper switch. The first output terminal of the second chopper switch serves as the first output terminal of the chopper operational amplifier and is connected to the positive input terminal of the multi-bit quantizer. The second output terminal of the second chopper switch serves as the second output terminal of the chopper operational amplifier and is connected to the negative input terminal of the multi-bit quantizer.

[0061] The multi-bit quantizer is a 2.5-bit quantizer, which includes multiple dynamic latch comparators and flip-flops. The first input of each dynamic latch is connected to the first output of the chopper operational amplifier, and the second input of each dynamic latch is connected to the second output of the chopper operational amplifier. The output of each dynamic latch is connected to the input of a corresponding flip-flop. The output of each flip-flop is connected to the input of a counter and digital logic processing unit.

[0062] refer to Figures 5-6 As shown, when the multi-bit quantization hardware multiplexing extended counting analog-to-digital converter is in Sigma-Delta ADC operating mode,

[0063] The sampling module is used to sample the input signal and feed the sampling results back to the chopper operational amplifier and the arithmetic module;

[0064] The chopper operational amplifier is used to amplify the sampling result based on the feedback result and feed the amplified result back to the arithmetic module;

[0065] The arithmetic module is used to integrate the sampling result based on the amplification result and output the integration result to the multi-bit quantizer;

[0066] In Sigma-Delta ADC operating mode, a dual-sampling integration method is used. That is, integration is completed once between the two phases within one clock cycle. Both the input and output signals are fully differential signals, and the common-mode level of the signals is 0. Assuming that... Figure 6 In the sampling module, the average value of sampling capacitors CS11 and CS12 is C1, and the difference is ΔC. The switch switches once in each phase of one clock cycle, allowing the integrator to complete one integration. It can be seen that this structure achieves double sampling, and the sampling frequency will be doubled. The charge transferred to the upper and lower integrating capacitors during switch switching is given by formulas (7) and (8), respectively.

[0067] The upper integrating capacitors are CF11 and CF21. The total charge transferred to capacitors CF11 and CF21 is:

[0068]

[0069] The lower half of the integrating capacitors are CF12 and CF22. The total charge transferred to capacitors CF12 and CF22 is expressed as:

[0070]

[0071] The differential charge is:

[0072]

[0073] The common-mode charge is:

[0074]

[0075] Its z-domain expression is:

[0076]

[0077] When the fully floating integrator is working, the input of the operational amplifier is always a floating node. It has an incremental Sigma-Delta structure. The integrator is reset after each sampling point is transformed. Therefore, the input of the operational amplifier can be connected to a suitable common-mode level during this reset phase.

[0078] A multi-bit quantizer is used to quantize the integration result and output the quantized result to a counter and digital logic processing.

[0079] The counter and digital logic processing are used to count and process the quantization results, and output the processing results to the DAC module as the output result.

[0080] The DAC module is used to convert the processing results into digital-to-analog conversion to obtain feedback results, and then feed the feedback results back to the control module;

[0081] The control module is used to feed the feedback results back to the chopper operational amplifier.

[0082] Combination Figure 5 and Figure 6 , Figure 5 CLKM and CLK in the table refer to the system clock. Figure 5 The remaining clocks are generated by CLKM and CLK.

[0083] Among them, capacitors Cs11 and Cs12 have the same capacitance value, which is Cs1; capacitors Cs21 and Cs22 have the same capacitance value, which is Cs2; and capacitors CF11, CF12, CF21, and CF22 have the same capacitance value, which is Cf.

[0084] The first clock phase is the reset phase, at which point the integrator is cleared to zero, and the op-amp inputs receive a defined common-mode level. Additionally, Vin is sampled onto Cs11 and Cs12. The charges on Cs21 and Cs22 are cleared. The first accumulation after reset only accumulates Vin, not the feedback signal, therefore...

[0085]

[0086] Next, based on the quantizer's judgment result, the feedback signal D[1]×Vref is determined. In the second accumulation phase, we have:

[0087]

[0088] Following this pattern, we have the following recursive formula:

[0089]

[0090] After N1 accumulations, we have:

[0091]

[0092] In the N1+1th accumulation, Vin is no longer added; only (D[N1-1]+D[N1])×Vref is accumulated. Therefore, we have:

[0093]

[0094] The N1+2th accumulation also does not accumulate Vin, but only (D[N1]+D[N1+1])×Vref, thus we have:

[0095]

[0096] From the above formula, we get:

[0097]

[0098] The numerator of the second term in the above equation does not contain If the factor is directly extended and transformed on V[N+2], nonlinearity will occur due to the matching error between Cs2 and Cf. Therefore, before the extended transformation, the positions of Cf and Cs2 are swapped and a product operation is performed. To ensure that the result does not exceed the transformation range of the cyclic ADC, D[N1+2]×Vref is also subtracted, resulting in:

[0099]

[0100] Vcount is the initial value of the extended transformation. From the above equation, we can obtain:

[0101]

[0102]

[0103] In the formula, and It is obtained from the subsequent quantizer and digital logic processor. Vcount is the input value of the cyclic ADC.

[0104] Combination Figure 5 and Figure 7 As shown, when the multi-bit quantization hardware multiplexing extended counting analog-to-digital converter is in cyclic ADC operating mode,

[0105] The sampling module and the arithmetic module are used to alternately sample the output of the chopper operational amplifier in the current pulse and input it to the chopper operational amplifier, or to subtract the sampling result of the previous pulse from the feedback result of the DAC module in the previous pulse.

[0106] The sampling module uses different pulses for subtraction or sampling compared to the arithmetic module.

[0107] The chopper operational amplifier is used to receive the subtraction result, amplify the subtraction result, and output the amplified result to the sampling module or the arithmetic module;

[0108] A multi-bit quantizer is used to quantize the amplified result and output the quantized result to a counter and digital logic processing.

[0109] The counter and digital logic processing are used to count and process the quantization results, and output the processing results to the DAC module as the output result.

[0110] The DAC module is used to convert the processing results into digital-to-analog conversion to obtain feedback results, and then feed the feedback results back to the sampling module or the arithmetic module.

[0111] The cyclic ADC operating mode can be divided into two phases. In the odd-numbered phase, the original voltage across CF21 and CF22 is V[i-1]. In this phase, the right plates of CF21 and CF22 are connected to the negative input terminal of the op-amp, and the left plates are connected to d[i-1]×Vref. The original voltage across CS21 and CS22 is also V[i-1]. Therefore, after this phase ends, there is...

[0112]

[0113] Where CS1 = Cf = CS2, then:

[0114] V[i]=2×V[i-1]-d[i-1]×Vref(23);

[0115] This achieves the operation of multiplying by 2 and subtracting from the reference voltage. At the same time, the voltages on CS11 and CS12 also change to V[i], and the reference voltage is d[i-1]×Vref.

[0116] In the next phase (even-numbered phase), the actions of CS11 and CS12 are interchanged with those of CF21 and CF22, and similarly, the following is obtained:

[0117]

[0118] Right now:

[0119] V[i+1]=2×V[i]-d[i]×Vref(25);

[0120] This process of repeating is how the cyclic ADC algorithm is implemented.

[0121] refer to Figure 8 Whether in Sigma-Delta ADC operating mode or cyclic ADC operating mode, the quantizer uses a 2.5-bit quantizer circuit. For example... Figure 8 As shown, a redundant signed digit (RSD) output is used, employing six comparators with different thresholds to obtain a three-digit output: 000, 001, 010, 011, 100, 101, and 110. The figure illustrates the correspondence between V[i] and V[i+1] before and after one cyclic transformation.

[0122] This invention employs a dual-sampling integrator, which effectively reduces the power consumption of the operational amplifier and better solves the capacitor mismatch problem. Furthermore, by using a 2.5-bit quantizer, the conversion cycle is shortened while providing the same accuracy in Sigma-Delta ADC mode; in cyclic ADC mode, the 2.5-bit quantizer provides a higher number of effective bits per conversion compared to 1-bit quantization, significantly reducing the conversion cycle.

[0123] The chopper operational amplifier uses, for example Figure 9 The chopper circuit shown modulates flicker noise from within the signal bandwidth to a higher frequency outside the signal band. The first chopper switch, Chop1, modulates the input signal to a high frequency, and then the high-frequency input signal and the low-frequency noise signal are simultaneously amplified by the amplifier. Finally, the second chopper switch, Chop2, restores the high-frequency input signal back to a low frequency, while the low-frequency noise signal is then modulated to a higher frequency band by Chop2.

[0124] This invention employs redundant digital outputs, which reduces the circuit's requirements for comparator accuracy and offset. This reduced requirement for accuracy and offset voltage means that low-power dynamic latch comparators can be used in the design, significantly reducing power consumption. Simultaneously, the use of chopping technology effectively reduces low-frequency flicker noise, thereby significantly improving the overall circuit accuracy and reliability.

[0125] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0126] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0127] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A multi-bit quantization hardware multiplexing extended counting analog-to-digital converter, characterized in that, include: Sampling module, control module, arithmetic module, chopper operational amplifier, multi-bit quantizer, counter and digital logic processing, DAC module; The outputs of the sampling module and the control module are both connected to the input of the chopper operational amplifier. The output of the chopper operational amplifier is connected to the input of the multi-bit quantizer. The output of the multi-bit quantizer is connected to the input of the counter and digital logic processing module and the DAC module. The output of the DAC module is fed back to the sampling module, the control module, and the arithmetic module. The sampling module, the control module, and the arithmetic module are controlled by multiple clock signals and are time-division multiplexed, so that the multi-bit quantization hardware multiplexed extended counting analog-to-digital converter alternately operates in Sigma-Delta ADC mode and cyclic ADC mode.

2. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, When the multi-bit quantization hardware multiplexing extended counting analog-to-digital converter is in Sigma-Delta ADC operating mode, The sampling module is used to sample the input signal and feed the sampling result back to the chopper operational amplifier and the operational module; The chopper operational amplifier is used to amplify the sampling result based on the feedback result and feed the amplified result back to the computing module; The arithmetic module is used to integrate the sampling result based on the amplification result and output the integration result to the multi-bit quantizer. The multi-bit quantizer is used to quantize the integration result and output the quantization result to the counter and digital logic processing. The counter and digital logic processing are used to count and process the quantization result, and output the processing result to the DAC module as the output result. The DAC module is used to perform digital-to-analog conversion on the processing result to obtain a feedback result, and then feed the feedback result back to the control module; The control module is used to feed the feedback result back to the chopper operational amplifier.

3. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, When the multi-bit quantization hardware multiplexing extended counting analog-to-digital converter is in cyclic ADC operating mode The sampling module and the arithmetic module are used to alternately sample the output result of the chopper operational amplifier in the current pulse and input it to the chopper operational amplifier, or to subtract the sampling result of the previous pulse from the feedback result of the DAC module in the previous pulse. The sampling module uses a different pulse for subtraction or sampling than the arithmetic module. The chopper operational amplifier is used to receive the subtraction result, amplify the subtraction result, and output the amplified result to the sampling module or the operation module; The multi-bit quantizer is used to quantize the amplification result and output the quantization result to the counter and digital logic processing. The counter and digital logic processing are used to count and process the quantization result, and output the processing result to the DAC module as the output result. The DAC module is used to perform digital-to-analog conversion on the processing result to obtain a feedback result, and then feed the feedback result back to the sampling module or the computing module.

4. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, The sampling module includes capacitors CS11 and CS11, and switches S11, S12, S21, S22, S101, S102, S131, S132, S111, S112, S31, S32, S41, and S42. Specifically, the first terminal of switch S11 is connected to the first terminal of switch S22 and serves as the negative input terminal (VIN-); the second terminal of switch S11 is connected to the first terminals of switch S21, S101, S131, and capacitor CS11; the second terminal of switch S101 is connected to the negative feedback signal (VB-); the second terminal of switch S131 is connected to the negative output signal (Vout-); the second terminal of switch S21 is connected to the first terminal of switch S12 and serves as the positive input terminal (VIN+); the second terminal of switch S22 is connected to the second terminal of switch S21, the first terminal of switch S102, the first terminal of switch S132, and capacitor CS12; the second terminal of switch S102 is connected to... Positive feedback signal (VB+); the second terminal of switch S132 is connected to the positive output signal (Vout+); the second terminal of capacitor CS11 is connected to the first terminal of switch S31, the first terminal of switch S111, and the first terminal of switch S41; the second terminal of switch S31 is connected to the second terminal of switch S42, and its output is connected to the first input terminal of the chopper operational amplifier; the second terminal of capacitor CS12 is connected to the second terminal of switch S112, the first terminal of switch S42, and the first terminal of switch S32; the second terminal of switch S32 is connected to the second terminal of switch S41, and its output is connected to the second input terminal of the chopper operational amplifier; the second terminal of switch S111 is connected to the first terminal of switch S112, and is connected to the common-mode signal (VCM).

5. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, The control module includes: capacitors CS21 and CS21, and switches S51, S52, S61, S62, S121, S122, S141, S142, S123, S124, S71, S72, S81, and S82. Specifically, the first terminal of switch S51 is connected to the first terminal of switch S62 and is connected to the positive feedback output signal (VB+); the second terminal of switch S51 is connected to the first terminals of switch S61, switch S121, switch S141, and capacitor CS21; the second terminal of switch S141 is connected to the positive output signal; the second terminal of switch S61 is connected to the first terminal of switch S52 and is connected to the negative feedback signal (VB-); the second terminal of switch S62 is connected to the second terminal of switch S52, the first terminal of switch S122, the first terminal of switch S142, and capacitor CS22; the second terminal of switch S142 is connected to the negative output signal (Vout-); the second terminal of switch S132 is connected to the positive output signal (VB-). Vout+); The second terminal of capacitor CS21 is connected to the first terminal of switch S71, the first terminal of switch S123, and the first terminal of switch S81; The second terminal of switch S71 and the second terminal of switch S82 are connected to the first input terminal of the chopper operational amplifier; The second terminal of capacitor CS22 is connected to the second terminal of switch S124, the first terminal of switch S72, and the first terminal of switch S82; The second terminal of switch S72 is connected to the second terminal of switch S81, and its output is connected to the second input terminal of the chopper operational amplifier; The second terminal of switch S121 is connected to the first terminal of switch S122, and is connected to the common-mode signal (VCM); The second terminal of switch S123 is connected to the first terminal of switch S124, and is connected to the common-mode signal (VCM).

6. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, The operation module includes a symmetrical upper sub-module and a lower sub-module. The upper sub-module includes switches SF11, SF21, SF31, SF41, SF61, S91, S133, and S103; and capacitors CF11 and CF21. Specifically, the first terminals of switches SF11, SF31, and S91 are all connected to the first input terminal of the chopper operational amplifier; the second terminal of switch SF11 is connected to the first terminal of capacitor CF11; the second terminal of capacitor CF11 is connected to the first terminals of switches SF61 and SF21; the second terminal of switch SF61 is connected to a common-mode signal (VCM); the second terminal of switch SF31 is connected to the first terminal of switch S103 and capacitor CF21; the second terminal of switch S103 is connected to a common-mode signal (VCM); the second terminal of switch CF21 is connected to the first terminals of switches S133 and SF41; the second terminal of switch S133 is connected to a positive feedback signal (VB+); the second terminals of switches SF21, SF41, and S91 are all output terminals connected to the positive input terminal of the multi-bit quantizer. The lower submodule includes switches SF12, SF22, SF32, SF42, SF62, S92, S134, and S104; and capacitors CF12 and CF22. Specifically, the first terminals of switches SF12, SF32, and S92 are all connected to the second input terminal of the chopper operational amplifier; the second terminal of switch SF12 is connected to the first terminal of capacitor CF12; the second terminal of capacitor CF12 is connected to the first terminals of switches SF22 and SF62; the second terminal of switch SF62 is connected to the common-mode signal (VCM); the second terminal of switch SF32 is connected to the first terminal of switch S104 and capacitor CF22; the second terminal of switch S104 is connected to the common-mode signal (VCM); the second terminal of switch CF22 is connected to the first terminals of switches S134 and SF42; the second terminal of switch S134 is connected to the negative feedback signal (VB-); the second terminals of switches SF22, SF42, and S92 are all output terminals connected to the negative input terminal of the multi-bit quantizer.

7. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, The chopper operational amplifier includes: an operational amplifier and two chopper switches; Wherein, the first input terminal of the first chopper switch serves as the first input terminal of the chopper operational amplifier, and the second input terminal of the first chopper switch serves as the second input terminal of the chopper operational amplifier; the first output terminal of the first chopper switch is connected to the first input terminal of the operational amplifier, the second output terminal of the first chopper switch is connected to the second input terminal of the operational amplifier, the first output terminal of the operational amplifier is connected to the first input terminal of the second chopper switch, the second output terminal of the operational amplifier is connected to the second input terminal of the second chopper switch, the first output terminal of the second chopper switch serves as the first output terminal of the chopper operational amplifier, and is connected to the positive input terminal of the multi-bit quantizer; the second output terminal of the second chopper switch serves as the second output terminal of the chopper operational amplifier, and is connected to the negative input terminal of the multi-bit quantizer.

8. The multi-bit quantization hardware multiplexing extended counting analog-to-digital converter according to claim 1, characterized in that, The multi-bit quantizer is a 2.5-bit quantizer, which includes multiple dynamic latch comparators and flip-flops; The first input terminal of each dynamic latch is connected to the first output terminal of the chopper operational amplifier, and the second input terminal of each dynamic latch is connected to the second output terminal of the chopper operational amplifier; the output terminal of each dynamic latch is connected to the input terminal of a flip-flop; and the output terminal of each flip-flop is connected to the input terminal of the counter and the digital logic processing unit.

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