Test circuitry for testing multi-cycle path circuitry

Abstract

Test circuitry for testing a multi-cycle path circuit includes on-chip clock controller circuitry and first clock adjustment circuitry. The on-chip clock controller circuitry is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and to generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuitry is configured to generate a first test clock signal from the first control signal and the internal clock signal for testing a multi-cycle path circuit. The plurality of first bits is configured to set a first pulse in the first test clock signal to avoid a timing violation in the multi-cycle path circuit.

Description

Technical Field

[0001] This case concerns test circuit systems, particularly test circuit systems that can be used to test multi-cycle path circuits. Background Technology

[0002] To ensure a chip meets design requirements, timing analysis can be performed to ensure that multiple circuits within the chip operate correctly. When a chip contains multicycle path circuits, existing testing methods require disabling these circuits or reducing the clock signal speed to avoid timing errors, resulting in decreased test coverage. In other related technologies, to obtain test results for multicycle path circuits, the test data from an automatic test pattern generator can be adjusted to attempt to estimate a suitable clock signal for the circuit. However, in practical applications, this estimation method may lead to excessively long runtime for the automatic test pattern generator, or the generator may fail to generate suitable test data for estimation. Summary of the Invention

[0003] In some embodiments, one of the objectives of this invention is (but not limited to) to provide a test circuit system that can utilize multiple bits to configure the clock signal for testing multi-cycle path circuits.

[0004] In some embodiments, the test circuit system includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit generates an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generates a first control signal in response to the scan enable signal, the plurality of first bits, and the reference clock signal. The first clock adjustment circuit generates a first test clock signal based on the first control signal and the internal clock signal to test a multicycle path circuit. The plurality of first bits are used to set a first pulse in the first test clock signal to prevent a timing violation in the multicycle path circuit.

[0005] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a test circuit system drawn according to some embodiments of this case; Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of the on-chip clock controller circuit; Figure 3 Drawing based on some embodiments of this case Figure 2 A schematic diagram of the scanning control circuit in the image; Figure 4 Drawing based on some embodiments of this case Figure 2 A schematic diagram of the test clock control circuit in the diagram; and Figure 5 Drawing based on some embodiments of this case Figure 2 A schematic diagram of another test clock control circuit. Detailed Implementation

[0007] All terms used herein have their common meanings. The definitions of the terms used in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this document. Similarly, this document is not limited to the various embodiments shown in this specification.

[0008] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term “circuit” can be a single system formed by at least one circuit, and the term “circuit” can be a device that connects at least one transistor and / or at least one active or passive component in a certain manner to process signals.

[0009] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, and third, etc., are used herein to describe and distinguish the individual components. Therefore, a first component may also be referred to as a second component without departing from the intent of this document. For ease of understanding, similar components in the accompanying figures will be designated with the same reference numerals.

[0010] Figure 1 This is a schematic diagram of a test circuit system 100 according to some embodiments of the present invention. The test circuit system 100 can test a multicycle path circuit 100B, a single cycle path circuit 100A, and a single cycle path circuit 100C (e.g., scan testing, static timing analysis, etc.). In this example, the single cycle path circuit 100A, multicycle path circuit 100B, and single cycle path circuit 100C are sequentially connected in series. In some embodiments, the test circuit system 100 can be integrated with the multicycle path circuit 100B, single cycle path circuit 100A, and single cycle path circuit 100C into a single chip.

[0011] In some embodiments, the signal (or data) transmitted between the two buffers (or flip-flops) in the multi-cycle path circuit 100B requires at least two cycles to stabilize. In other words, at least two cycles are required between the setup time and hold time of the multi-cycle path circuit 100B. For example, the transmission between the input of the multi-cycle path circuit 100B (e.g., the signal path between the single-cycle path circuit 100A and the multi-cycle path circuit 100B) and the output of the multi-cycle path circuit 100B (e.g., the signal path between the multi-cycle path circuit 100B and the single-cycle path circuit 100C) requires at least two cycles. In some embodiments, the signal (or data) transmitted between the two buffers (or flip-flops) in the single-cycle path circuit 100A (or 100C) stabilizes in only one cycle. In different embodiments, each of the multi-cycle path circuit 100B, the single-cycle path circuit 100A, and the single-cycle path circuit 100C may be implemented by several digital logic circuits.

[0012] The test circuit system 100 includes an on-chip clock (OCC) controller circuit 110, a clock adjustment circuit 120, and a clock adjustment circuit 130. The OCC controller circuit 110 can generate an internal clock signal CLKT in response to a reference clock signal CLKR, a scan enable signal SEN, multiple enable bits EN[0] to EN[3], and a scan mode signal SM. In some embodiments, the reference clock signal CLKR can be generated by, but is not limited to, a phase-locked loop circuit. Furthermore, the OCC controller circuit 110 can also generate a control signal SC1 in response to the scan enable signal SEN, multiple bits B1[0] to B1[3], and the reference clock signal CLKR, and can generate a control signal SC2 in response to the scan enable signal SEN, multiple bits B2[0] to B2[3], and the reference clock signal CLKR.

[0013] Clock adjustment circuit 120 is used to generate test clock signal CLK1 in response to control signal SC1 and internal clock signal CLKT to test multi-cycle path circuit 100B. Clock adjustment circuit 130 is used to generate test clock signal CLK2 in response to control signal SC2 and internal clock signal CLKT to test single-cycle path circuit 100A and single-cycle path circuit 100C.

[0014] In some embodiments, the clock adjustment circuit 120 includes a logic gate circuit 121 and a clock gating circuit 122. The logic gate circuit 121 generates an enable signal EN1 in response to an inverted version of the control signal SC1. For example, the logic gate circuit 121 may be (but is not limited to) an AND gate circuit with an inverted input, wherein the inverted input receives the control signal SC1, and the other input can receive a test signal F1. In some embodiments, the test signal F1 may be (but is not limited to) test data from an automatic test pattern generator. The clock gating circuit 122 generates a test clock signal CLK1 in response to the generated enable signal EN1 and an internal clock signal CLKT. For example, the clock gating circuit 122 may be (but is not limited to) an integrated clock gating (ICG) cell, which determines whether to generate a pulse for the output test clock signal CLK1 based on the generated enable signal EN1.

[0015] In some embodiments, clock adjustment circuit 120 and clock adjustment circuit 130 have the same circuit structure. For example, similar to clock adjustment circuit 120, clock adjustment circuit 130 may include a logic gate circuit 131 and a clock gate control circuit 132. Logic gate circuit 131 is used to generate an enable signal EN2 in response to an inverted control signal SC2. For example, logic gate circuit 131 may be (but is not limited to) an AND gate circuit with an inverting input, wherein the inverting input receives the control signal SC2, and the other input (i.e., the non-inverting input) can receive a test signal F2. In some embodiments, test signal F2 may be (but is not limited to) test data from an automatic test pattern generator. Clock gate control circuit 132 can generate a test clock signal CLK2 in response to the generated enable signal EN2 and an internal clock signal CLKT. For example, clock gate control circuit 132 may be (but is not limited to) an integrated clock gate control unit, which can sequentially determine whether to generate multiple pulses of the output test clock signal CLK2 according to the generated enable signal EN2.

[0016] Using the above configuration, multiple bits B1[0] to B1[3] can be used to set at least one pulse of the test clock signal CLK1 to avoid timing violations in the multi-cycle path circuit 100B. In some embodiments, timing violations may include (but are not limited to) hold time violations, setup time violations, etc. Furthermore, in this example, multiple bits B1[0] to B1[3] and multiple bits B2[0] to B2[3] can also be used to set the interval between pulses (e.g., pulse P1') in the test clock signal CLK1 and pulses (e.g., pulses P_0 to P_3) in the test clock signal CLK2 to avoid the aforementioned timing violations.

[0017] by Figure 1 For example, when a single-cycle path circuit 100A is triggered by pulse P0 of the internal clock signal CLKT, it can generate a stable output to the multi-cycle path circuit 100B within one cycle (corresponding to one pulse width). Therefore, the multi-cycle path circuit 100B can receive the output of the single-cycle path circuit 100A by being triggered by pulse P1 of the internal clock signal CLKT, and generate a stable output after two cycles (corresponding to two pulse widths). Therefore, the single-cycle path circuit 100C can receive the output of the multi-cycle path circuit 100B for subsequent operations by being triggered by pulse P3 of the internal clock signal CLKT. In this way, all timing violations can be avoided without reducing the speed of the internal clock signal CLKT, allowing for proper testing of the single-cycle path circuit 100A, the multi-cycle path circuit 100B, and the single-cycle path circuit 100C.

[0018] To achieve the above timing sequence, multiple bits B1[0] to B1[3] can be sequentially set to logic value 1, logic value 0, logic value 1 and logic value 1 (marked as B1[3:0]=1101 in the figure), and multiple bits B2[0] to B2[3] can be sequentially set to logic value 0, logic value 1, logic value 1 and logic value 0 (marked as B2[3:0]=0110 in the figure). The OCC controller circuit 110 can generate control signal SC1 corresponding to multiple bits B1[0] to B1[3] (whose waveform has logic value 1, logic value 1, logic value 0 and logic value 0 in the order from left to right) and control signal SC2 corresponding to multiple bits B2[0] to B2[3] (whose waveform has logic value 0, logic value 1, logic value 1 and logic value 0 in the order from left to right). In this way, the clock adjustment circuit 120 can respond to the inversion of multiple bits in the control signal SC1 and output the pulse P1 of the internal clock signal CLKT as the pulse P1' of the test clock signal CLK1.

[0019] For example, since bit B1[3] has a logic value of 1, and the inverted state of bit B1[3] is a logic value of 0, the logic gate circuit 121 can output an enable signal EN1 with a logic value of 0. Under this condition, the clock gate circuit 122 blocks (or disables) the pulse P3 of the internal clock signal CLKT, thereby removing the corresponding pulse P3' of the test clock signal CLK1 (drawn as a dashed line). Similarly, in response to bits B1[0] and B1[2], the clock gate circuit 122 blocks (or disables) the pulses P0 and P2 of the internal clock signal CLKT, thereby removing the pulses P0' and P2' of the test clock signal CLK1 (drawn as a dashed line). Conversely, since bit B1[1] has a logic value of 0, and the inverted state of bit B1[1] is a logic value of 1, the logic gate circuit 121 outputs an enable signal EN1 with a logic value of 1 (assuming the test signal F1 has a logic value of 1). Under these conditions, the clock gate circuit 132 does not block the pulse P1 of the internal clock signal CLKT, and outputs the pulse P1 as the pulse P1' of the test clock signal CLK1. Based on a similar operation, the clock adjustment circuit 130 can respond to the inversion of multiple bits in the control signal SC2 to output the pulses P0 and P3 of the internal clock signal CLKT as the pulses P_0 and P_3 of the test clock signal CLK2, and remove the pulses P_1 and P_2 (drawn as dashed lines) of the test clock signal CLK2. Equivalently, by setting multiple bits B1[0]~B1[3] and multiple bits B2[0]~B2[3], the interval between the pulse P1' in the test clock signal CLK1 and the pulses P_0 and P_3 in the test clock signal CLK2 can be set. For example, as Figure 1 As shown, pulses P1', P_0, and P_3 are multiple pulses that are not consecutive. This avoids timing violations in the circuit under test (e.g., multi-cycle path circuit 100B, single-cycle path circuit 100A, and single-cycle path circuit 100C).

[0020] It should be understood that the number of control signals (i.e., control signals SC1 and SC2) generated by the OCC controller circuit 110 will vary depending on different practical needs (e.g., different circuit architectures under test). In different embodiments, the number of control signals generated by the OCC controller circuit 110 may be at least one. For example, if the circuit to be tested only contains a multi-cycle path circuit 100B, the OCC controller circuit 110 may only generate control signal SC1, and the test circuit system 100 may only contain clock adjustment circuit 120. Therefore, this application does not assume that... Figure 1 The setup shown is an example, and the various numbers of clock adjustment circuits and / or various numbers of control signals are all quantities that this case intends to cover.

[0021] Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of the OCC controller circuit 110 is shown. In this example, the OCC controller circuit 110 includes a scan control circuit 210, a test clock control circuit 220, and a test clock control circuit 230. The scan control circuit 210 generates a signal S1 in response to the scan enable signal SEN and the reference clock signal CLKR, and generates an internal clock signal CLKT based on the signal S1, multiple enable bits EN[0] to EN[3], and the scan mode signal SM. The test clock control circuit 220 generates a control signal SC1 in response to the signal S1, multiple bits B1[0] to B1[3], and the reference clock signal CLKR. Similarly, the test clock control circuit 230 generates a control signal SC2 in response to the signal S1, multiple bits B2[0] to B2[3], and the reference clock signal CLKR. In some embodiments, the scan control circuit 210, the test clock control circuit 220, and the test clock control circuit 230 may be synchronized via the signal S1.

[0022] It should be understood that in other embodiments, if the circuit to be tested only contains the multi-cycle path circuit 100B, the OCC controller circuit 110 may only generate the control signal SC1. Under this condition, the OCC controller circuit 110 may not include the test clock control circuit 230.

[0023] Figure 3 Drawing based on some embodiments of this case Figure 2A schematic diagram of the scan control circuit 210 is shown. In some embodiments, the scan control circuit 210 includes a D-type flip-flop circuit 305, multiple D-type flip-flop circuits 310[0] to 310[3], multiple inverter circuits 315[0] to 315[3], multiple logic gate circuits 320[0] to 320[3], logic gate circuit 325, logic gate circuit 330, clock gate circuit 335, logic gate circuit 340, and multiplexer circuit 345. The D-type flip-flop circuit 305 is triggered by a reference clock signal CLKR to transmit the scan enable signal SEN as signal S1. The multiple D-type flip-flop circuits 310[0] to 310[3] are connected in series and triggered by the reference clock signal CLKR to output multiple signals S20[0] to S20[3] in sequence according to signal S1. Each of the multiple inverter circuits 315[0] to 315[3] generates a corresponding signal among the multiple signals S30[0] to S30[3] based on a corresponding signal S1 and a corresponding signal among the multiple signals S20[0] to S20[2]. For example, inverter circuit 315[0] generates signal S30[0] based on signal S1, and inverter circuit 315[1] generates signal S30[1] based on signal S20[0]. By analogy, the arrangement of the remaining inverter circuits 315[2] and 315[3] should be understood.

[0024] Each of the multiple logic gate circuits 320[0] to 320[3] is used to generate a corresponding signal S40[0] to S40[3] based on a corresponding signal among multiple signals S30[0] to S30[3], a corresponding enable bit EN[0] to EN[3], and a corresponding signal S20[0] to S20[3]. For example, logic gate circuit 320[0] generates signal S40[0] based on signal S30[0], enable bit EN[0], and signal S20[0]. Logic gate circuit 320[1] generates signal S40[1] based on signal S30[1], enable bit EN[1], and signal S20[1]. By analogy, the arrangement of the remaining logic gate circuits 320[2] and 320[3] should be understood. In some embodiments, each of the plurality of logic gate circuits 320[0] to 320[3] may be (but is not limited to) an AND gate circuit.

[0025] Logic gate circuit 325 is used to generate signal S5 based on multiple signals S40[0] to S40[3]. In some embodiments, logic gate circuit 325 may be (but is not limited to) an OR gate circuit. Logic gate circuit 330 is used to generate signal S6 based on signal S5 and scan mode signal SM. In some embodiments, logic gate circuit 330 may be (but is not limited to) an OR gate circuit with an inverting input, wherein the inverting input receives scan mode signal SM, and another input (i.e., a non-inverting input) receives signal S5. Clock gate circuit 335 is used to generate clock signal CK based on signal S6 and reference clock signal CLKR. Logic gate circuit 340 generates switching signal SS based on scan mode signal SM and scan enable signal SEN. In some embodiments, logic gate circuit 340 may be (but is not limited to) an OR gate circuit with an inverting input, and multiplexer circuit 345 is used to selectively output scan clock signal CLKS or clock signal CK as internal clock signal CLKT based on switching signal SS.

[0026] Figure 4 Drawing based on some embodiments of this case Figure 2 A schematic diagram of the test clock control circuit 220 is shown. In this example, the test clock control circuit 220 includes multiple D-type flip-flop circuits 410[0]~410[3], multiple inverter circuits 415[0]~415[3], multiple logic gate circuits 420[0]~420[3], and a logic gate circuit 425. The multiple D-type flip-flop circuits 410[0]~410[3] are connected in series and triggered by a reference clock signal CLKR to output multiple signals S21[0]~S21[3] in sequence according to the signal S1.

[0027] Multiple inverter circuits 415[0] to 415[3] generate multiple signals S31[0] to S31[3] based on signal S1 and a portion of signals S21[0] to S21[3]. In some embodiments, a portion of signals S21[0] to S21[3] does not include the last signal S21[3]. That is, the portion of signals may be multiple signals S21[0] to S21[2]. In detail, each of the multiple inverter circuits 415[0] to 415[3] generates a corresponding signal S31[0] to S31[3] based on signal S1 and a corresponding signal S21[0] to S21[2]. For example, inverter circuit 415[0] generates signal S31[0] based on signal S1, and inverter circuit 415[1] generates signal S31[1] based on signal S21[0]. Similarly, the arrangement of the remaining inverter circuit 415[2] and inverter circuit 415[3] should be understood.

[0028] Each of the multiple logic gate circuits 420[0] to 420[3] is used to generate a multiple signal S41[0] to S41[3] based on a corresponding signal among multiple signals S31[0] to S31[3], a corresponding bit among multiple bits B1[0] to B1[3], and a corresponding signal among multiple signals S21[0] to S21[3]. For example, logic gate circuit 420[0] generates signal S41[0] based on signal S31[0], bit B1[0], and signal S21[0]. Logic gate circuit 420[1] generates signal S41[1] based on signal S31[1], bit B1[1], and signal S21[1]. And so on, the arrangement of the remaining logic gate circuits 420[2] and 420[3] should be understood. In some embodiments, each of the plurality of logic gate circuits 420[0] to 420[3] may be (but is not limited to) an AND gate circuit. Logic gate circuit 425 is used to generate a control signal SC1 based on a plurality of signals S41[0] to S41[3]. In some embodiments, logic gate circuit 425 may be (but is not limited to) an OR gate circuit.

[0029] Using the above configuration method, multiple bits of the control signal SC1 can be configured using multiple bits B1[0] to B1[3]. Thus, Figure 1 The clock adjustment circuit 120 can generate the corresponding test clock signal CLK1 accordingly. In other words, the user can set the logic values ​​of multiple bits B1[0] to B1[3] according to the required timing of the multi-cycle path circuit 100B, so as to directly adjust the timing of the test clock signal CLK1 and thus avoid timing violations.

[0030] Figure 5 Drawing based on some embodiments of this case Figure 2 A schematic diagram of the test clock control circuit 230 is shown. In some embodiments, the test clock control circuit 220 and the test clock control circuit 230 may have the same circuit structure. For example, the test clock control circuit 230 includes multiple D-type flip-flop circuits 510[0] to 510[3], multiple inverter circuits 515[0] to 515[3], multiple logic gate circuits 520[0] to 520[3], and a logic gate circuit 525. The multiple D-type flip-flop circuits 510[0] to 510[3] are connected in series and triggered by a reference clock signal CLKR to output multiple signals S22[0] to S22[3] in sequence according to the signal S1.

[0031] Multiple inverter circuits 515[0] to 515[3] generate multiple signals S32[0] to S32[3] based on signal S1 and a portion of signals S22[0] to S22[3]. In some embodiments, a portion of signals S22[0] to S22[3] does not include the last signal S22[3]. That is, the portion of signals may be multiple signals S22[0] to S22[2]. In detail, each of the multiple inverter circuits 515[0] to 515[3] generates a corresponding signal S32[0] to S32[3] based on signal S1 and a corresponding signal S22[0] to S22[2]. For example, inverter circuit 515[0] generates signal S32[0] based on signal S1, and inverter circuit 515[1] generates signal S32[1] based on signal S22[0]. Similarly, the configuration of the remaining inverter circuit 515[2] and inverter circuit 515[3] should be understood.

[0032] Each of the multiple logic gate circuits 520[0] to 520[3] is used to generate a multiple signal S42[0] to S42[3] based on a corresponding signal among multiple signals S32[0] to S32[3], a corresponding bit among multiple bits B2[0] to B2[3], and a corresponding signal among multiple signals S22[0] to S22[3]. For example, logic gate circuit 520[0] generates signal S42[0] based on signal S32[0], bit B2[0], and signal S22[0]. Logic gate circuit 520[1] generates signal S42[1] based on signal S32[1], bit B2[1], and signal S22[1]. And so on, the arrangement of the remaining logic gate circuits 520[2] and 520[3] should be understood. In some embodiments, each of the plurality of logic gate circuits 520[0] to 520[3] may be (but is not limited to) an AND gate circuit. Logic gate circuit 525 is used to generate control signal SC2 according to a plurality of signals S42[0] to S42[3]. In some embodiments, logic gate circuit 525 may be (but is not limited to) an OR gate circuit.

[0033] Similarly, by means of the above configuration, multiple bits of the control signal SC2 can be configured using multiple bits B2[0] to B2[3]. Thus, Figure 1 The clock adjustment circuit 130 can generate a corresponding test clock signal CLK2 accordingly. In other words, if the circuit to be tested contains a multi-cycle path circuit (e.g., a circuit with multiple cycles), the clock adjustment circuit 130 can generate a corresponding test clock signal CLK2. Figure 1 Multi-cycle path circuit 100B) and single-cycle path circuit (e.g., for Figure 1The single-cycle path circuits 100A and 100B allow users to set the logic values ​​of multiple bits B1[0] to B1[3] and multiple bits B2[0] to B2[3] according to the connection method between the multi-cycle path circuit and the single-cycle path circuit and the timing required by both, so as to directly adjust the timing of the test clock signal CLK1 and the test clock signal CLK2, thereby avoiding timing violations. In this way, full-speed testing can be performed without reducing the speed of the internal clock signal CLKT or shutting down the multi-cycle path circuit, so as to obtain higher test coverage.

[0034] The circuit arrangements shown in the above embodiments are for illustrative purposes only and are not intended to limit the scope of this invention. Circuit arrangements capable of performing the same or similar functions are all within the scope of this invention.

[0035] In summary, the test circuit system in some embodiments of this invention can utilize configurable multiple bits to set the timing of the test clock signal. This allows for timing analysis of multi-cycle path circuits without reducing speed, achieving higher test coverage.

[0036] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection of this case shall be determined by the scope of the patent application in this specification.

[0037] [Symbol Explanation]

[0038] 100: Test circuit system

[0039] 100A, 100C: Single-cycle path circuit

[0040] 100B: Multi-cycle path circuit

[0041] 110: On-chip clock controller circuit

[0042] 120: Clock Adjustment Circuit

[0043] 121, 131: Logic gate circuits

[0044] 122, 132, 335: Clock gate control circuit

[0045] 130: Clock Adjustment Circuit

[0046] 210: Scanning control circuit

[0047] 220, 230: Test clock control circuit

[0048] 305, 310[0]~310[3], 410[0]~410[3], 510[0]~510[3]: D-type flip-flop circuit

[0049] 315[0]~315[3], 415[0]~415[3], 515[0]~515[3]: Inverter circuit

[0050] 320[0]~320[3], 420[0]~420[3], 520[0]~520[3]: Logic gate circuit

[0051] 325, 425, 525: Logic gate circuits

[0052] 330, 340: Logic gate circuit

[0053] 345: Multiplexer Circuit

[0054] B1[0]~B1[3], B1[3:0], B2[0]~B2[3], B2[3:0]: bits

[0055] CK: Clock signal

[0056] CLK1, CLK2: Test clock signals

[0057] CLKR: Reference clock signal

[0058] CLKS: Scan clock signal

[0059] CLKT: Internal clock signal

[0060] EN[0]~EN[3]: Enable bits

[0061] EN1, EN2: The obtained enable signals

[0062] F1, F2: Test signals

[0063] P0~P3, P0'~P3', P_0~P_3: Pulse

[0064] S1: Signal

[0065] S20[0]~S20[3]、S21[0]~S21[3]、S22[0]~S22[3]:Signals

[0066] S30[0]~S30[3]、S31[0]~S31[3]、S32[0]~S32[3]:Signals

[0067] S40[0]~S40[3]、S31[0]~S31[3]、S42[0]~S42[3]:Signals

[0068] S5, S6: Signals

[0069] SC1, SC2: Control signals

[0070] SEN: Scan Enable Signal

[0071] SM: Scan mode signal

[0072] SS: Switching signal.

Claims

1. A test circuit system, comprising: An on-chip clock controller circuit is used to generate an internal clock signal in response to a reference clock signal, a scan enable signal, multiple enable bits and a scan mode signal, and to generate a first control signal in response to the scan enable signal, multiple first bits and the reference clock signal. as well as A first clock adjustment circuit is provided to generate a first test clock signal based on the first control signal and the internal clock signal, in order to test a multi-cycle path circuit. The plurality of first bits are used to set a first pulse in the first test clock signal to avoid a timing violation in the multi-cycle path circuit. The clock controller circuit on this chip includes: A scan control circuit is used to generate a first signal in response to the scan enable signal and the reference clock signal, and to generate the internal clock signal based on the first signal, the plurality of enable bits and the scan mode signal. as well as A test clock control circuit is used to generate the first control signal in response to the first signal, the plurality of first bits, and the reference clock signal. The test clock control circuit is used for: Multiple second signals are output sequentially based on the reference clock signal and the first signal; Multiple third signals are generated based on the first signal and a portion of the multiple second signals; Multiple fourth signals are generated based on the multiple first bits, the multiple third signals, and the multiple second signals; as well as The first control signal is generated based on the plurality of fourth signals.

2. The test circuit system according to claim 1, wherein the scan control circuit and the test clock control circuit are synchronized via the first signal.

3. The test circuit system according to claim 1, wherein the test clock control circuit comprises: Multiple D-type flip-flop circuits are connected in series sequentially and used to trigger via the reference clock signal and output multiple second signals sequentially according to the first signal; Multiple inverter circuits are used to generate multiple third signals based on the first signal and a portion of the multiple second signals; A plurality of first logic gate circuits, wherein each of the plurality of first logic gate circuits is configured to generate a corresponding of a plurality of fourth signals based on a corresponding of a plurality of first bits, a corresponding of a plurality of third signals, and a corresponding of a plurality of second signals. as well as A second logic gate circuit is used to generate the first control signal based on the plurality of fourth signals.

4. The test circuit system according to claim 3, wherein a portion of the plurality of second signals does not include the last signal among the plurality of second signals.

5. The test circuit system of claim 1, wherein the on-chip clock controller circuit is further configured to generate a second control signal in response to the scan enable signal, the plurality of second bits, and the reference clock signal, and the test circuit system further comprises: A second clock adjustment circuit is provided to generate a second test clock signal based on the second control signal and the internal clock signal to test a single-cycle path circuit, wherein the single-cycle path circuit is coupled to the multi-cycle path circuit.

6. The test circuit system according to claim 5, wherein the plurality of first bits and the plurality of second bits are used to set the interval between the first pulse and the plurality of second pulses in the second test clock signal, so as to avoid the timing violation.

7. The test circuit system according to claim 6, wherein the first pulse and the plurality of second pulses are discontinuous pulses.

8. The test circuit system according to claim 1, wherein the first clock adjustment circuit comprises: A logic gate circuit is used to generate a resulting enable signal in response to an inverted version of the first control signal; and A clock gate circuit is used to generate the first test clock signal in response to the obtained enable signal and the internal clock signal.

9. The test circuit system according to claim 8, wherein the logic gate circuit is an AND gate circuit having an inverting input terminal, and the inverting input terminal is used to receive the first control signal.

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