A test vector reordering method and system suitable for 3D packaged chips

Abstract

This invention discloses a test vector reordering method and system suitable for three-dimensional packaged chips, comprising the following steps: obtaining an initial test sequence tv0 and the failure rate of each test vector; sorting the initial test sequence tv0 in descending order according to the failure rates of all test vectors to generate a new test sequence tv2; starting from the 0th test vector of the new test sequence tv2, accumulating the failure rates from high to low until the accumulated result is greater than the accumulated threshold to obtain high failure rate test vectors; if there is only one high failure rate test vector belonging to a unit under test, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the high failure rate vector list, and the actual number of high failure rate test vectors is denoted as N. hfr The invention involves obtaining an initial test sequence and performing tests using that sequence. Its advantages include reducing testing time and improving testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing, and more specifically to a test vector reordering method and system suitable for three-dimensional packaged chips. Background Technology

[0002] 3D stacked chips are assembled from multiple chiplets connected by through silicon vias (TSVs). A key advantage is improved chiplet yield, flexible process selection for each chiplet, and reduced manufacturing costs. Because 3D stacked chips contain multiple chiplets, and each chiplet integrates multiple IP cores or functional units, modular testing schemes are often used to shorten the length of individual test vectors. That is, each test vector only tests a specified unit under test, such as a portion of the chiplets or IP cores; each unit under test is tested independently. Different units under test correspond to different test vector lengths and have different scan chain paths, therefore, the scan path configuration needs to be adjusted in real time during testing.

[0003] Test vector sequence reordering optimization is an effective way to improve chip testing efficiency and reduce testing time. Current reordering schemes in the literature are all designed for chips with only one core, and are not suitable for testing three-dimensional stacked chips assembled from multiple cores. Testing such chips requires frequent switching of scan paths, thus necessitating consideration of the configuration time of the new scan chain and the additional test vector added before the scan chain switch to respond to the removal of the previous test vector; these are all unique to three-dimensional stacked chip testing.

[0004] Conventional 3D test vector sequences are organized sequentially by the unit under test (DUT); all test vectors for the same DUT are grouped together and sorted by their failure rates from highest to lowest. Using this sequence, the next DUT is only introduced after all vectors from the previous DUT have been tested. Therefore, test vectors with high failure rates from later DUTs are sent to the chip under test too late, significantly increasing the detection time for many faulty chips. These test vectors should be moved forward in the test sequence to improve the overall efficiency of chip testing. However, after moving a high failure rate test vector forward (to position i), the scan path corresponding to this test vector may differ from the scan paths of its newly adjacent preceding and following test vectors (the (i-1)th and (i+1)th vectors). Therefore, an additional test vector with the same scan path and length must be introduced immediately after the test vector whose scan path is about to switch (the (i-1)th and (i)th vectors) to serially remove the test response of the moved test vector from the chip's TDO pin; this also adds an extra scan path configuration operation. All of the above processes increase testing time costs, resulting in low testing efficiency. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the existing three-dimensional test vector sequence test has high testing time cost and low testing efficiency.

[0006] This invention solves the above-mentioned technical problems through the following technical means: a test vector reordering method suitable for three-dimensional packaged chips, comprising the following steps:

[0007] Step 1: Obtain the initial test sequence tv0 and the failure rate of each test vector;

[0008] Step 2: Sort the initial test sequence tv0 in descending order according to the failure rate of all test vectors, and generate a new test sequence tv2;

[0009] Step 3: Starting from the 0th test vector of the new test sequence tv2, accumulate the results of each vector in descending order of failure rate until the (k-1)th vector. If the accumulated result is greater than the accumulation threshold, then the corresponding test vector is considered a high failure rate test vector, generating a list of high failure rate test vectors. k is the initial value for the number of high failure rate test vectors. If a unit under test has only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quartile of all high failure rate test vectors, this high failure rate test vector is deleted from the list of high failure rate test vectors. Let N be the actual number of high failure rate test vectors. hfr ;

[0010] Step 4: Create a new sequence tv, whose first N is... hfr The test vectors are the high failure rate test vectors in the new test sequence tv2, arranged in descending order. The high failure rate test vectors are deleted from the initial test sequence tv0, and the remaining part of the initial test sequence tv0 is appended to the sequence tv to form the initial tuning test sequence. The initial tuning test sequence is used for testing.

[0011] Further, step one includes:

[0012] Through formula Obtain the initial test sequence tv0;

[0013] Among them, TV i,j It is the j-th largest test vector in the i-th unit under test, sorted in descending order of failure rate. 1,0 It is the test vector with the highest failure rate in the first unit under test; N is the number of units under test; Ltv i It is the number of test vectors contained in the i-th unit to be tested.

[0014] Furthermore, the step of accumulating the results from the 0th test vector of the new test sequence tv2 in descending order of failure rate until the (k-1)th vector, where the accumulated result is greater than the accumulated threshold, includes:

[0015] Through formula Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, where P i Let P be the failure rate of the i-th test vector. th It is an accumulated threshold set to divide test vectors with high failure rates.

[0016] Furthermore, the test vector reordering method for three-dimensional packaged chips also includes step five, which includes:

[0017] Step 501: Calculate the expected value of the test time corresponding to the initial test sequence;

[0018] Step 502: Use the initial test sequence as the new test sequence tv2;

[0019] Step 503: Determine whether the id-th test vector tv2[id] and the (id-1)-th test vector tv2[id-1] of the new test sequence tv2 belong to the same test unit. If yes, proceed to step 506; otherwise, execute step 504.

[0020] Step 504: tv2[id-1] belongs to the j-th unit to be tested. In the new test sequence tv2, the test vectors tv2[id+1] and tv2[N] are... hfr Between -1], find the next test vector belonging to the j-th test unit; if the test vector tv2[i] meets the condition, move tv2[i] to the position of tv2[id] so that tv2[id-1] and tv2[id] belong to the same test unit, and move the original tv2[id] to tv2[i-1] in the test sequence one position to the right;

[0021] Step 505: Calculate the expected value of the test time corresponding to the new test sequence tv2. If the expected value of its test time is lower than the expected value of the test time corresponding to the initial test sequence, then adopt the sequence generated in step 504 after the exchange order and use it as the initial test sequence. Otherwise, restore the new test sequence tv2 to the initial test sequence in step 501 before the misalignment exchange.

[0022] Step 506, id+1, return to step 503 to continue calculating the next test vector, until the Nth... hfr -1 test vectors have been calculated.

[0023] Furthermore, the expected value L of the test time exp The calculation process is as follows:

[0024]

[0025] Q0 = 1, Q i=(1-P i-1 )Q i-1 (i = 1 ~ N) tv -1)

[0026]

[0027]

[0028] L exp = (1-Y)·L exp,fault +Y·L pass

[0029] Among them, L exp,fault L represents the expected time required to detect the fault in a group of faulty chips, representing a proportion of 1-Y. i N is the length of the i-th test vector in the test sequence. tv Q is the number of test vectors. i-1 This represents the probability that a faulty chip cannot be detected by the first i-1 test vectors. Q i It is the probability that the faulty chip cannot be detected by the first i test vectors, and it is the probability that the faulty chip cannot be detected by the first i-1 vectors (Q). i-1 ), and also through the detection of (1-P) by the i-th vector. i The conditional probability of S. i The test time (TCK cycles) required for the i-th test vector, including the time L consumed by that test vector. i and the configuration time L for scan chain switching conf , The length of the last test vector, i.e., in Li, i = N tv -1, P i-1 T represents the failure rate of the (i-1)th test vector in the test sequence. i Indicates the Tth i There are n units to be tested, and the i-th test vector belongs to the T-th unit. i One unit to be tested, L conf L pass It is the fixed testing time for a normal chip with a yield of Y, where Y is the yield.

[0030] This invention also provides a test vector reordering system suitable for three-dimensional packaged chips, comprising:

[0031] The initialization module is used to obtain the initial test sequence tv0 and the failure rate of each test vector;

[0032] The reordering module is used to sort the initial test sequence tv0 in descending order according to the failure rate of all test vectors and generate a new test sequence tv2.

[0033] The sequence processing module is used to start from the 0th test vector of the new test sequence tv2, and accumulate the failure rates of each vector from high to low until the (k-1)th vector. If the accumulated result is greater than the accumulated threshold, then the corresponding test vector is considered a high failure rate test vector, and a list of high failure rate test vectors is generated. k is the initial value of the number of high failure rate test vectors. If a test unit has only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the list of high failure rate test vectors. Let N be the actual number of high failure rate test vectors. hfr ;

[0034] The initial test sequence generation module is used to create a new sequence tv, whose first N... hfr The test vectors are the high failure rate test vectors in the new test sequence tv2, arranged in descending order. The high failure rate test vectors are deleted from the initial test sequence tv0, and the remaining part of the initial test sequence tv0 is appended to the sequence tv to form the initial tuning test sequence. The initial tuning test sequence is used for testing.

[0035] Furthermore, the initialization module is also used for:

[0036] Through formula Obtain the initial test sequence tv0;

[0037] Among them, TV i,j It is the j-th largest test vector in the i-th unit under test, sorted in descending order of failure rate. 1,0 It is the test vector with the highest failure rate in the first unit under test; N is the number of units under test; Ltv i It is the number of test vectors contained in the i-th unit to be tested.

[0038] Furthermore, the step of accumulating the results from the 0th test vector of the new test sequence tv2 in descending order of failure rate until the (k-1)th vector, where the accumulated result is greater than the accumulated threshold, includes:

[0039] Through formula Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, where P i Let P be the failure rate of the i-th test vector. th It is an accumulated threshold set to divide test vectors with high failure rates.

[0040] Furthermore, the test vector reordering system suitable for three-dimensional packaged chips further includes a sequence update module, which is used for:

[0041] Step 501: Calculate the expected value of the test time corresponding to the initial test sequence;

[0042] Step 502: Use the initial test sequence as the new test sequence tv2;

[0043] Step 503: Determine whether the id-th test vector tv2[id] and the (id-1)-th test vector tv2[id-1] of the new test sequence tv2 belong to the same test unit. If yes, proceed to step 506; otherwise, execute step 504.

[0044] Step 504: tv2[id-1] belongs to the j-th unit to be tested. In the new test sequence tv2, the test vectors tv2[id+1] and tv2[N] are... hfr Between -1], find the next test vector belonging to the j-th test unit; if the test vector tv2[i] meets the condition, move tv2[i] to the position of tv2[id] so that tv2[id-1] and tv2[id] belong to the same test unit, and move the original tv2[id] to tv2[i-1] in the test sequence one position to the right;

[0045] Step 505: Calculate the expected value of the test time corresponding to the new test sequence tv2. If the expected value of its test time is lower than the expected value of the test time corresponding to the initial test sequence, then adopt the sequence generated in step 504 after the exchange order and use it as the initial test sequence. Otherwise, restore the new test sequence tv2 to the initial test sequence in step 501 before the misalignment exchange.

[0046] Step 506, id+1, return to step 503 to continue calculating the next test vector, until the Nth... hfr -1 test vectors have been calculated.

[0047] Furthermore, the expected value L of the test time exp The calculation process is as follows:

[0048]

[0049] Q0 = 1, Q i =(1-P i-1 )Q i-1 (i = 1 ~ N) tv -1)

[0050]

[0051]

[0052] L exp = (1-Y)·L exp,fault +Y·L pass

[0053] Among them, L exp,fault L represents the expected time required to detect the fault in a group of faulty chips, representing a proportion of 1-Y. i N is the length of the i-th test vector in the test sequence. tv Q is the number of test vectors. i-1 This represents the probability that a faulty chip cannot be detected by the first i-1 test vectors. Q i It is the probability that the faulty chip cannot be detected by the first i test vectors, and it is the probability that the faulty chip cannot be detected by the first i-1 vectors (Q). i-1 ), and also through the detection of (1-P) by the i-th vector. i The conditional probability of S. i The test time (TCK cycles) required for the i-th test vector, including the time L consumed by that test vector. i and the configuration time L for scan chain switching conf , The length of the last test vector, i.e., in Li, i = N tv -1, P i-1 T represents the failure rate of the (i-1)th test vector in the test sequence. i Indicates the Tth i There are n units to be tested, and the i-th test vector belongs to the T-th unit. i One unit to be tested, L conf L pass It is the fixed testing time for a normal chip with a yield of Y, where Y is the yield.

[0054] The advantages of this invention are as follows: This invention sorts the entire tv0 sequence in descending order, breaking the organization method of grouping by the unit under test, and generates a new test sequence tv2. Based on tv2, a list of high failure rate test vectors is generated. If a unit under test belongs to only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the high failure rate test vector list. This avoids switching the scan path twice for this single high failure rate test vector, reducing test time and greatly improving test efficiency. Furthermore, the initial tuning test sequence is constructed, with its first N... hfr One is a high failure rate test vector in the tv2 sequence. The test priority of high failure rate vectors is increased, which further improves test efficiency. Attached Figure Description

[0055] Figure 1 This is a flowchart of a test vector reordering method for three-dimensional packaged chips disclosed in an embodiment of the present invention;

[0056] Figure 2This is a flowchart of step S5 in a test vector reordering method for three-dimensional packaged chips disclosed in an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Example 1

[0059] This invention provides a test vector reordering method suitable for 3D packaged chips. The entire method requires obtaining the chip testing time to determine whether the proposed solution reduces testing time compared to existing conventional solutions. Therefore, given a test sequence, the time required for chip fault detection is calculated, as follows:

[0060] For a given N tv The expected value L of the test time (TCK cycles) required to determine whether a 3D stacked chip under test is normal or faulty using a test sequence of test vectors. exp for:

[0061]

[0062] Expected value L of chip detection time measured in TCK cycles exp It consists of two parts: a fixed test time L for normal chips with a yield of Y. pass (All test vectors must be passed before a chip can be considered a normal chip); and the expected time L required to detect the faulty chips, which account for 1-Y. exp,fault L i and P i These are the length and failure rate of the i-th test vector in the test sequence, respectively; L conf This is the time required to configure the scan path; the i-th test vector belongs to the T-th... i There are 1 unit under test. All indices start from 0. During testing, if a test vector detects a fault, all remaining test vectors are skipped, and the chip is directly marked as a faulty chip.

[0063] Here, the failure rate P iDefined as: the proportion of faulty chips detected by the i-th test vector in the test sequence out of all faulty chips. In practical operation, using a large number of faulty chips as a sample, all test vectors are fed into each faulty chip, and the number of faulty chips that each test vector can detect is collected, thus calculating the failure rate. The sum of the failure rates of all test vectors is normalized to 1.

[0064] like Figure 1 As shown, the test vector reordering method of the present invention includes the following steps:

[0065] S1: Obtain the initial test sequence tv0 and the failure rate of each test vector; the specific process of S1 is as follows:

[0066] The standard test sequence is organized as follows.

[0067]

[0068] Among them, TV ij It is the j-th largest test vector in the i-th unit under test, sorted in descending order of failure rate, such as tv 1,0 It is the test vector with the highest failure rate in the first unit under test; N is the number of units under test; Ltv i This represents the number of test vectors contained in the i-th unit under test. A standard test sequence involves arranging each unit under test in descending order of failure rate, and then sequentially concatenating the units. The standard sequence organized by unit under test is used as the initial test sequence tv0. In this embodiment, the initial test sequence tv0 and the failure rate of each test vector are read from the input file.

[0069] S2: Sort the initial test sequence tv0 in descending order according to the failure rate of all test vectors, break the organization method of grouping by the unit under test, and generate a new test sequence tv2;

[0070] S3: Starting from the 0th test vector of the new test sequence tv2, accumulate the test vectors according to their failure rates from high to low until the (k-1)th vector. If the accumulated result is greater than the accumulated threshold, then the corresponding test vector is considered a high failure rate test vector, and a list of high failure rate test vectors is generated. k is the initial value of the number of high failure rate test vectors. If a unit under test has only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the list of high failure rate test vectors. Let N be the actual number of high failure rate test vectors. hfr The specific process is as follows:

[0071] Starting from the 0th test vector in the tv2 sequence, increment the failure rates sequentially from high to low until the (k-1)th vector, such that:

[0072]

[0073] Where P th This is the cumulative threshold set to divide test vectors into High Fault Ratio (HFR) vectors, and k is the initial value for the number of HFR test vectors. Subsequently, the test priority of these HFR vectors will be increased, placing them first in the test sequence.

[0074] If a unit under test (DUT) belongs to only one HFR test vector, and the failure rate of that HFR vector ranks in the bottom quartile of all HFR vectors, this HFR vector will be removed from the HFR vector list. Otherwise, two scan paths need to be switched for this single test vector (the scan path corresponding to this test vector must be different from the paths of its two adjacent test vectors). The additional test time due to the change in scan chain will likely outweigh the time saved by moving the HFR vector forward, thus reducing test efficiency. After the operation, let N be the actual number of HFR test vectors. hfr .

[0075] S4: Create a new sequence tv, whose first N is... hfr The test vectors are the high-failure-rate test vectors in the new test sequence tv2, arranged in descending order. These high-failure-rate test vectors are removed from the initial test sequence tv0, and the remaining portion of the initial test sequence tv0 is appended to the sequence tv. This tv is the initial tuning test sequence, which is then used for testing. This process increases the testing priority of the HFR vectors without introducing excessive scan path switching, thus effectively shortening the testing time.

[0076] S5, such as Figure 2 As shown, the test vector reordering method further includes step S5, which involves further adjusting the order of the HFR vectors in the initial test sequence to further reduce the expected test time Lexp calculated by formula 1. The specific process is as follows:

[0077] Step 501: Calculate the expected value of the test time corresponding to the initial test sequence;

[0078] Step 502: Use the initial test sequence as the new test sequence tv2;

[0079] Step 503: Determine whether the id-th test vector tv2[id] and the (id-1)-th test vector tv2[id-1] of the new test sequence tv2 belong to the same test unit. If yes, proceed to step 506; otherwise, execute step 504.

[0080] Step 504: tv2[id-1] belongs to the j-th unit to be tested. In the new test sequence tv2, the test vectors tv2[id+1] and tv2[N] are... hfrBetween -1], find the next test vector belonging to the j-th test unit; if the test vector tv2[i] meets the condition, move tv2[i] to the position of tv2[id] so that tv2[id-1] and tv2[id] belong to the same test unit, and move the original tv2[id] to tv2[i-1] in the test sequence one position to the right;

[0081] Step 505: Calculate the expected value of the test time corresponding to the new test sequence tv2. If the expected value of its test time is lower than the expected value of the test time corresponding to the initial test sequence, then adopt the sequence generated in step 504 after the exchange order and use it as the initial test sequence. Otherwise, restore the new test sequence tv2 to the initial test sequence in step 501 before the misalignment exchange.

[0082] Step 506, id+1, return to step 503 to continue calculating the next test vector, until the Nth... hfr -1 test vectors have been calculated.

[0083] The pseudocode for optimizing the initial tuning sequence is shown below.

[0084]

[0085] The following two specific simulation examples demonstrate the effectiveness of the present invention.

[0086] Case 1:

[0087] The above reordering algorithm is applied to a 3D stacked chip containing 6 test cells. The number of test vectors in each test cell, the length of the test vectors, and the failure rate of each test vector within each test cell (arranged in descending order) are shown in Table 1. In Formula 1, the chip yield Y is taken as 60%, and in Formula 3, the cumulative threshold P... th It is 0.55.

[0088] Table 1 Test vector configuration in simulation

[0089]

[0090] Where U0~U5 are the test units 0~5, the table above, viewed vertically from left to right, represents the initial conventional test sequence, as shown in Formula 2. Within each test unit, they are first arranged in descending order of test vector failure rate, and then sequentially assembled according to the order of test units 0~5.

[0091] The initial test sequence after executing algorithm flows S1 to S5 is shown in Table 2. The three columns labeled N, unit, and id respectively indicate the sequential number of each vector in the test sequence, the number of the unit under test to which the vector belongs, and the descending number within that unit under test (as shown in Table 1). The actual number of HFR test vectors is 7, which are the first test vectors numbered 0 to 6 in the table below. It should be noted that although only one vector of unit under test U5 is a high-priority HFR vector, it is still retained in the final HFR vector list and is tested first because its failure rate ranks second among all HFR vectors, not in the bottom quarter.

[0092] Table 2 Initial tuning sequence after shifting the test vector for high failure rate

[0093]

[0094] The final test sequence after executing algorithm flow S5 is shown in Table 3. This step fine-tunes the order of HFR vectors at the beginning of the sequence, attempting to group HFR test vectors belonging to the same test unit together to reduce the number of scan chain switches and further reduce test time. The test order of the subsequent non-HFR vectors grouped by test unit remains unchanged.

[0095] Table 3. Final test sequences after optimization of the reordering algorithm.

[0096]

[0097] Compared to conventional test sequences, simulation results show that: using only the test sequence optimized by this algorithm (steps S1 to S5), without the QSTAP test architecture, the expected chip test time (Lexp in Formula 1) is slightly reduced by 3.51%; if both the sequence optimized by this algorithm and the QSTAP test architecture are used simultaneously, this expected value is significantly reduced by 8.61%. For faulty chips, using the sequence optimized by this algorithm, the time required to detect the fault is reduced by 43.1% and 46.7% when the QSTAP test architecture is used, respectively. The QSTAP test architecture allows for rapid configuration of the scan path, thus saving the aforementioned Lexp time. conf Time; even without this architecture, using the IEEE-1838 standard test circuit, this solution can still save test time, but the test results are slightly less than those using QSTAP.

[0098] Through the above technical solution, this invention sorts the entire tv0 sequence in descending order, breaking the organization method of grouping by the unit under test, and generates a new test sequence tv2. Based on tv2, a list of high failure rate test vectors is generated. If a unit under test belongs to only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the high failure rate test vector list. This avoids switching the scan path twice for this single high failure rate test vector, reducing test time and greatly improving test efficiency. Furthermore, the initial tuning test sequence is constructed, with its first N... hfr The first is the high-failure-rate test vector in the tv2 sequence, which increases the test priority of high-failure-rate vectors and further improves test efficiency. Furthermore, the algorithm of this invention takes into account the scan chain configuration time and the additional equal-length test vector added after scan chain switching to serially remove the test vector from the chip's TDO pin—elements unique to 3D stacked chip testing. It is particularly suitable for testing scenarios where chip yield is not very high (not close to 100%, generally 50-80%), a small number of test vectors have significantly higher failure rates than others (not all test vectors have similar failure rates), and frequent scan path switching is required; 3D stacked chip testing meets these characteristics, therefore, this invention is suitable for application in 3D stacked chip testing.

[0099] Case 2:

[0100] In this example, the 3D packaged chip has 9 groups of test units (UTPs) from U0 to U8. The number of test vectors, the length of each test vector, and the failure rates of the top 10 test vectors within each UTP are shown in Table 4. In Formula 1, the chip yield Y is set to 60%, and the cumulative threshold Pth in Formula 3 is 0.6.

[0101] Table 4 Test vector configuration in simulation

[0102]

[0103] After executing algorithm flow I to IV, the resulting initial test sequence is shown in Table 5. The actual number of HFR test vectors is 18, which are the first test vectors numbered 0 to 17 in Table N below.

[0104] Table 5 Initial Adjustment Sequence After Moving High Failure Rate Test Vectors Forward

[0105]

[0106] The final test sequence after executing algorithm flow V is shown in Table 6. Only the order of the HFR test vectors in the initial tuning sequence is adjusted.

[0107] Table 6. Final test sequences after optimization of the reordering algorithm.

[0108]

[0109] Compared to conventional test sequences, simulation results show that using only the test sequences optimized by this algorithm (steps I-V) without the QSTAP test architecture reduces the expected chip test time by 5.69%; if both the optimized sequences and the QSTAP test architecture are used simultaneously, this expected reduction is significantly greater than 9.09%. For faulty chips, the time required to detect their fault using the optimized sequences is reduced by 49.4% and 52.1% when no QSTAP test architecture is used, respectively.

[0110] Example 2

[0111] Based on Embodiment 1, Embodiment 2 of the present invention also provides a test vector reordering system suitable for three-dimensional packaged chips, comprising:

[0112] The initialization module is used to obtain the initial test sequence tv0 and the failure rate of each test vector;

[0113] The reordering module is used to sort the initial test sequence tv0 in descending order according to the failure rate of all test vectors and generate a new test sequence tv2.

[0114] The sequence processing module is used to start from the 0th test vector of the new test sequence tv2, and accumulate the failure rates of each vector from high to low until the (k-1)th vector. If the accumulated result is greater than the accumulated threshold, then the corresponding test vector is considered a high failure rate test vector, and a list of high failure rate test vectors is generated. k is the initial value of the number of high failure rate test vectors. If a test unit has only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the list of high failure rate test vectors. Let N be the actual number of high failure rate test vectors. hfr ;

[0115] The initial test sequence generation module is used to create a new sequence tv, whose first N... hfr The test vectors are the high failure rate test vectors in the new test sequence tv2, arranged in descending order. The high failure rate test vectors are deleted from the initial test sequence tv0, and the remaining part of the initial test sequence tv0 is appended to the sequence tv to form the initial tuning test sequence. The initial tuning test sequence is used for testing.

[0116] Specifically, the initialization module is also used for:

[0117] Through formula Obtain the initial test sequence tv0;

[0118] Among them, TV i,jIt is the j-th largest test vector in the i-th unit under test, sorted in descending order of failure rate. 1,0 It is the test vector with the highest failure rate in the first unit under test; N is the number of units under test; Ltv i It is the number of test vectors contained in the i-th unit to be tested.

[0119] Specifically, starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, when the accumulated result exceeds the accumulated threshold. This includes:

[0120] Through formula Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, where P i Let P be the failure rate of the i-th test vector. th It is an accumulated threshold set to divide test vectors with high failure rates.

[0121] Specifically, the test vector reordering system suitable for three-dimensional packaged chips further includes a sequence update module, which is used for:

[0122] Step 501: Calculate the expected value of the test time corresponding to the initial test sequence;

[0123] Step 502: Use the initial test sequence as the new test sequence tv2;

[0124] Step 503: Determine whether the id-th test vector tv2[id] and the (id-1)-th test vector tv2[id-1] of the new test sequence tv2 belong to the same test unit. If yes, proceed to step 506; otherwise, execute step 504.

[0125] Step 504: tv2[id-1] belongs to the j-th unit to be tested. In the new test sequence tv2, the test vectors tv2[id+1] and tv2[N] are... hfr Between -1], find the next test vector belonging to the j-th test unit; if the test vector tv2[i] meets the condition, move tv2[i] to the position of tv2[id] so that tv2[id-1] and tv2[id] belong to the same test unit, and move the original tv2[id] to tv2[i-1] in the test sequence one position to the right;

[0126] Step 505: Calculate the expected value of the test time corresponding to the new test sequence tv2. If the expected value of its test time is lower than the expected value of the test time corresponding to the initial test sequence, then adopt the sequence generated in step 504 after the exchange order and use it as the initial test sequence. Otherwise, restore the new test sequence tv2 to the initial test sequence in step 501 before the misalignment exchange.

[0127] Step 506, id+1, return to step 503 to continue calculating the next test vector, until the Nth... hfr -1 test vectors have been calculated.

[0128] More specifically, the calculation process for the expected value of the test time is as follows:

[0129]

[0130] Q0 = 1, Q i =(1-P i-1 )Q i-1 (i = 1 ~ N) tv -1)

[0131]

[0132]

[0133] L exp = (1-Y)·L exp,fault +Y·L pass

[0134] Among them, L exp,fault L represents the expected time required to detect the fault in a group of faulty chips, representing a proportion of 1-Y. i N is the length of the i-th test vector in the test sequence. tv Q is the number of test vectors. i-1 This represents the probability that a faulty chip cannot be detected by the first i-1 test vectors. Q i It is the probability that the faulty chip cannot be detected by the first i test vectors, and it is the probability that the faulty chip cannot be detected by the first i-1 vectors (Q). i-1 ), and also through the detection of (1-P) by the i-th vector. i The conditional probability of S. i The test time (TCK cycles) required for the i-th test vector, including the time L consumed by that test vector. i and the configuration time L for scan chain switching conf , The length of the last test vector, i.e., in Li, i = N tv -1, P i-1 T represents the failure rate of the (i-1)th test vector in the test sequence.i Indicates the Tth i There are n units to be tested, and the i-th test vector belongs to the T-th unit. i One unit to be tested, L conf L pass It is the fixed testing time for a normal chip with a yield of Y, where Y is the yield.

[0135] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test vector reordering method suitable for three-dimensional packaged chips, characterized in that, Includes the following steps: Step 1: Obtain the initial test sequence tv0 and the failure rate of each test vector; Step 2: Sort the initial test sequence tv0 in descending order according to the failure rate of all test vectors, and generate a new test sequence tv2; Step 3: Starting from the 0th test vector of the new test sequence tv2, accumulate the results of each vector in descending order of failure rate until the (k-1)th vector. If the accumulated result is greater than the accumulation threshold, then the corresponding test vector is considered a high failure rate test vector, generating a list of high failure rate test vectors. k is the initial value for the number of high failure rate test vectors. If a unit under test has only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quartile of all high failure rate test vectors, this high failure rate test vector is deleted from the list of high failure rate test vectors. Let N be the actual number of high failure rate test vectors. hfr ; Step 4: Create a new sequence tv, whose first N is... hfr The test vectors are the high failure rate test vectors in the new test sequence tv2, arranged in descending order. The high failure rate test vectors are deleted from the initial test sequence tv0, and the remaining part of the initial test sequence tv0 is appended to the sequence tv to form the initial tuning test sequence. The initial tuning test sequence is used for testing.

2. The test vector reordering method for three-dimensional packaged chips according to claim 1, characterized in that, Step one includes: Through formula Obtain the initial test sequence tv0; Among them, TV i,j It is the j-th largest test vector in the i-th unit under test, sorted in descending order of failure rate. 1,0 It is the test vector with the highest failure rate in the first unit under test; N is the number of units under test; Ltv i It is the number of test vectors contained in the i-th unit to be tested.

3. The test vector reordering method for three-dimensional packaged chips according to claim 1, characterized in that, Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, including: Through formula Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, where P i Let P be the failure rate of the i-th test vector. th It is an accumulated threshold set to divide test vectors with high failure rates.

4. The test vector reordering method for three-dimensional packaged chips according to claim 1, characterized in that, It also includes step five, which includes: Step 501: Calculate the expected value of the test time corresponding to the initial test sequence; Step 502: Use the initial test sequence as the new test sequence tv2; Step 503: Determine whether the id-th test vector tv2[id] and the (id-1)-th test vector tv2[id-1] of the new test sequence tv2 belong to the same test unit. If yes, proceed to step 506; otherwise, execute step 504. Step 504: tv2[id-1] belongs to the j-th unit to be tested. In the new test sequence tv2, the test vectors tv2[id+1] and tv2[N] are... hfr Between -1], find the next test vector belonging to the j-th test unit; if the test vector tv2[i] meets the condition, move tv2[i] to the position of tv2[id] so that tv2[id-1] and tv2[id] belong to the same test unit, and move the original tv2[id] to tv2[i-1] in the test sequence one position to the right; Step 505: Calculate the expected value of the test time corresponding to the new test sequence tv2. If the expected value of its test time is lower than the expected value of the test time corresponding to the initial test sequence, then adopt the sequence generated in step 504 after the exchange order and use it as the initial test sequence. Otherwise, restore the new test sequence tv2 to the initial test sequence in step 501 before the misalignment exchange. Step 506, id+1, return to step 503 to continue calculating the next test vector, until the Nth... hfr -1 test vectors have been calculated.

5. The test vector reordering method for three-dimensional packaged chips according to claim 4, characterized in that, Expected test time L exp The calculation process is as follows: Q0=1,Q i =(1-P i-1 )Q i-1 (i=1~N tv -1) L exp <(1-Y)·L exp,fault +Y·L pass Among them, L exp,fault L represents the expected time required to detect the fault in a group of faulty chips, representing a proportion of 1-Y. i N is the length of the i-th test vector in the test sequence. tv Q is the number of test vectors. i-1 S is the probability that a faulty chip cannot be detected by the first i-1 test vectors. i The test time required for the i-th test vector. P is the length of the last test vector. i-1 T represents the failure rate of the (i-1)th test vector in the test sequence. i Indicates the Tth i There are n units to be tested, and the i-th test vector belongs to the T-th unit. i One unit to be tested, L conf L pass It is the fixed testing time for a normal chip with a yield of Y, where Y is the yield.

6. A test vector reordering system suitable for three-dimensional packaged chips, characterized in that, include: The initialization module is used to obtain the initial test sequence tv0 and the failure rate of each test vector; The reordering module is used to sort the initial test sequence tv0 in descending order according to the failure rate of all test vectors and generate a new test sequence tv2. The sequence processing module is used to start from the 0th test vector of the new test sequence tv2, and accumulate the failure rates of each vector from high to low until the (k-1)th vector. If the accumulated result is greater than the accumulated threshold, then the corresponding test vector is considered a high failure rate test vector, and a list of high failure rate test vectors is generated. k is the initial value of the number of high failure rate test vectors. If a test unit has only one high failure rate test vector, and the failure rate of this high failure rate test vector ranks in the last quarter of all high failure rate test vectors, this high failure rate test vector is deleted from the list of high failure rate test vectors. Let N be the actual number of high failure rate test vectors. hfr ; The initial test sequence generation module is used to create a new sequence tv, whose first N... hfr The test vectors are the high failure rate test vectors in the new test sequence tv2, arranged in descending order. The high failure rate test vectors are deleted from the initial test sequence tv0, and the remaining part of the initial test sequence tv0 is appended to the sequence tv to form the initial tuning test sequence. The initial tuning test sequence is used for testing.

7. A test vector reordering system suitable for three-dimensional packaged chips according to claim 6, characterized in that, The initialization module is also used for: Through formula Obtain the initial test sequence tv0; Among them, TV i,j It is the j-th largest test vector in the i-th unit under test, sorted in descending order of failure rate. 1,0 It is the test vector with the highest failure rate in the first unit under test; N is the number of units under test; Ltv i It is the number of test vectors contained in the i-th unit to be tested.

8. A test vector reordering system for three-dimensional packaged chips according to claim 6, characterized in that, Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, including: Through formula Starting from the 0th test vector of the new test sequence tv2, the results are accumulated sequentially from high to low failure rates until the (k-1)th vector, at which point the accumulated result exceeds the accumulation threshold, where P i Let P be the failure rate of the i-th test vector. th It is an accumulated threshold set to divide test vectors with high failure rates.

9. A test vector reordering system for three-dimensional packaged chips according to claim 6, characterized in that, It also includes a sequence update module, which is used for: Step 501: Calculate the expected value of the test time corresponding to the initial test sequence; Step 502: Use the initial test sequence as the new test sequence tv2; Step 503: Determine whether the id-th test vector tv2[id] and the (id-1)-th test vector tv2[id-1] of the new test sequence tv2 belong to the same test unit. If yes, proceed to step 506; otherwise, execute step 504. Step 504: tv2[id-1] belongs to the j-th unit to be tested. In the new test sequence tv2, the test vectors tv2[id+1] and tv2[N] are... hfr Between -1], find the next test vector belonging to the j-th test unit; if the test vector tv2[i] meets the condition, move tv2[i] to the position of tv2[id] so that tv2[id-1] and tv2[id] belong to the same test unit, and move the original tv2[id] to tv2[i-1] in the test sequence one position to the right; Step 505: Calculate the expected value of the test time corresponding to the new test sequence tv2. If the expected value of its test time is lower than the expected value of the test time corresponding to the initial test sequence, then adopt the sequence generated in step 504 after the exchange order and use it as the initial test sequence. Otherwise, restore the new test sequence tv2 to the initial test sequence in step 501 before the misalignment exchange. Step 506, id+1, return to step 503 to continue calculating the next test vector, until the Nth... hfr -1 test vectors have been calculated.

10. A test vector reordering system suitable for three-dimensional packaged chips according to claim 9, characterized in that, Expected test time L exp The calculation process is as follows: Q0=1,Q i =(1-P i-1 )Q i-1 (i=1~N tv -1) L exp <(1-Y)·L exp,fault +Y·L pass Among them, L exp,fault L represents the expected time required to detect the fault in a group of faulty chips, representing a proportion of 1-Y. i N is the length of the i-th test vector in the test sequence. tv Q is the number of test vectors. i-1 S is the probability that a faulty chip cannot be detected by the first i-1 test vectors. i L is the test time required for the i-th test vector. Ntv-1 P is the length of the last test vector. i-1 T represents the failure rate of the (i-1)th test vector in the test sequence. i Indicates the Tth i There are n units to be tested, and the i-th test vector belongs to the T-th unit. i One unit to be tested, L conf L pass It is the fixed testing time for a normal chip with a yield of Y, where Y is the yield.

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