Driving substrate, display panel and display device

Abstract

Embodiments of the present application provide a kind of driving substrate, display panel and display device.Driving substrate includes multiple drive units, drive unit includes N pixel electrode and 1 storage capacitor, N is positive integer, N≥2;Storage capacitor includes the reference electrode and the counter electrode of overlapping arrangement;Drive unit further includes data switch and N pixel switch, the control end of pixel switch receives the selection signal, the first end of pixel switch is coupled to the counter electrode, the second end of pixel switch is coupled to pixel electrode;Driving substrate includes data line, data line is coupled to the counter electrode by data switch.In the present application, N pixel electrode shares a storage capacitor, when the size of pixel electrode is reduced, it can still ensure that the capacitance value of storage capacitor is large enough, and it can ensure sufficient driving of electrophoretic particles when applied in electronic paper products, to avoid uneven display.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving substrate, a display panel, and a display device. Background Technology

[0002] Currently, e-paper products are widely used in the consumer market, covering areas such as smart labels, readers, and advertising signs. Most e-paper products are currently monochrome, with few color e-paper products entering mass production. Color e-paper, compared to monochrome e-paper, requires merging three or four pixels into a single main pixel; if the pixel size remains unchanged, the resolution will be severely affected. Furthermore, current driving substrate technology makes it difficult to miniaturize the size of individual pixels, thus limiting the development of color e-paper products. Summary of the Invention

[0003] This invention provides a driving substrate, a display panel, and a display device to solve the technical problem that the pixel size in current driving substrates cannot be miniaturized.

[0004] In a first aspect, embodiments of the present invention provide a driving substrate, the driving substrate including a plurality of driving units, each driving unit including N pixel electrodes and 1 storage capacitor, where N is a positive integer and N≥2; the storage capacitor includes an overlapping reference electrode and a counter electrode;

[0005] The driving unit also includes N pixel switches and data switches. The control terminal of the pixel switch receives the gating signal, the first terminal of the pixel switch is coupled to the counter electrode, and the second terminal of the pixel switch is coupled to the pixel electrode.

[0006] The driving substrate includes data lines, which are coupled to the counter electrode via a data switch.

[0007] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display panel, including the driving substrate provided in any embodiment of the present invention.

[0008] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0009] The driving substrate, display panel, and display device provided in this invention have the following advantages: Since N pixel electrodes in the driving unit share a single storage capacitor, the number of storage capacitors is reduced when the number of pixel electrodes 11 is fixed. Even when reducing the size of the pixel electrodes, there is still space to accommodate a large storage capacitor, ensuring a sufficiently large capacitance value that meets the requirements for storage capacitor values ​​in electronic paper products. The storage capacitor allows for full charging of the pixel electrodes, preventing voltage drops due to transistor switch leakage and gate-source capacitance coupling, ensuring sufficient driving of electrophoretic particles and avoiding uneven display. Furthermore, since N pixel electrodes share a storage capacitor, sufficient space can be reserved in the area of ​​each pixel electrode to accommodate a pixel switch, meeting the size requirements of the pixel switch and giving it a certain voltage withstand capability, reducing leakage current in the off state and stabilizing the voltage on the pixel electrode. The driving substrate provided in this invention, when applied to electronic paper products, enables miniaturization of pixel size, especially meeting the PPI requirements of color electronic paper products. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a partial schematic diagram of a driving substrate provided in an embodiment of the present invention;

[0012] Figure 2 A circuit diagram of a single driving unit in a driving substrate provided for an embodiment of the present invention;

[0013] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0015] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0016] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 7 A driving timing diagram provided for an embodiment of the present invention;

[0018] Figure 8Another driving timing diagram provided in an embodiment of the present invention;

[0019] Figure 9 This is a schematic diagram of another driving substrate circuit provided in an embodiment of the present invention;

[0020] Figure 10 This is a schematic diagram of another driving substrate circuit provided in an embodiment of the present invention;

[0021] Figure 11 Another driving timing diagram provided in an embodiment of the present invention;

[0022] Figure 12 Another driving timing diagram provided in an embodiment of the present invention;

[0023] Figure 13 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention;

[0024] Figure 14 for Figure 13 Circuit diagram of the driving unit;

[0025] Figure 15 for Figure 13 An enlarged schematic diagram of one of the driving units;

[0026] Figure 16 for Figure 1 A schematic diagram of a cross-section at the position of the tangent AA′;

[0027] Figure 17 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention;

[0028] Figure 18 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention;

[0029] Figure 19 for Figure 18 A schematic diagram of a cross-section at the location of the tangent line BB′;

[0030] Figure 20 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention;

[0031] Figure 21 for Figure 20 Circuit diagram at position Q in the middle region;

[0032] Figure 22 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0035] Electronic paper products have specific requirements for the storage capacitance of pixels. If the storage capacitance is too small, it will lead to insufficient retention within a single frame, resulting in inadequate driving of electrophoretic particles and uneven display. The main factor affecting the size of the storage capacitance in electronic paper products is the facing area of ​​the two plates of the storage capacitor, and the size of this facing area directly affects the pixel size. Furthermore, the high voltage required to drive the electrophoretic particles in electronic paper products necessitates that the transistors in the driving circuit have a certain aspect ratio, which is also one of the reasons why pixel miniaturization is not possible in electronic paper products.

[0036] To address the problems existing in related technologies, embodiments of the present invention provide a driving substrate in which the pixel electrodes in the driving unit share a common storage capacitor. This ensures that the capacitance value of the storage capacitor is sufficiently large while reducing the size of the pixel electrodes. When applied to electronic paper products, this guarantees sufficient driving of electrophoretic particles and avoids uneven display. Furthermore, due to the shared storage capacitor, sufficient space can be reserved in the area where each pixel electrode is located to accommodate a pixel switch, meeting the size requirements of the pixel switch. The pixel switch has a certain voltage withstand capability, reducing leakage current in the off state and stabilizing the voltage on the pixel electrode. This invention enables the miniaturization of sub-pixel sizes, meeting the PPI (Pixels Per Inch) requirements of color electronic paper products.

[0037] Figure 1 This is a partial schematic diagram of a driving substrate provided in an embodiment of the present invention. Figure 2 This is a circuit diagram of a single driving unit in a driving substrate provided in an embodiment of the present invention.

[0038] like Figure 1As shown, the driving substrate includes multiple driving units 10. Each driving unit 10 includes N pixel electrodes 11 and one storage capacitor 12, where N is a positive integer and N≥2. The N pixel electrodes 11 in the driving unit 10 share one storage capacitor 12. The storage capacitor 12 includes an overlapping reference electrode 121 and a counter electrode 122. Figure 1 The diagram uses N=3 as an example.

[0039] Combination Figure 2 The driving unit 10 also includes a data switch 14 and N pixel switches 13. The control terminal of each pixel switch 13 receives a gating signal. The gating signal is provided by the gating signal line 40. Figure 2 The diagram illustrates that the control terminals of the three pixel switches 13 are connected to the first gating signal line 40-1, the second gating signal line 40-2, and the third gating signal line 40-3, respectively. The first terminal of each pixel switch 13 is coupled to the opposite electrode 122 of the storage capacitor 12, and the second terminal is coupled to the pixel electrode 11. The reference electrode 121 of the storage capacitor 12 can be grounded. In other words, N pixel electrodes 11 are connected to the storage capacitor 12 via pixel switches 13, and the N pixel electrodes 11 in the driving unit 10 share one storage capacitor 12.

[0040] The driving substrate includes a data line 20 and a data control line 30. The data line 20 is coupled to the counter electrode 122 via a data switch 14. The control terminal of the data switch 14 is coupled to the data control line 30.

[0041] Figure 1 Both pixel switch 13 and data switch 14 are illustrated as single-gate transistors. In some embodiments, pixel switch 13 and / or data switch 14 are dual-gate transistors, which can improve the leakage current of the transistor in the off state. For example, if pixel switch 13 is a dual-gate transistor, the leakage current of pixel switch 13 in the off state is reduced, which can improve the voltage stability on the pixel electrode. In addition, the embodiments of the present invention do not limit the transistor type of pixel switch 13 and data switch 14; pixel switch 13 and data switch 14 can be either n-type transistors or p-type transistors.

[0042] In the driving substrate provided in this embodiment of the invention, the driving unit 10 includes N pixel electrodes 11. The N pixel electrodes 11 in the driving unit 10 share a single storage capacitor 12, thus reducing the number of storage capacitors 12 when the number of pixel electrodes 11 is fixed. Even with a reduced pixel electrode size, there is still space to accommodate a large storage capacitor 12, ensuring that the capacitance value of the storage capacitor 12 is sufficiently large to meet the requirements for capacitance value in electronic paper products. The storage capacitor can fully charge the pixel electrodes 11, preventing voltage drops due to transistor switch leakage and gate-source capacitance coupling, ensuring sufficient driving of electrophoretic particles and preventing uneven display. Furthermore, since the N pixel electrodes 11 share the storage capacitor 12, sufficient space can be reserved in the area where each pixel electrode 11 is located to accommodate a pixel switch 13, meeting the size requirements of the pixel switch 13. This allows the pixel switch 13 to have a certain voltage withstand capability, reducing leakage current in the off state and stabilizing the voltage on the pixel electrode 13. The driving substrate provided in this embodiment of the invention can achieve pixel miniaturization when applied in electronic paper products, especially meeting the PPI requirements of color electronic paper products.

[0043] In applications, the driving substrate can serve as the driving backplane of electronic paper products. The pixel electrode 11 on the driving substrate and the common electrode on the opposing substrate form an electric field that drives the movement of electrophoretic particles. In electronic paper products, each pixel includes a pixel electrode 11.

[0044] In some implementations, the display panel employs microcapsule-type electrophoretic display technology. Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 3 As shown, the display panel includes a driving substrate 01, an electrophoretic film 02, and a counter substrate 03. The electrophoretic film 02 includes microcapsules 021, and each microcapsule 021 contains electrophoretic particles 022 and an electrophoretic solution. The electrophoretic film 02 serves as the display medium between the driving substrate 01 and the counter substrate 03. The counter substrate 03 also includes a common electrode 031, which overlaps with the pixel electrode 11 along the thickness direction e of the display panel. Figure 3 The structure of the driving substrate 01 is only simplified in the diagram. The driving substrate 01, electrophoretic membrane 02, and opposing substrate 03 are fabricated separately. Adhesive layers are used to bond the driving substrate 01 to the electrophoretic membrane 02, and also to the electrophoretic membrane 02 and opposing substrate 03. Alternatively, the electrophoretic membrane 02 can be fabricated on the opposing substrate 03, and then the electrophoretic membrane 02 and the opposing substrate 03 can be bonded together as a single unit to the driving substrate 01. The common electrode 031 on the opposing substrate 03 can be electrically connected to the driving substrate 01, allowing the driving substrate 01 to provide a driving voltage to the common electrode 031.

[0045] In other embodiments, the display panel employs microcup electrophoretic display technology. Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 4 As shown, the display panel includes a driving substrate 01, an electrophoretic film 02, and an opposing substrate 03. The electrophoretic film 02 includes a plurality of microcuplets 023, and electrophoretic particles 022 and electrophoretic liquid are disposed in the microcuplets 023. The electrophoretic film 02 is a display medium between the driving substrate 01 and the opposing substrate 03. Figure 4 The diagram illustrates the common electrode 031 on the opposing substrate 03 and the pixel electrode 11 on the driving substrate 01. In this embodiment, the electrophoretic film 02 can be fabricated separately and then bonded to the driving substrate 01 and the opposing substrate 03 respectively using an adhesive layer; alternatively, the electrophoretic film 02 can be fabricated on the opposing substrate 03, and then the electrophoretic film 02 and the opposing substrate 03 can be bonded together as a whole to the driving substrate 01. The common electrode 031 on the opposing substrate 03 can be electrically connected to the driving substrate 01, thereby allowing the driving substrate 01 to provide a driving voltage to the common electrode 031.

[0046] In other embodiments, the display panel employs a dam-type electrophoretic display technology. Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 As shown, the display panel includes a driving substrate 01 and a counter substrate 03. After multiple driving units are fabricated on the driving substrate 01, multiple dike structures 024 are fabricated on top of the driving units. The dike structures 024 surround the area where the pixels are located, and the dike structures 024 are essentially multiple micropits. Electrophoretic particles 022 and electrophoretic liquid are filled into the dike structures 024, and then encapsulated. The dike structures 024, electrophoretic particles 022, and electrophoretic liquid constitute the display medium layer 04 between the driving substrate 01 and the counter substrate 03. Figure 5 The diagram illustrates the substrate 00, pixel switch 13, and pixel electrode 11. The pixel switch 13 includes a gate g, an active layer w, a source s, and a drain d, and the pixel electrode 11 is electrically connected to the drain d. Figure 5 The pixel switch 13 is shown as a bottom-gate transistor, but it can also be a top-gate transistor. Along the thickness direction e of the display panel, the common electrode 031 on the opposing substrate 03 and the pixel electrode 11 on the driving substrate 01 overlap.

[0047] In some implementations, microcapsule-based electrophoretic display technology is used as an example. Figure 6 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 6As shown, the opposing substrate 03 further includes a color resist layer, which comprises at least three different color resist units 032; along the thickness direction e of the display panel, the color resist units 032 overlap with the pixel electrodes 11. This embodiment can achieve color display. Optionally, the N color resist units overlapping the N pixel electrodes 11 in the driving unit may have different colors.

[0048] The driving substrate provided in this embodiment of the invention is used to drive a display panel for display. The display of one image includes N refresh cycles, and N pixel electrodes 11 write data voltages in each of the N refresh cycles. Specifically, in one refresh cycle: data switch 14 is open, data line 20 is connected to the opposing electrode 122, pixel switch 13 is open, pixel electrode 11 is connected to the opposing electrode 122, and data line 20 writes data voltages to the pixel electrode 11 and stores them on the storage capacitor 12. During the period when pixel switch 13 is open, the storage capacitor 12 can be used to maintain the voltage on the pixel electrode 11. Since the capacitance value of the storage capacitor 12 is large enough, it can fully charge the pixel electrode 11, avoiding voltage drops in the pixel electrode 11 due to leakage and gate-source capacitance coupling, thus ensuring sufficient driving of electrophoretic particles. For one driving unit 10, the process of writing data voltages to one pixel electrode 11 is realized by controlling the opening of data switch 14 and pixel switch 13 in one refresh cycle. Then, N refresh cycles cause the N pixel electrodes 11 in the driving unit 10 to write data voltage respectively, and all N pixel electrodes 11 participate in the display. The driving substrate completes the display of a complete picture after N refresh cycles.

[0049] In some implementations, the data voltage range is [-15V, 15V].

[0050] In one embodiment, taking N=3 as an example, combined with Figure 6 To illustrate this embodiment, a driving substrate is applied to a display panel. A driving unit 10 includes three pixel electrodes 11, each overlapping with a color resist unit 032. When the colors of the three overlapping color resist units 032 in the driving unit are different—for example, the three pixel electrodes 11 overlap with red, green, and blue color resist units 032 respectively—each pixel in the display panel includes a color resist unit 032, a pixel electrode 11, and a pixel switch 13. Therefore, a red pixel in the display panel includes a red color resist unit and its overlapping pixel electrode 11; a green pixel includes a green color resist unit and its overlapping pixel electrode 11; and a blue pixel includes a blue color resist unit and its overlapping pixel electrode 11. The display panel can display an image in the following manner.

[0051] The display panel displays an image in three refresh cycles, driving red, green, and blue color pixels to display in each of the three refresh cycles.

[0052] Figure 7 This is a driving timing diagram provided as an embodiment of the present invention. Combined with... Figure 2 The schematic diagram of the drive unit circuit is used for explanation. Figure 7 In the diagram, 30 represents the signal timing of a data control line 30 in the driving substrate. In one embodiment, the pixel switch 13 connected to the first gating signal line 40-1 belongs to the red pixel, the pixel switch 13 connected to the second gating signal line 40-2 belongs to the green pixel, and the pixel switch 13 connected to the third gating signal line 40-3 belongs to the blue pixel. The data control line 30 controls the data switch 14, and the data control line 30 provides an enable signal to control the data switch 14 to open. Figure 7 As shown:

[0053] In the first refresh cycle T1, pixel switch 13 in the red pixel is turned on, pixel electrode 11 and the opposing electrode 122 are connected, data switch 14 is turned on, and data line 20 and the opposing electrode 122 are connected. Data line 20 writes the data voltage corresponding to the red pixel to pixel electrode 11. During the period when pixel switch 13 is on, storage capacitor 12 maintains the voltage on pixel electrode 11 stable, preventing the voltage on pixel electrode 11 from dropping. An electric field is formed between pixel electrode 11 and common electrode 031 in the red pixel to control the electrophoretic particles to move to the required position, realizing the grayscale display of the red pixel. Due to the bistable characteristics of the electrophoretic particles, when pixel switch 13 is turned off, the electrophoretic particles will remain in the current position and will not move, so the red pixel maintains its display state. In this refresh cycle, all driving units 10 work to charge the pixel electrodes 11 of all red pixels, so all red pixels display the grayscale they need to display. And after the first refresh cycle ends, the red pixels maintain their display state.

[0054] In the second refresh cycle T2, pixel switch 13 in the green pixel is turned on, pixel electrode 11 and the opposing electrode 122 are connected, data switch 14 is turned on, and data line 20 and the opposing electrode 122 are connected. Data line 20 writes the data voltage corresponding to the green pixel to pixel electrode 11. During the period when pixel switch 13 is on, storage capacitor 12 maintains the voltage on pixel electrode 11 stable. An electric field is formed between pixel electrode 11 and common electrode 031 in the green pixel to control the electrophoretic particles to move to the required position, realizing the grayscale display of the green pixel. After pixel switch 13 is turned off, the green pixel maintains its display state. In this refresh cycle, all driving units 10 work to charge the pixel electrodes 11 of all green pixels, so all green pixels display the grayscale they need to display. After the second refresh cycle ends, the green pixels maintain the display state, and the red pixels maintain the display state during and after the second refresh cycle.

[0055] In the third refresh cycle T3, pixel switch 13 in the blue pixel is turned on, pixel electrode 11 and the opposing electrode 122 are connected, data switch 14 is turned on, and data line 20 and the opposing electrode 122 are connected. Data line 20 writes the data voltage corresponding to the blue pixel to pixel electrode 11. During the period when pixel switch 13 is on, storage capacitor 12 maintains the voltage on pixel electrode 11 stable. An electric field is formed between pixel electrode 11 and common electrode 031 in the blue pixel to control the electrophoretic particles to move to the required position, realizing the grayscale display of the blue pixel. After pixel switch 13 is turned off, the blue pixel maintains its display state. In this refresh cycle, all driving units 10 work to charge the pixel electrodes 11 of all blue pixels, so all blue pixels display the grayscale they need to display. In the third refresh cycle, both green and red pixels maintain their display state. After the third refresh cycle is completed, red, green, and blue pixels in the display panel all maintain their display state. The three color pixels work together to display a single image.

[0056] Figure 7 The description only uses the example of red pixels being displayed in the first refresh cycle, green pixels in the second refresh cycle, and blue pixels in the third refresh cycle. This embodiment of the invention does not limit the sequential driving and display order of the red, green, and blue pixels in the three refresh cycles.

[0057] In this embodiment of the invention, N pixel electrodes 11 within the driving unit 10 share a single storage capacitor 12, combined with Figure 7 As the timing diagram illustrates, in each refresh cycle, data switch 14 is turned on once and pixel switch 13 is turned on once. This allows data voltage to be written to pixel electrode 11 via data line 20, and storage capacitor 12 is used to maintain voltage stability on pixel electrode 11, ensuring sufficient charging of pixel electrode 11. In a display panel, after pixel electrode 11 is charged, it forms an electric field with the common electrode to drive the movement of electrophoretic particles, controlling the particles to move to the required position for grayscale display. When pixel switch 13 connected to pixel electrode 11 is turned off, the electrophoretic particles remain in their original positions, and the corresponding pixel displays a unchanged grayscale. However, in some implementations, after pixel switch 13 is turned off, residual charge may remain on pixel electrode 11. This residual charge may form an electric field with the common electrode (because pixels in the display panel share a common electrode, and a voltage signal is continuously present on the common electrode during display). This can cause the electrophoretic particles within the pixel, which should remain in their original positions, to shift, resulting in chaotic particle movement and abnormal pixel display.

[0058] To avoid chaotic movement of electrophoretic particles within pixels when displaying an image, embodiments of the present invention further improve the driving timing by adding a reset phase to the refresh cycle. In some implementations, Figure 8 This is another driving timing diagram provided for an embodiment of the present invention. (In conjunction with...) Figure 2 Understand the schematic diagram of the driving unit circuit. Taking N=3 as an example, as... Figure 8 As shown, each refresh cycle includes a data writing phase t-1 and a reset phase t-2. In the data writing phase t-1, the data control line 30 provides an enable signal to control the data switch 14 to turn on, and the data line 20 writes the data voltage to the pixel electrode 11. In the reset phase t-2, the data control line 30 provides an enable signal to control the data switch 14 to turn on, and the data line 20 writes the reset voltage to the pixel electrode 11. In each refresh cycle, the reset phase t-2 is executed after the data writing phase t-1. In this embodiment, a reset phase t-2 is set in the refresh cycle, and the pixel electrode 11 is reset using a reset voltage to ensure that there is no voltage difference between the pixel electrode 11 and the common electrode after the refresh cycle ends and the pixel switch 13 is turned off. This ensures that the electrophoretic particles in the pixel can remain at the position they moved to when the pixel electrode 11 was energized, thereby ensuring that the grayscale of the pixel display remains unchanged and avoiding chaotic movement of electrophoretic particles, which could lead to abnormal pixel display.

[0059] In some implementations, the reset voltage is equal to the voltage value of the common voltage set in the display panel, and the reset voltage is 0V.

[0060] In some implementations, such as Figure 1 As shown, the driving substrate includes a data control line 30. The control terminal of the data switch 14 is coupled to the data control line 30. The first terminal of the data switch 14 is coupled to the data line 20, and the second terminal of the data switch 14 is coupled to the counter electrode 122. Multiple driving units 10 are arranged in a row 10H along a first direction x, and multiple driving units 10 are arranged in a column 10L along a second direction y. The first direction x and the second direction y intersect; optionally, the first direction x and the second direction y are perpendicular to each other. One data control line 30 is coupled to multiple data switches 14 in a row 10H; one data line 20 is coupled to multiple data switches 14 in a column 10L. In this embodiment, one data control line 30 controls multiple data switches 14 in a row 10H, and the data control line 30 is essentially a row gate line. One data line 20 provides data voltage to multiple driving units 10 in a column 10L. Multiple data control lines 30 and multiple data lines 20 work together to drive multiple cell rows 10H line by line, completing one refresh cycle.

[0061] In some implementations... Figure 9Another schematic diagram of a driving substrate circuit provided in an embodiment of the present invention is shown below. Figure 9 As shown, the driving substrate includes a gate line group 40Z, which includes N gate signal lines 40. The control terminals of the N pixel switches 13 in the driving unit are respectively connected to the N gate signal lines 40. Figure 9 Taking N=3 as an example, multiple driving units 10 are arranged in a unit row 10H along a first direction x; multiple driving units 10 in a unit row 10H share a single gate line group 40Z. The gate line group 40Z includes a first gate signal line 40-1, a second gate signal line 40-2, and a third gate signal line 40-3. When N=3, each driving unit 10 includes three pixel switches 13, and the control terminals of the three pixel switches 13 are respectively connected to the three gate lines 40 in the gate line group 40Z. Driving a unit row 10H with a single gate line group 40Z simplifies the driving method of the unit row 10H and simplifies the wiring in the driving substrate.

[0062] like Figure 9 As shown, the driving substrate includes multiple cell rows 10H and multiple data control lines 30, which are arranged along the second direction y. Figure 9 The diagram illustrates three cell rows 10H, and corresponding to the first data control line 30-1, the second data control line 30-2, and the third data control line 30-3, respectively. The data control lines 30 are connected to the row driving structure 60, which controls the provision of enable signals to the multiple data control lines 30 row by row within a refresh cycle. The row driving structure 60 can be, for example, a shift driving circuit fabricated on a driving substrate, or a driving chip fixed on the driving substrate. The data line 20 is electrically connected to the data driving structure 50, which can be a driving chip or a flexible circuit board bonded to the driving substrate.

[0063] In one refresh cycle: multiple data control lines 30 sequentially output enable signals, and multiple data switches 14 coupled to one data control line 30 simultaneously open under the control of the enable signals. The process of driving multiple cell rows 10H line-by-line using multiple data control lines 30 is completed within one refresh cycle. Combined with... Figure 2 and Figure 7 As illustrated in the embodiment, for a driving unit 10, data voltage is written to a pixel electrode 11 after the data switch 14 is turned on once in one refresh cycle. The process of writing data voltage to N pixel electrodes 11 in the driving unit 10 is completed over N refresh cycles.

[0064] In some embodiments, the N gate signal lines 40 in the gate line group 40Z are the first gate signal line 40-1, the second gate signal line 40-2, and so on up to the Nth gate signal line 40-N; the driving substrate includes multiple gate line groups 40Z, wherein multiple i-th gate signal lines 40-i in the multiple gate line groups 40Z are electrically connected to each other, where i is a positive integer, 1≤i≤N.

[0065] Figure 10 Another schematic diagram of a driving substrate circuit provided in an embodiment of the present invention is shown below. Figure 10 As shown, N=3, and the gate line group 40Z includes a first gate signal line 40-1, a second gate signal line 40-2, and a third gate signal line 40-3. Multiple first gate signal lines 40-1, multiple second gate signal lines 40-2, and multiple third gate signal lines 40-3 in the multiple gate line groups 40Z are electrically connected to each other. In one refresh cycle, multiple gate line groups 40Z can share the same gate signal, reducing the number of gate signals required on the driving substrate, thereby reducing the number of pins on the driving chip and helping to reduce costs.

[0066] In some implementations, N gating signal lines 40 provide enable signals in N refresh cycles; the refresh cycle duration is t, and the duration for each enable signal provided by the gating signal line 40 is t. Within one refresh cycle, multiple data control lines 30 provide enable signals row by row, and the on-time of a data switch 14 is much shorter than the refresh cycle duration t. Since the on-time of the pixel switch 13 controlled by the gating signal line 40 is equal to the refresh cycle duration t, after the data switch 14 is turned off within one refresh cycle, the pixel electrode 11 remains electrically connected to the storage capacitor 12. The storage capacitor 12 maintains the voltage on the pixel electrode 11 to ensure that the pixel electrode 11 is fully charged. When the driving substrate is applied to electronic paper products, fully charging the pixel electrode 11 ensures sufficient driving of the electrophoretic particles, avoiding uneven display.

[0067] Figure 11 This is another driving timing diagram provided for an embodiment of the present invention. When N=3, the display of one screen includes three refresh cycles T1, T2, and T3. Combined with... Figure 10To understand the driving method of the driving substrate during the refresh cycle, the enable signal provided by the strobe signal line 40 is for a duration equal to the refresh cycle duration. Taking the first refresh cycle T1 as an example: In the first refresh cycle T1: the first strobe signal line 40-1 provides an enable signal to control the pixel switch 13 connected to it to turn on, and the duration of the enable signal provided by the first strobe signal line 40-1 is equal to the duration of the first refresh cycle T1; multiple data control lines 30 provide enable signals row by row, and one data control line 30 controls multiple data switches 14 in a unit row 10H to turn on simultaneously. Since multiple strobe line groups 40Z share the strobe signal, the pixel switches 13 connected to the first strobe signal line 40-1 in each unit row 10H are all continuously in the on state. When the data switch 14 is on, the data voltage is written to the pixel electrode 11 using the data line 20, and after the data switch 14 is turned off, the voltage on the pixel electrode 11 is maintained using the storage capacitor 12. During the period when the first strobe signal line 40-1 provides an enable signal, multiple data control lines 30 provide enable signals row by row, and data voltages are written row by row to the pixel electrodes 11 in multiple unit rows 10H using data lines 20. For a driving unit 10, only one pixel switch 13 is turned on in one refresh cycle. After the data switch 14 is turned off, the storage capacitor 12 can still be electrically connected to the pixel electrode 11, using the storage capacitor 12 to maintain the voltage on the pixel electrode 11, so as to ensure that the pixel electrode 11 is fully charged.

[0068] In this embodiment of the invention, the refresh cycle includes a data writing phase. During the data writing phase, the data switch 14 is turned on, and the data line 20 writes data voltage to the pixel electrode 11. The enable signal provided by the strobe signal line 40 covers the data writing phase. The data writing phase is also the phase in a refresh cycle where multiple data control lines 40 provide enable signals line by line. The duration of one enable signal provided by the strobe signal line 40 is equal to the duration of one refresh cycle. Figure 11 The diagram only illustrates that during one refresh cycle, three strobe signal lines sequentially provide enable signals, which are... Figure 11 It can be seen that during a refresh cycle, the enable signal period provided by the strobe signal line 40 covers the data writing stage, thereby enabling multiple cell rows 10H to share the strobe signal. During the enable signal period provided by the strobe signal line 40 in a refresh cycle, the data writing process of multiple cell rows 10H is completed.

[0069] In some implementations... Figure 12 This is another driving timing diagram provided in an embodiment of the present invention. Taking N= as an example, Figure 10 The provided driver board can be used Figure 12 The driving sequence is illustrated. For example... Figure 12As shown, the display of one frame includes three refresh cycles: the first refresh cycle T1, the second refresh cycle T2, and the third refresh cycle T3. Each refresh cycle includes a data writing phase t-1 and a reset phase t-2. In the data writing phase t-1, multiple data control lines 30 sequentially output enable signals, and data lines 20 write data voltages to the pixel electrodes 11. In the reset phase t-2, multiple data control lines 30 simultaneously output enable signals, wherein the data switch 14 is turned on, and data lines 20 write reset voltages to the pixel electrodes 11. Figure 12 The diagram illustrates that during the data writing phase t-1, the first data control line 30-1, the second data control line 30-2, and the third data control line 30-3 sequentially output enable signals. During the reset phase t-2, the first data control line 30-1, the second data control line 30-2, and the third data control line 30-3 simultaneously output enable signals. In this embodiment, a reset phase t-2 is set within the refresh cycle. After the data writing phase t-1 is completed, a reset voltage is used to reset the pixel electrode 11. This ensures that after the refresh cycle ends and the pixel switch 13 is turned off, there is no voltage difference between the pixel electrode 11 and the common electrode. Therefore, the electrophoretic particles within the pixel can remain stationary at the positions they moved to when the pixel electrode 11 was energized. This ensures that the grayscale of the pixel display remains unchanged and prevents chaotic movement of the electrophoretic particles, which could lead to abnormal pixel display. Furthermore, by setting multiple data control lines 30 to simultaneously output enable signals during the reset phase t-2, which means that the pixel electrodes 11 in multiple unit rows 10H are reset simultaneously within the refresh cycle, the duration of the reset phase t-2 within the refresh cycle is relatively small. Therefore, increasing the reset phase t-2 has a smaller impact on the refresh cycle, thereby reducing the impact on the display refresh rate.

[0070] Additionally, during the refresh cycle, the enable signal line 40 provides an enable signal for a period covering the data write phase t-1 and the reset phase t-2. For example... Figure 12 In the first refresh cycle T1, the first strobe signal line 40-1 provides an enable signal. The period during which the first strobe signal line 40-1 provides the enable signal covers the data writing phase t-1 and the reset phase t-2. This allows multiple cell rows 10H to share the same strobe signal. Within one refresh cycle, the data writing process for multiple cell rows 10H and the reset process for the pixel electrode 11 are completed during the period when the strobe signal line 40-1 provides the enable signal. In application, after the pixel electrode 11 is written with the data voltage, it forms an electric field with the common electrode to control the electrophoretic particles in the pixel to move to a fixed position. Then, the pixel electrode 11 is reset using a reset voltage. When the reset voltage is equal to the voltage of the common electrode, the position of the electrophoretic particles in the pixel remains fixed. This avoids the electrophoretic particles moving erratically after the refresh cycle ends, preventing abnormal pixel display.

[0071] In some implementations, with Figure 1 For example, Figure 1 The diagram shows a top view of the drive substrate, which can be understood as being parallel to the thickness direction of the drive substrate. Figure 1 The schematic driving unit 10 includes three pixel electrodes 11 and a storage capacitor 12. Along the thickness direction of the driving substrate, a pixel switch 13 coupled to the pixel electrodes 11 overlaps with the pixel electrodes 11, and the storage capacitor 12 partially overlaps with each of the three pixel electrodes 11. In electronic paper products, the pixel electrodes 11 need to be opposite to a common electrode to form an electric field, so the pixel electrodes 11 need to be arranged in-plane in the driving substrate. By partially overlapping the storage capacitor 12 with each of the N pixel electrodes 11, the storage capacitor 12 is placed within the space of the N pixel electrodes 11, allowing for a larger space for the storage capacitor 12, thus ensuring the capacitance value required by the electronic paper product. Furthermore, placing the pixel switch 13 overlapping with the pixel electrodes 11 within the same area also meets the size requirements of the pixel switch 13 in electronic paper products, giving the pixel switch 13 a certain voltage withstand capability, reducing leakage current in the off state, and stabilizing the voltage on the pixel electrodes 13.

[0072] In some embodiments, N pixel electrodes 11 in the driving unit 10 are arranged along a first direction x, and the electrodes of the storage capacitor 12 extend along the first direction x. Taking N=3 as an example... Figure 1 As shown, the three pixel electrodes 11 in the driving unit 10 are arranged along the first direction x, and the reference electrode 121 and the counter electrode 122 of the storage capacitor 12 both extend along the first direction x. This allows the electrodes of the storage capacitor 12 to have a large length in the first direction x, which is beneficial to increase the electrode area of ​​the storage capacitor 12, increase the capacitance value of the storage capacitor 12, and meet the requirements for the capacitance value of the storage capacitor 12.

[0073] like Figure 1 As shown, the driving substrate is provided with a gating signal line 40, a data control line 30, and a data line 20. The gating signal line 40 and the data control line 30 extend along a first direction x, and the data line 20 extends along a second direction y. The data line 20 and the data control line 30 intersect to define the area where the driving unit 10 is located. A portion of the gating signal line 40 is multiplexed as the gate of the pixel switch 13. The pixel switch 13 overlaps with the pixel electrode 11, so the gating signal line 40 partially overlaps with the pixel electrode 11. Figure 1 The image also shows that the pixel switch 13 is connected to the first via V1 of the pixel electrode 11.

[0074] In another embodiment, Figure 13 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention. Figure 14 for Figure 13 A circuit diagram of the driving unit. Figure 13 The diagram illustrates the four drive units 10 in the drive substrate, such as... Figure 13 As shown, N=4, and the four pixel electrodes 11 in the driving unit 10 are arranged in a 2x2 configuration. The driving substrate contains a gating signal line 40 and a data control line 30 extending along a first direction x, and a data line 20 extending along a second direction y. The four pixel electrodes 11 in the driving unit 10 are connected to the storage capacitor 12 via pixel switches 13, and the data line 20 is connected to the storage capacitor 12 via a data switch 14. The pixel switches 13 are controlled by the gating signal line 40. In the driving substrate, multiple driving units 10 are arranged in a row 10H along the first direction x, and multiple driving units 10 are arranged in a column 10L along the second direction y.

[0075] When N=4, a cell row 10H requires four gating signal lines 40 to drive it, and these four gating signal lines 40 form a gating line group 40Z. Combined with... Figure 14 As can be seen, the control terminals of the four pixel switches 13 in the driving unit 10 are respectively connected to the first gating signal line 40-1, the second gating signal line 40-2, the third gating signal line 40-3 and the fourth gating signal line 40-4 in the gating line group 40Z.

[0076] In this embodiment, the display of an image includes four refresh cycles, during which the four pixel electrodes 11 write data voltages. Specifically, in one refresh cycle: the data switch 14 is open, the data line 20 is connected to the opposing electrode 122, the pixel switch 13 is open, and the pixel electrode 11 is connected to the opposing electrode 122. The data line 20 writes data voltages to the pixel electrode 11. While the pixel switch 13 remains open, the storage capacitor 12 maintains the voltage on the pixel electrode 11. In the four refresh cycles, the four pixel electrodes 11 in the driving unit 10 write data voltages respectively, and all four pixel electrodes 11 participate in the display. The driving substrate completes the display of a complete image after four refresh cycles.

[0077] Optional, Figure 13 In this embodiment, multiple gating line groups 40Z share a gating signal, that is, multiple i-th gating signal lines 40-i in multiple gating line groups 40Z are electrically connected to each other, where i is a positive integer, 1≤i≤N. Figure 11 The driving method in the timing diagram can be applied to Figure 13The driving substrate provided in this embodiment displays an image in four refresh cycles. For example, in the first refresh cycle, the first gating signal line 40-1 provides an enable signal to control the pixel switch 13 connected to it to turn on. The duration of the enable signal provided by the first gating signal line 40-1 is equal to the duration of the first refresh cycle. Since multiple gating line groups 40Z share the gating signal, the pixel switches 13 connected to the first gating signal line 40-1 in each unit row 10H are all continuously in the on state. When the first gating signal line 40-1 provides the enable signal, multiple data control lines 30 provide enable signals row by row. One data control line 30 controls multiple data switches 14 in one unit row 10H to turn on simultaneously. When the data switch 14 is on, data voltage is written to the pixel electrode 11 using data line 20, and after the data switch 14 is turned off, the voltage on the pixel electrode 11 is maintained using storage capacitor 12. During the period when the first strobe signal line 40-1 provides an enable signal, multiple data control lines 30 provide enable signals row by row, and data voltages are written row by row to the pixel electrodes 11 in multiple unit rows 10H using data lines 20. In this way, data voltages are written to the four pixel electrodes 11 in multiple driving units 10 in the entire driving substrate after four refresh cycles.

[0078] During the period when the strobe signal line provides an enable signal, the process of multiple data control lines 30 sequentially providing enable signals to write data voltage to cell row 10H is called the data writing phase.

[0079] Figure 12 The driving method in the timing diagram can also be applied to Figure 13 The driving substrate provided in this embodiment includes a data writing phase and a reset phase in one refresh cycle. During the reset phase, multiple data control lines 30 simultaneously output enable signals to reset the pixel electrode 11. This can be combined with... Figure 1 and Figure 12 The relevant descriptions of the embodiments are for reference only and will not be repeated here.

[0080] In one embodiment, the display panel includes Figure 13The driving substrate provided in this embodiment includes a display panel with pixels comprising red, green, blue, and white pixels, each containing electrophoretic particles. One red pixel, one green pixel, one blue pixel, and one white pixel constitute a display unit, and one display unit corresponds to one driving unit 10 on the driving substrate. Specifically, a pixel electrode 11, in conjunction with a common electrode, drives the electrophoretic particles in the pixel to move, thereby achieving pixel display. In this embodiment, the process of the display panel displaying an image includes four refresh cycles. For example, in the first refresh cycle, data voltage is written to the pixel electrode 11 corresponding to the red pixel to drive the red pixel to display; in the second refresh cycle, data voltage is written to the pixel electrode 11 corresponding to the green pixel to drive the green pixel to display; in the third refresh cycle, data voltage is written to the pixel electrode 11 corresponding to the blue pixel to drive the blue pixel to display; and in the fourth refresh cycle, data voltage is written to the pixel electrode 11 corresponding to the white pixel to drive the white pixel to display. After completing four refresh cycles, an image is displayed. This embodiment of the invention does not limit the refresh display order of different color pixels in the four refresh cycles.

[0081] In some embodiments, the pixels of the display panel include red pixels, green pixels, blue pixels, and white pixels, and the pixels include electrophoretic particles. The driving substrate in the display panel includes multiple driving units 10, each driving unit 10 including four pixel electrodes 11 and one storage capacitor, wherein the four pixel electrodes 11 in the driving unit 10 are arranged in the same direction. One red pixel, one green pixel, one blue pixel, and one white pixel constitute a display unit, and one display unit corresponds to one driving unit 10 in the driving substrate. In this embodiment, the process of the display panel displaying an image includes four refresh cycles.

[0082] Figure 15 for Figure 13 An enlarged schematic diagram of a driving unit, as shown below. Figure 15 As shown, in a driving unit 10, four pixel electrodes 11 are arranged in a first electrode row 11H-1 and a second electrode row 11H-2 along a first direction x. The ends of the two pixel electrodes 11 in the first electrode row 11H-1 closest to the ends of the second electrode row 11H-2 are called the first ends. Figure 15 (Not shown in the image), the ends of the two pixel electrodes 11 in the second electrode row 11H-2 closest to the ends of the first electrode row 11H-1 are the second ends ( Figure 15(Not shown in the image). The storage capacitor 12 and the first ends of the two pixel electrodes 11, and the second ends of the two pixel electrodes 11 overlap, that is, the storage capacitor 12 and the four pixel electrodes 11 form an array region that overlaps in the middle region. The driving substrate includes a gating signal line 40 extending along the first direction x. The control terminal of the pixel switch 13 is coupled to the gating signal line 40, and the driving unit 10 is correspondingly connected to the four gating signal lines 40. In the second direction y, two of the four gating signal lines 40 are located on one side of the storage capacitor 12, and the other two are located on the other side of the storage capacitor 12. The second direction y intersects the first direction x. The control terminal of the data switch 14 is coupled to the data control line 30, which extends along the first direction x. In the second direction y, the data control line 30 is located on one side of the storage capacitor 12.

[0083] Figure 15 In this embodiment, when N=4, the four pixel electrodes 11 in the driving unit 10 are arranged in a 2x2 row and 2x2 column configuration. The storage capacitor 12 is positioned in the middle of the area where the four pixel electrodes 11 are arranged, resulting in partial overlap between the storage capacitor 12 and each of the four pixel electrodes 11. Placing a storage capacitor 12 within the area of ​​the four pixel electrodes 11 ensures that its capacitance is sufficiently large, meeting the capacitance requirements for electronic paper products. This allows for adequate charging of the pixel electrodes 11, ensuring sufficient driving of the electrophoretic particles and preventing uneven display. Furthermore, the four selection signal lines 40 are positioned in pairs on either side of the storage capacitor 12, facilitating electrical connection between the selection signal lines 40 and the pixel switch 13. The data control line 30 is positioned on one side of the storage capacitor 12, facilitating electrical connection between the data control line 30 and the data switch 14.

[0084] In some implementations... Figure 16 for Figure 1 A schematic diagram of a cross-section at the position of the midtangent AA′, as shown below. Figure 16 As shown, the driving substrate includes a substrate 00, and a first metal layer 001, a second metal layer 022, and a transparent conductive layer 003 disposed sequentially away from the substrate 00. At least a portion of the select signal line 40, at least a portion of the data control line 30, and the reference electrode 121 are located in the first metal layer 001; the data line 20 and the counter electrode 122 are located in the second metal layer 002; and the pixel electrode 11 is located in the transparent conductive layer 003. Optionally, the material of the first metal layer 001 includes molybdenum, the material of the second metal layer 002 includes titanium and aluminum, and the material of the transparent conductive layer 003 includes indium tin oxide. Figure 16 As shown, the driving substrate also includes a semiconductor layer 004, the material of which comprises silicon. The semiconductor layer 004 is used to form the active layer of the switching transistor. Figure 16 The active layers of pixel switch 13 and data switch 14 are located on semiconductor layer 004. Figure 16 The diagram illustrates pixel switch 13 and data switch 14 as bottom-gate transistors. In other embodiments, pixel switch 13 and data switch 14 are top-gate transistors.

[0085] The active layer of the transistor of the present invention may include at least one of amorphous silicon, low-temperature polycrystalline silicon and oxide semiconductor, and the transistor here may include pixel switch 13 and data switch 14. Figure 16 The diagram illustrates the structure of a transistor fabricated using amorphous silicon technology.

[0086] Figure 16 The diagram also illustrates the first via V1, through which the pixel electrode 11 is electrically connected to the second end of the pixel switch 13.

[0087] In addition, a planarization layer 005 is provided between the transparent conductive layer 003 and the second metal layer 002. The planarization layer 005 has a planarization function, which can provide a flat substrate for the transparent conductive layer 003 and ensure the flatness of the pixel electrode 11.

[0088] In some implementations, a portion of at least one strobe signal line 40 is located in the second metal layer 002. Figure 17 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention. Figure 17 Only the area containing one driving unit 10 on the driving substrate is shown, illustrated with N=3. For example... Figure 17 The driving unit 10 shown has three pixel electrodes 11 arranged along a first direction x. The driving substrate includes a first gating signal line 40a extending along the first direction x and a second gating signal line 40b extending along a second direction y. The first gating signal line 40a is located in the first metal layer 01. The second gating signal line 40b includes a first segment 40b-1 and a second segment 40b-2. The first segment 40b-1 is located in the first metal layer 001, and the second segment 40b-2 is located in the second metal layer 002. The second segment 40b-2 and the first segment 40b-1 are electrically connected through a second via V2. A portion of the first segment 40b-1 is multiplexed as the gate of the pixel switch 13. The data line 20 is located in the second metal layer 002, the data control line 30 is located in the first metal layer 001, and the pixel electrode 11 is located in the transparent conductive layer 003. The sheet resistance of the second metal layer 002 is less than that of the first metal layer 001. By placing the second segment 40b-2 of the second gating signal line 40b in the second metal layer 002, the overall resistance of the second gating signal line 40b can be reduced, thereby reducing the voltage drop of the signal transmitted on the second gating signal line 40b, which is beneficial to improving the uniformity of the in-plane signal.

[0089] In other embodiments, at least one data control line 30 includes a third segment and a fourth segment, the third segment being located in the first metal layer 001 and the fourth segment being located in the second metal layer 002. The third and fourth segments are electrically connected through a via penetrating the insulating layer, and a portion of the third segment is multiplexed as the gate of the data switch 14. This embodiment can reduce the overall resistance of the data control line 30, thereby reducing the voltage drop of the transmitted signal on the data control line 30, which is beneficial for improving in-plane signal uniformity.

[0090] In other implementations, Figure 18 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention. Figure 19 for Figure 18 A schematic diagram of a cross-section at the location of the tangent line BB′. Figure 18 The diagram illustrates the area where a driving unit 10 is located on the driving substrate, shown with N=3. (Combined with...) Figure 18 and Figure 19 The driving substrate includes a gating signal line 40 and a data control line 30. The control terminal of the pixel switch 13 is coupled to the gating signal line 40, and the control terminal of the data switch 14 is coupled to the data control line 30. The driving substrate includes a substrate 00, and a first metal layer 001, a second metal layer 002, a third metal layer 006, and a transparent conductive layer 003 disposed sequentially away from the substrate 00. Optionally, the material of the first metal layer 001 includes molybdenum, the materials of the second metal layer 002 and the third metal layer 006 include titanium and aluminum, and the material of the transparent conductive layer 003 includes indium tin oxide.

[0091] The storage capacitor 12 includes a reference electrode 121, a counter electrode 122 and a third electrode 123. The reference electrode 121 is opposite to the counter electrode 122, the third electrode 123 is opposite to the reference electrode 121, and the third electrode 123 is electrically connected to the counter electrode 122.

[0092] Among them, at least some of the gate signal lines 40, at least some of the data control lines 30, and the counter electrode 122 are located in the first metal layer 001, the data line 20 and the reference electrode 121 are located in the second metal layer 002, the third electrode 123 is located in the third metal layer 006, and the pixel electrode 11 is located in the transparent conductive layer 003.

[0093] Depend on Figure 19 As can be seen, the third electrode 123 is connected to the second terminal of the data switch 14 through the third via V3 penetrating the insulating layer, and the second terminal of the data switch 14 is connected to the counter electrode 122 through the fourth via V4 penetrating the insulating layer. This achieves an electrical connection between the third electrode 123 and the counter electrode 122.

[0094] The driving substrate provided in this embodiment includes three metal layers, and the three electrodes of the storage capacitor 12 are respectively located in the three metal layers, so that the storage capacitor 12 forms a sandwich structure, thereby increasing the capacitance value of the storage capacitor 12.

[0095] In the driving substrate provided in this embodiment of the invention, the capacitance value of the storage capacitor 12 is C0, where 0.5pf ≤ C0 ≤ 3fp. The capacitance value of the storage capacitor 12 is not less than 0.5pf, ensuring that the pixel electrode 11 is fully charged during the refresh cycle, thus guaranteeing sufficient driving of electrophoretic particles in electronic paper products. The capacitance value of the storage capacitor 12 is not greater than 3fp, preventing the storage capacitor 12 from being too large and affecting the PPI of the electronic paper product.

[0096] The above-mentioned embodiments illustrate the structure of the driving substrate and the driving method of the driving substrate during the display of a screen, taking N=3 or N=4 as examples.

[0097] In other embodiments, N=2, meaning one driving unit 10 includes two pixel electrodes 11 and one storage capacitor 12. In this embodiment, the display of one image includes two refresh cycles. When applied to a display panel, if the display panel includes red, green, and blue pixels, and each pixel includes a pixel electrode 11, then some driving units 10 correspond to the first red pixel and one green pixel, some driving units 10 correspond to the first red pixel and one blue pixel, and some driving units 10 correspond to the first green pixel and one blue pixel.

[0098] In another embodiment, the display panel includes four color pixels: red, green, blue, and white. A driving unit 10 in the driving substrate includes two pixel electrodes 11 and one storage capacitor 12.

[0099] In another embodiment, the display panel includes four color pixels: red, green, blue, and white. A driving unit 10 in the driving substrate includes three pixel electrodes 11 and one storage capacitor 12.

[0100] In some implementations... Figure 20 This is a schematic diagram of another driving substrate provided in an embodiment of the present invention. Figure 21 for Figure 20 A circuit diagram at position Q in the middle region. (See diagram below.) Figure 20 As shown, the driving substrate includes multiple driving units 10, each driving unit 10 including two pixel electrodes 11 and one storage capacitor 12. The pixel electrodes 11 are connected to the opposing electrode 122 of the storage capacitor 12 via a pixel switch 13, and the reference electrode 121 of the storage capacitor 12 is grounded. The control terminal of the pixel switch 13 is connected to a selection signal line 40, combined with... Figure 21As can be seen, the two pixel switches 13 in the driving unit 10 are respectively connected to the first gating signal line 40-1 and the second gating signal line 40-2. A first data line 20-1 is provided in the driving substrate, and the first data line 20-1 is connected to the storage capacitor 12 in the driving unit 10 through the data switch 14.

[0101] The driving substrate also includes a conventional driving structure 70, which includes a pixel electrode 11 and a storage capacitor 12. In the conventional driving structure 70, the pixel electrode 11 is electrically connected to the storage capacitor 12. Figure 20 The diagram illustrates that pixel electrode 11 is connected to the counter electrode 122 of storage capacitor 12 via fifth via V5. A second data line 20-2 is provided in the driving substrate, and the second data line 20-2 is connected to storage capacitor 12 in conventional driving structure 70 via data switch 14.

[0102] In addition, by Figure 20 It can be seen that the control terminal of the data switch 14 in the drive unit 10 and the control terminal of the data switch 14 in the conventional drive structure 70 are both connected to the data control line 30.

[0103] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 22 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 22 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device in the fields of smart tags, readers, and advertising signs.

[0104] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A drive substrate, characterized by, The driving substrate includes multiple driving units, each driving unit including N pixel electrodes and 1 storage capacitor, where N is a positive integer and N≥2; the storage capacitor includes an overlapping reference electrode and a counter electrode. The driving unit further includes a data switch and N pixel switches. The control terminals of the N pixel switches receive a gating signal. The first terminals of the N pixel switches are respectively coupled to the opposing electrode, and the second terminals of the N pixel switches are respectively coupled to the N pixel electrodes. The driving substrate includes a data line, which is coupled to the opposing electrode via the data switch; the driving substrate includes a data control line, the control terminal of the data switch is coupled to the data control line, the first terminal of the data switch is coupled to the data line, and the second terminal of the data switch is coupled to the opposing electrode.

2. The driving substrate according to claim 1, characterized in that, The display of an image includes N refresh cycles, and each of the N pixel electrodes writes data voltage during the N refresh cycles; wherein, During one refresh cycle: the data switch is turned on, the data line is connected to the opposite electrode, the pixel switch is turned on, the pixel electrode is connected to the opposite electrode, and the data line writes data voltage to the pixel electrode.

3. The driving substrate according to claim 2, characterized in that, The refresh cycle includes a data writing phase and a reset phase; During the data writing phase, the data line writes the data voltage to the pixel electrode; During the reset phase, the data line writes a reset voltage to the pixel electrode.

4. The driving substrate according to claim 1, characterized in that, The plurality of driving units are arranged in a row along a first direction, and the plurality of driving units are arranged in a column along a second direction, wherein the first direction and the second direction intersect. One of the data control lines is coupled to a plurality of the data switches in one of the cell rows; One of the data lines is coupled to a plurality of the data switches in one of the cell columns.

5. The driving substrate according to claim 4, characterized in that, The driving substrate includes a plurality of the cell rows and a plurality of the data control lines, wherein the plurality of data control lines are arranged along the second direction; The display of a screen includes N refresh cycles. In one refresh cycle, multiple data control lines sequentially output enable signals, and multiple data switches coupled to one data control line are simultaneously turned on under the control of the enable signals.

6. The driving substrate according to claim 5, characterized in that, The refresh cycle includes a data writing phase and a reset phase; During the data writing phase, multiple data control lines sequentially output enable signals; During the reset phase, multiple data control lines simultaneously output enable signals, wherein the data switch is turned on, and the data lines write the reset voltage to the pixel electrode.

7. The driving substrate according to claim 1, characterized in that, The driving substrate includes a gate line group, which includes N gate signal lines. The control terminals of the N pixel switches in the driving unit are respectively connected to the N gate signal lines. The plurality of driving units are arranged in a unit row along a first direction; Multiple drive units in a row of cells share a single strobe line group.

8. The driving substrate according to claim 7, characterized in that, The N gating signal lines in the gating line group are the first gating signal line, the second gating signal line, and so on up to the Nth gating signal line; The driving substrate includes a plurality of the selected line groups, wherein multiple i-th selected signal lines in the plurality of selected line groups are electrically connected to each other, i is a positive integer, 1≤i≤N.

9. The driving substrate according to claim 7, characterized in that, The display of a screen includes N refresh cycles, and the N strobe signal lines provide enable signals in the N refresh cycles respectively; the refresh cycle is t, and the duration of each enable signal provided by the strobe signal line is t.

10. The driving substrate according to claim 9, characterized in that, The refresh cycle includes a data writing phase; during the data writing phase, the data line writes a data voltage to the pixel electrode; the strobe signal line provides an enable signal for a period covering the data writing phase; Alternatively, the refresh cycle includes a data writing phase and a reset phase; during the data writing phase, the data line writes a data voltage to the pixel electrode. During the reset phase, the data line writes a reset voltage to the pixel electrode; the strobe signal line provides an enable signal for a period covering both the data writing phase and the reset phase.

11. The driving substrate according to claim 1, characterized in that, Along the thickness direction of the driving substrate, the pixel switch coupled to the pixel electrode overlaps with the pixel electrode, and the storage capacitor partially overlaps with each of the N pixel electrodes.

12. The driving substrate according to claim 11, characterized in that, In the driving unit, N pixel electrodes are arranged along a first direction, and the electrodes of the storage capacitor extend along the first direction.

13. The driving substrate according to claim 10, characterized in that, N=4, and the four pixel electrodes are arranged in a 2-row, 2-column configuration.

14. The driving substrate according to claim 13, characterized in that, The four pixel electrodes are arranged into a first electrode row and a second electrode row along a first direction. The two pixel electrodes of the first electrode row near the end of the second electrode row are the first end, and the two pixel electrodes of the second electrode row near the end of the first electrode row are the second end. The storage capacitor and the first ends of the two pixel electrodes, and the second ends of the two pixel electrodes overlap; The driving substrate includes a gating signal line extending along the first direction, the control terminal of the pixel switch is coupled to the gating signal line, and the driving unit is correspondingly connected to four of the gating signal lines; In the second direction, two of the four gating signal lines are located on one side of the storage capacitor, and the other two are located on the other side of the storage capacitor. The second direction intersects the first direction. The driving substrate further includes a data control line extending along the first direction, and the control terminal of the data switch is coupled to the data control line; in the second direction, the data control line is located on one side of the storage capacitor.

15. The driving substrate according to claim 1, characterized in that, The driving substrate includes a gating signal line and a data control line. The control terminal of the pixel switch is coupled to the gating signal line, and the control terminal of the data switch is coupled to the data control line. The driving substrate includes a substrate, and a first metal layer, a second metal layer, and a transparent conductive layer disposed sequentially away from the substrate; In this configuration, at least a portion of the gating signal line, at least a portion of the data control line, and the reference electrode are located in the first metal layer, the data line and the counter electrode are located in the second metal layer, and the pixel electrode is located in the transparent conductive layer.

16. The driving substrate according to claim 15, characterized in that, At least one of the gating signal lines includes a first segment and a second segment, wherein the first segment is located in the first metal layer and the second segment is located in the second metal layer; And / or, at least one of the data control lines includes a third segment and a fourth segment, the third segment being located in the first metal layer and the fourth segment being located in the second metal layer.

17. The driving substrate according to claim 1, characterized in that, The driving substrate includes a gating signal line and a data control line. The control terminal of the pixel switch is coupled to the gating signal line, and the control terminal of the data switch is coupled to the data control line. The driving substrate includes a substrate, and a first metal layer, a second metal layer, a third metal layer and a transparent conductive layer disposed sequentially away from the substrate; The storage capacitor further includes a third electrode, which is opposite to the reference electrode and is electrically connected to the opposite electrode; Wherein, at least a portion of the gating signal line, at least a portion of the data control line, and the counter electrode are located in the first metal layer, the data line and the reference electrode are located in the second metal layer, the third electrode is located in the third metal layer, and the pixel electrode is located in the transparent conductive layer.

18. The driving substrate according to claim 1, characterized in that, The capacitance value of the storage capacitor is C0, where 0.5pf ≤ C0 ≤ 3fp.

19. A display panel, characterized by The display panel includes the driving substrate as described in any one of claims 1 to 18.

20. The display panel according to claim 19, characterized in that, The display panel further includes a display medium and an opposing substrate; the display medium is located between the driving substrate and the opposing substrate. The opposing substrate also includes a common electrode, which overlaps with the pixel electrode along the thickness direction of the display panel.

21. The display panel according to claim 20, characterized in that, The opposing substrate further includes a color resist layer, which includes at least three different color resist units; along the thickness direction of the display panel, the color resist units overlap with the pixel electrodes; The N color resist units overlapped by the N pixel electrodes in the driving unit have different colors.

22. A display device comprising: Includes the display panel as described in any one of claims 19 to 21.

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