A reset signal control method and apparatus

Abstract

This invention provides a reset signal control method and apparatus. The method includes: Step 1: The system is powered on, and the control board outputs a first reset signal to reset the target peripheral according to a preset timing sequence, while the core board keeps the second reset signal in an invalid state; Step 2: After the core board completes initialization, it sends a target peripheral reset control authority handover command to the control board according to a preset communication protocol; Step 3: After receiving the reset control authority handover command, the control board monitors whether the core board has set the second reset signal to an invalid level. If so, it proceeds to the next step; otherwise, it repeats this step; Step 4: The control board shields the first reset signal and pulls the corresponding port voltage high to a preset voltage and maintains it until the system is powered off. This invention can satisfy the peripheral reset timing sequence while maintaining the normal operation of the vehicle information system, thus improving the stability of the product.

Description

Technical Field

[0001] This invention relates to the field of signal control technology, and in particular to a reset signal control method and apparatus. Background Technology

[0002] Currently, in-vehicle information systems based on a control board + core board architecture have a microprocessor (MCU) on the control board for receiving various commands and controlling the transmission of various system signals. The core board is mainly based on a System-on-Chip (SoC) solution and has various application programs installed to handle multimedia content, including audio and video playback and interface display. In the current design, the system reset signal is issued by the SoC's application program, which notifies the MCU to execute via a preset software protocol.

[0003] To enrich the functionality of in-vehicle systems, adding external devices (such as SXM boxes) is a common expansion method. Some peripherals have special reset requirements (especially during certain certification tests). If the current method of issuing reset signals from the core board is used, the timing of the peripheral reset will not meet the requirements because it needs to communicate with the MCU protocol, and the SOC is not yet running when the in-vehicle information system is first powered on. Alternatively, to meet this timing requirement, the ports of the control board and the core board that connect to the peripheral reset signals can be connected together. However, the control board and the core board use different voltages. For example, the MCU is a 5V system, and the SOC is a 3.3V system. If the reset ports of the two are directly connected together, it will cause timing discrepancies, leading to system malfunctions.

[0004] Therefore, there is an urgent need for a technical solution that can meet the timing requirements of peripheral device reset and enable the vehicle information system to work normally. Summary of the Invention

[0005] This invention provides a reset signal control method and apparatus, which aims to overcome the deficiencies in the prior art, satisfying both the reset timing of peripheral devices and maintaining the normal operation of the vehicle information system, thereby improving the stability of the product.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] This invention provides a reset signal control method, comprising:

[0008] Step 1: The system is powered on. The control board outputs the first reset signal according to the preset timing to reset the target peripheral device, while the core board keeps the second reset signal in an invalid state.

[0009] Step 2: After the core board completes initialization, it sends a target peripheral reset control authority handover command to the control board according to the preset communication protocol.

[0010] Step 3: After receiving the reset control authority handover instruction, the control board monitors whether the core board has set the second reset signal to an invalid level. If yes, proceed to the next step; otherwise, repeat this step.

[0011] Step 4: The control board blocks the first reset signal and pulls the corresponding port voltage up to the preset voltage and maintains it until the system is powered off.

[0012] Specifically, the effective level of the first reset signal and the second reset signal is low, and the invalid level is high.

[0013] Specifically, the preset communication protocol is a serial communication protocol.

[0014] Specifically, the preset communication protocol is the UART communication protocol.

[0015] Specifically, the preset voltage is the invalid level of the first reset signal.

[0016] Another aspect of the present invention provides a reset signal control device, comprising: a first reset signal module, a pull-up signal module, a first reset port, a first communication module, a reset control authority module, and a power-on module disposed in a control board; a second reset signal module, a second reset port, a second communication module, and a power supply module disposed in a core board; and further comprising an external reset module and an external power supply interface.

[0017] The first reset port is connected to the first reset signal module, the pull-high signal module, and the peripheral reset module; the peripheral reset module is also connected to the second reset port. The reset control authority module is connected to the first reset signal module, the pull-high signal module, and the first communication module. The second communication module is connected to the first communication module and the second reset signal module; the second reset signal module is also connected to the second reset port. The power-on module is connected to the power supply module and the peripheral power supply interface.

[0018] The first reset signal module is used to output a first reset signal according to a preset reset timing sequence when the system is powered on;

[0019] The pull-up signal module is used to pull the first reset port up to a preset voltage and maintain it until the system is powered off;

[0020] The first reset port is used to receive the first reset signal and send it to the peripheral reset module;

[0021] The first communication module is used to transmit information with the second communication module according to a preset communication protocol;

[0022] The reset control permission module is used to receive a reset control permission transfer instruction and switch the reset control permission of the target peripheral.

[0023] The power-on module is used to output power control signals to the power module and peripheral power supply interface to turn the power supply on or off to the core board or target peripheral.

[0024] The second reset signal module is used to independently output a second reset signal to reset the target peripheral after obtaining reset control authority for the target peripheral;

[0025] The second reset port is used to receive the second reset signal and send it to the peripheral reset module;

[0026] The second communication module is used to transmit information with the first communication module according to a preset communication protocol;

[0027] The power module is used to receive instructions from the power-on module and turn the power supply to the core board on or off.

[0028] The peripheral reset module is used to receive signals from the first reset port or the second reset port and generate a target peripheral reset signal;

[0029] The peripheral power supply interface is used to receive the power-on module's command and send it to the target peripheral.

[0030] Specifically, the first reset port is a GPIO, a reset function multiplexed port.

[0031] Specifically, the first communication module and the second communication module are serial communication modules.

[0032] Specifically, the first communication module and the second communication module are UART communication modules.

[0033] Specifically, the peripheral reset module is a signal processing module that reverses the signals of the first reset signal module and the second reset signal module.

[0034] Specifically, the peripheral reset module includes: a first input terminal, a second input terminal, an output terminal, a first transistor, a second transistor, a first resistor, a second resistor, and a third resistor;

[0035] The collector of the first transistor is connected to the output terminal and one end of the first resistor; the base of the first transistor is connected to one end of the second resistor and one end of the third resistor; the emitter of the first transistor is grounded; the other end of the first resistor is connected to the power supply voltage of the control board; and the other end of the third resistor is grounded.

[0036] The collector of the second transistor is connected to the first input terminal and the other end of the second resistor, the base of the first transistor is connected to the second input terminal, and the emitter of the first transistor is grounded.

[0037] The beneficial effects of this invention are as follows: When the core board is powered on and has not completed initialization, the control board resets the target peripheral. After the core board completes initialization, the control board transfers the reset control authority of the target peripheral to the core board, then shields its own reset signal and pulls the corresponding port voltage up to a preset voltage and maintains it until the system is powered off. This achieves both satisfying the peripheral reset timing and maintaining the normal operation of the vehicle information system, thus improving the stability of the product. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the reset signal control method of the present invention;

[0039] Figure 2 This is a schematic diagram of the reset signal control device of the present invention;

[0040] Figure 3 This is a circuit diagram of the peripheral reset module of the present invention. Detailed Implementation

[0041] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The drawings are for reference and illustration only and do not constitute a limitation on the scope of protection of the present invention.

[0042] In the process described in the specification, claims, or drawings of this invention, each step is numbered (e.g., step 10, 20, etc.). These numbers are used only to distinguish the steps and do not represent any execution order. It should be noted that the terms "first," "second," etc., used herein are only for distinguishing the objects being described and do not represent a chronological order, nor do they indicate that "first," "second," etc., are different types.

[0043] Example 1

[0044] like Figure 1 As shown, this embodiment provides a reset signal control method, including:

[0045] Step 1: The system is powered on. The control board outputs the first reset signal according to the preset timing to reset the target peripheral device, while the core board keeps the second reset signal in an invalid state.

[0046] In this embodiment, the effective level of the first reset signal and the second reset signal is low, and the ineffective level is high. Of course, the opposite settings can be made according to actual needs.

[0047] The preset timing refers to outputting a high level at a certain moment, maintaining it for a certain period of time, and then outputting a low level.

[0048] Step 2: After the core board completes initialization, it sends a target peripheral reset control authority handover command to the control board according to the preset communication protocol.

[0049] When the system is powered on, the control board controls the target peripheral to reset in order to meet specific reset timing requirements. After the control board completes its task, the core board will take back the reset control, which is beneficial for the core board to generate a reset signal when the APP program sends an exception, thereby improving the stability and real-time performance of the APP program.

[0050] In this embodiment, the preset communication protocol is a serial communication protocol.

[0051] In this embodiment, the preset communication protocol is the UART communication protocol.

[0052] Step 3: After receiving the reset control authority handover instruction, the control board monitors whether the core board has set the second reset signal to an invalid level. If so, proceed to the next step; otherwise, repeat this step.

[0053] Step 4: The control board blocks the first reset signal and pulls the corresponding port voltage up to the preset voltage and maintains it until the system is powered off.

[0054] In this embodiment, the preset voltage is the invalid level of the first reset signal.

[0055] Example 2

[0056] like Figure 2 As shown, this embodiment provides a reset signal control device, including: a first reset signal module, a pull-up signal module, a first reset port, a first communication module, a reset control authority module, and a power-on module disposed in a control board; a second reset signal module, a second reset port, a second communication module, and a power supply module disposed in a core board; and also includes an external reset module and an external power supply interface.

[0057] The first reset port is connected to the first reset signal module, the pull-high signal module, and the peripheral reset module; the peripheral reset module is also connected to the second reset port. The reset control authority module is connected to the first reset signal module, the pull-high signal module, and the first communication module. The second communication module is connected to the first communication module and the second reset signal module; the second reset signal module is also connected to the second reset port. The power-on module is connected to the power supply module and the peripheral power supply interface.

[0058] The first reset signal module is used to output a first reset signal according to a preset reset timing sequence when the system is powered on;

[0059] The pull-up signal module is used to pull the first reset port up to a preset voltage and maintain it until the system is powered off;

[0060] The first reset port is used to receive the first reset signal and send it to the peripheral reset module;

[0061] The first communication module is used to transmit information with the second communication module according to a preset communication protocol;

[0062] The reset control permission module is used to receive a reset control permission transfer instruction and switch the reset control permission of the target peripheral.

[0063] The power-on module is used to output power control signals to the power module and peripheral power supply interface to turn the power supply on or off to the core board or target peripheral.

[0064] The second reset signal module is used to independently output a second reset signal to reset the target peripheral after obtaining reset control authority for the target peripheral;

[0065] The second reset port is used to receive the second reset signal and send it to the peripheral reset module;

[0066] The second communication module is used to transmit information with the first communication module according to a preset communication protocol;

[0067] The power module is used to receive instructions from the power-on module and turn the power supply to the core board on or off.

[0068] The peripheral reset module is used to receive signals from the first reset port or the second reset port and generate a target peripheral reset signal;

[0069] The peripheral power supply interface is used to receive the power-on module's command and send it to the target peripheral.

[0070] In this embodiment, the first reset port is a GPIO, a reset function multiplexed port.

[0071] In this embodiment, the first communication module and the second communication module are serial communication modules.

[0072] In this embodiment, the first communication module and the second communication module are UART communication modules.

[0073] In this embodiment, the peripheral reset module is a signal processing module that reverses the signals of the first reset signal module and the second reset signal module.

[0074] The operation of the reset signal control device described in this embodiment is the same as that of the reset signal control method described in Embodiment 1, and will not be repeated here.

[0075] Example 3

[0076] like Figure 3 As shown, unlike Embodiment 2, this embodiment provides a specific implementation circuit for the peripheral reset module, including:

[0077] First input terminal, second input terminal, output terminal, first transistor Q1, second transistor Q2, first resistor R1, second resistor R2, third resistor R3;

[0078] The collector of the first transistor Q1 is connected to the output terminal and one end of the first resistor R1. The base of the first transistor Q1 is connected to one end of the second resistor R2 and the third resistor R3. The emitter of the first transistor Q1 is grounded. The other end of the first resistor R1 is connected to the +5V power supply voltage of the control board. The other end of the third resistor R3 is grounded.

[0079] The collector of the second transistor Q2 is connected to the first input terminal and the other end of the second resistor R2, the base of the first transistor Q1 is connected to the second input terminal, and the emitter of the first transistor Q1 is grounded.

[0080] The working process of the reset module in this embodiment is as follows:

[0081] When the system is powered on, the signal at the first input terminal controlled by the first reset port is at a high level, the first transistor Q1 is turned on, and the signal at the output terminal is pulled low, thereby resetting the target peripheral.

[0082] After the core board is initialized, the control board transfers the reset control authority to the core board. The second reset port controls the signal of the second input terminal to be high, and then the first reset port pulls the signal of the first input terminal high and keeps it until the system is shut down.

[0083] If the target peripheral needs to be reset during operation, the signal at the second input terminal controlled by the second reset port is at a low level, the second transistor Q2 is cut off, the first transistor Q1 is turned on, and the signal at the output terminal is pulled low, thereby resetting the target peripheral.

[0084] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A reset signal control method, characterized by, include: Step 1: The system is powered on. The control board outputs the first reset signal according to the preset timing to reset the target peripheral device, while the core board keeps the second reset signal in an invalid state. Step 2: After the core board completes initialization, it sends a target peripheral reset control authority handover command to the control board according to the preset communication protocol. Step 3: After receiving the reset control authority handover instruction, the control board monitors whether the core board has set the second reset signal to an invalid level. If yes, proceed to the next step; otherwise, repeat this step. Step 4: The control board blocks the first reset signal and pulls the corresponding port voltage up to the preset voltage and maintains it until the system is powered off.

2. The reset signal control method according to claim 1, characterized by, The effective level of the first reset signal and the second reset signal is low, and the invalid level is high.

3. The reset signal control method according to claim 1, characterized by, The preset communication protocol is a serial communication protocol.

4. The reset signal control method according to claim 3, characterized by, The preset communication protocol is the UART communication protocol.

5. The reset signal control method according to claim 2, characterized in that, The preset voltage is the invalid level of the first reset signal.

6. A reset signal control device, characterized in that, include: The control board includes a first reset signal module, a pull-high signal module, a first reset port, a first communication module, a reset control authority module, and a power-on module; the core board includes a second reset signal module, a second reset port, a second communication module, and a power supply module; and also includes an external reset module and an external power supply interface. The first reset port is connected to the first reset signal module, the pull-high signal module, and the peripheral reset module; the peripheral reset module is also connected to the second reset port. The reset control authority module is connected to the first reset signal module, the pull-high signal module, and the first communication module. The second communication module is connected to the first communication module and the second reset signal module; the second reset signal module is also connected to the second reset port. The power-on module is connected to the power supply module and the peripheral power supply interface. The first reset signal module is used to output a first reset signal according to a preset reset timing sequence when the system is powered on; The pull-up signal module is used to pull the first reset port up to a preset voltage and maintain it until the system is powered off; The first reset port is used to receive the first reset signal and send it to the peripheral reset module; The first communication module is used to transmit information with the second communication module according to a preset communication protocol; The reset control permission module is used to receive a reset control permission transfer instruction and switch the reset control permission of the target peripheral. The power-on module is used to output power control signals to the power module and peripheral power supply interface to turn the power supply on or off to the core board or target peripheral. The second reset signal module is used to independently output a second reset signal to reset the target peripheral after obtaining reset control authority for the target peripheral; The second reset port is used to receive the second reset signal and send it to the peripheral reset module; The second communication module is used to transmit information with the first communication module according to a preset communication protocol; The power module is used to receive instructions from the power-on module and turn the power supply to the core board on or off. The peripheral reset module is used to receive signals from the first reset port or the second reset port and generate a target peripheral reset signal; The peripheral power supply interface is used to receive the power-on module's command and send it to the target peripheral.

7. The reset signal control device according to claim 6, characterized in that, The first reset port is a GPIO, a reset function multiplexed port.

8. The reset signal control device according to claim 6, characterized in that, The first communication module and the second communication module are serial communication modules.

9. The reset signal control device according to claim 7, characterized in that, The first communication module and the second communication module are UART communication modules.

10. The reset signal control device according to claim 6, characterized in that, The peripheral reset module is a signal processing module that inverts the signals from the first reset signal module and the second reset signal module. Specifically, the peripheral reset module includes: a first input terminal, a second input terminal, an output terminal, a first transistor, a second transistor, a first resistor, a second resistor, and a third resistor; The collector of the first transistor is connected to the output terminal and one end of the first resistor; the base of the first transistor is connected to one end of the second resistor and one end of the third resistor; the emitter of the first transistor is grounded; the other end of the first resistor is connected to the power supply voltage of the control board; and the other end of the third resistor is grounded. The collector of the second transistor is connected to the first input terminal and the other end of the second resistor, the base of the first transistor is connected to the second input terminal, and the emitter of the first transistor is grounded.

Images