An EEPROM data management method, device, equipment and storage medium

Abstract

The application relates to the computer technical field and discloses an EEPROM data management method applied to a BMC, which comprises the following steps: sending a reading message to a preset error correction module through a reading and writing module; receiving the reading message through the error correction module, and respectively acquiring target data and an error correction code from an EEPROM and a target flash memory in response to the reading message; verifying the integrity of the target data by using the error correction code through the error correction module; feeding back data normal information to the reading and writing module through the error correction module when the verification is passed; receiving the data normal information through the reading and writing module, and reading the target data from the EEPROM to a BMC cache in response to the data normal information. The application solves the problems that the storage space is excessively occupied, the equipment is not simple enough, and the system operation is not stable enough when EEPROM data is managed.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and specifically to an EEPROM data management method, apparatus, device, and storage medium. Background Technology

[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is widely used in applications requiring high data storage security and reliability, such as access control and attendance systems, measuring and medical instruments, contactless smart cards, and tax-controlled cash registers. However, with increasing programming cycles, EEPROMs are susceptible to damage, and stored data can become corrupted due to vibrations, noise, magnetism, etc.

[0003] On a server, the EEPROM stores MAC (Media Access Control) addresses, FRU (Field Replacement Unit) information, serial port switching information, login authentication keys, account passwords, and other user-customizable information. This information is crucial for the normal operation of the server system and the provision of user services. Data anomalies can easily lead to server crashes, user login failures, and device malfunction alarms, thus requiring high data reliability. Therefore, server applications require the EEPROM to automatically correct data errors after faults or data transitions to ensure stable and reliable server operation.

[0004] Related technologies use redundant encoding to ensure the data stored in EEPROM has error correction capabilities. However, these technologies encode the data and then store the error correction code along with the data in the EEPROM. The read / write software in the BMC (Board Management Controller) recalculates the error correction code when reading data. If the error correction code matches the one stored in the EEPROM, the data is read into the BMC cache. When the host system requests data from the BMC, the data in the BMC cache is forwarded to the host. This method requires additional space to store the error correction code, which reduces the effective data capacity of the EEPROM. This significantly reduces the utilization rate of the already limited EEPROM storage space. Furthermore, storing data and error correction codes together requires data encoding, and the read / write software must use decoding software to decode the encoded data to obtain usable data. Therefore, this results in problems such as excessive EEPROM storage space consumption, insufficient device simplification, and unstable system operation. Summary of the Invention

[0005] In view of this, the present invention provides an EEPROM data management method, apparatus, device and storage medium to solve the problems of excessive storage space occupation, insufficient device simplification and unstable system operation when managing EEPROM data in related technologies.

[0006] In a first aspect, the present invention provides an EEPROM data management method, applied to a BMC, comprising: sending a read message to a preset error correction module via a read / write module; receiving the read message via the error correction module, and in response to the read message, obtaining target data and error correction codes from the EEPROM and the target flash memory respectively; verifying the integrity of the target data using the error correction codes via the error correction module; when the verification is successful, feeding back data normal information to the read / write module via the error correction module; receiving the data normal information via the read / write module, and in response to the data normal information, reading the target data from the EEPROM into the BMC cache.

[0007] Based on the aforementioned technical means, this embodiment stores the error correction code in a separate target flash memory and deploys the read / write module and the error correction module independently. When the read / write module needs to read data into the BMC cache, the error correction module first checks the data in the EEPROM and verifies the data integrity using the error correction code obtained from the target flash memory. Only when the verification is successful is the error correction module informed that the target data in the EEPROM is normal and can be read. The read / write module then reads the target data from the EEPROM into the BMC cache for use by the server host. On one hand, the error correction code is no longer stored simultaneously with the target data, reducing the EEPROM storage space occupied. On the other hand, the error correction code and target data no longer need to be encoded and stored, eliminating the need for encoding / decoding software for the read / write module, reducing its complexity, and improving the device's simplification. Furthermore, the error correction module and the read / write module run as two independent processes, with read / write not coupled to error correction, improving system stability.

[0008] In one optional implementation, sending a read message to a preset error correction module via the read / write module includes: when the BMC powers on, detecting whether the EEPROM is initialized via the read / write module; when the EEPROM is not initialized, writing default configuration data to the EEPROM via the read / write module and marking the EEPROM as initialized; when the EEPROM is initialized, sending an initialized message to the error correction module via the read / write module, wherein the initialized message serves as a read message.

[0009] In one optional implementation, in response to a read message, target data and error correction codes are retrieved from the EEPROM and target flash memory respectively, including: when the BMC powers on, detecting whether the error correction code area of ​​the target flash memory is available through the error correction module, wherein the error correction code area is marked as available when the error correction code stored in the target flash memory can correct the target data; when the error correction code area is available, determining whether an initialization message has been received through the error correction module; when an initialization message is received, retrieving target data and error correction codes from the EEPROM and target flash memory respectively through the error correction module.

[0010] In an optional implementation, the method further includes: when the error correction code area is unavailable, waiting for an initialization message through the error correction module; when the initialization message is received through the error correction module, obtaining target data from the EEPROM in response to the initialization message, and calculating the error correction code corresponding to the target data; writing the error correction code into the target flash memory through the error correction module, and marking the error correction code area of ​​the target flash memory as available.

[0011] According to the above technical means, the error correction module and read / write module provided in this embodiment both run automatically when the BMC powers on, each performing its own task and cooperating with each other during task execution. First, when the BMC powers on, the read / write module checks whether the EEPROM is initialized. If initialized, it informs itself that it is ready, and the error correction module can start executing the error correction function at any time. If not initialized, the read / write module initializes the EEPROM. Simultaneously, upon BMC power-on, the error correction module immediately starts and checks whether the error correction code in the target flash memory is available. If available, it waits for the initialization message sent by the read / write module and immediately begins data integrity verification. If unavailable, it waits for the initialization message to arrive, thus confirming that the EEPROM already has data, recalculating the error correction code, saving it to the target flash memory, and assuming the error correction code is correct, marking it as available, and then re-executing the data integrity verification process. In this way, the read / write module and the error correction module are two parallel processes. They only need to wait when they need each other's data. Compared with related technologies that read data through the read / write module and then perform error correction, this not only reduces the task execution time, but also eliminates the need to repeat the reading process multiple times if there are errors in the data or error correction codes. The error correction module will accurately organize the error correction codes and data before the read / write module reads the data, ensuring the integrity of the data.

[0012] In an optional implementation, the method further includes: when verification fails, correcting the target data using error correction codes via an error correction module; when error correction fails, marking the error correction code area of ​​the target flash memory as unavailable via the error correction module; feeding back reinitialization information to the read / write module via the error correction module; receiving the reinitialization information via the read / write module and reinitializing the EEPROM in response to the reinitialization information; when error correction succeeds, writing the corrected target data into the EEPROM via the error correction module to update the target data in the EEPROM; feeding back reread information to the read / write module via the error correction module; receiving the reread information via the read / write module and re-executing the step of sending a read message to the preset error correction module in response to the reread information.

[0013] In an optional implementation, the method further includes: receiving second target data fed back by the server host through a read-write module; writing the second target data into an EEPROM through the read-write module; when the second target data is written into the EEPROM, detecting whether the second target data and the target data are the same through an error correction module; if the data are different, calculating a second error correction code for the second target data through the error correction module; and writing the second error correction code into the target flash memory through the error correction module to update the error correction code in the target flash memory.

[0014] In one optional implementation, the integrity of the target data is verified by the error correction module using error correction codes, including: verifying whether each bit of the target data is erroneous using CRC error correction codes; when each bit of the target data is verified to be correct, the integrity of the target data is determined to be verified as successful; when at least one bit of the target data is verified to be erroneous, the integrity of the target data is determined to be unsuccessful.

[0015] Secondly, the present invention provides an EEPROM data management device applied to a BMC, comprising: an error correction notification module for sending a read message to a preset error correction module via a read / write module; an error correction data acquisition module for receiving the read message via the error correction module and, in response to the read message, acquiring target data and error correction codes from the EEPROM and the target flash memory respectively; a verification module for verifying the integrity of the target data using the error correction code via the error correction module; a normal feedback module for feeding back data normal information to the read / write module via the error correction module when the verification is successful; and a data reading module for receiving the data normal information via the read / write module and, in response to the data normal information, reading the target data from the EEPROM into the BMC cache.

[0016] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0017] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an EEPROM data management method according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the structure of a server system according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a CRC check according to an embodiment of the present invention;

[0022] Figure 4 This is another flowchart illustrating an EEPROM data management method according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure of an EEPROM data management device according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] According to an embodiment of the present invention, an embodiment of an EEPROM data management method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0027] This embodiment provides an EEPROM data management method, which can be used in the aforementioned computer device. Figure 1 This is a flowchart of an EEPROM data management method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0028] Step S101: Send a read message to the preset error correction module through the read / write module.

[0029] In step S102, the error correction module receives a read message and, in response to the read message, retrieves the target data and error correction code from the EEPROM and the target flash memory, respectively.

[0030] Step S103: The integrity of the target data is verified by the error correction module using the error correction code.

[0031] Step S104: When the verification is successful, the error correction module sends the data normal information back to the read / write module.

[0032] Step S105: Receive normal data information through the read / write module, and in response to the normal data information, read the target data from the EEPROM into the BMC cache.

[0033] Specifically, the BMC is a dedicated controller in the server used to record server information, monitor server status, and record server logs. In this embodiment, two separate software modules are deployed within this controller: a read / write module and an error correction module. The read / write module is similar to read / write software in related technologies, used to read data from EEPROM and save it to the BMC cache. When the BMC receives a data read request from the host (server host) through the read / write module, it forwards the data in the BMC cache to the server host. The error correction module inherits the capabilities of data integrity verification, error correction, and error correction code generation, allowing the read / write module to focus solely on data reading and writing. Furthermore, this application utilizes the free space of the Flash storage in the server (target flash memory) to store error correction codes. Flash storage is a form of electronically erasable programmable read-only memory, allowing for multiple erasures and writes during operation, used to store system software and file system images, etc. Figure 2As shown, the error correction module can access the target flash memory to store and read data, as well as the data stored in the EEPROM, and can also detect the system software's read and write operations on the EEPROM.

[0034] In this embodiment of the invention, the error correction module and the read / write module communicate with each other. After the BMC powers on, when the BMC needs to read data from the EEPROM, it first sends a read message to the error correction module through the read / write module. The error correction module responds to the read message by retrieving the target data and error correction codes from the EEPROM and the target flash memory, respectively. The error correction codes include, but are not limited to, Hamming codes, parity check codes, and BCD codes. Then, the error correction module uses the error correction codes to verify the integrity of the target data. If the data verification passes, it promptly feeds back data integrity information to the read / write module; if the verification fails, it uses the error correction codes to correct the data, thus achieving successful verification. Afterward, based on the data integrity information, the read / write module reads the target data from the EEPROM and saves the target data to the BMC cache.

[0035] This approach eliminates the need to store error correction codes concurrently with target data, reducing EEPROM storage space usage. Furthermore, the error correction codes and target data no longer require encoding and storage, removing encoding / decoding software from the read / write module, thus reducing its complexity and improving device simplification. Additionally, the error correction module and read / write module run as two independent processes, with the read / write process not coupled to the error correction process, improving system stability.

[0036] In some alternative implementations, step S101 includes:

[0037] Step a1: When the BMC powers on, it checks whether the EEPROM is initialized through the read / write module.

[0038] Step a2: When the EEPROM is not initialized, the default configuration data is written to the EEPROM through the read / write module, and the EEPROM is marked as initialized.

[0039] Step a3: When the EEPROM is initialized, an initialized message is sent to the error correction module through the read / write module, where the initialized message is used as a read message.

[0040] In some alternative implementations, step S102 includes:

[0041] Step a4: When the BMC is powered on, the error correction module detects whether the error correction code area of ​​the target flash memory is available. When the error correction code stored in the target flash memory can correct the target data, the error correction code area is marked as available.

[0042] Step a5: When the error correction code area is available, the error correction module determines whether an initialized message has been received.

[0043] Step a6: When the initialized message is received, the error correction module retrieves the target data and error correction code from the EEPROM and the target flash memory, respectively.

[0044] In this embodiment, an EEPROM data management method further includes:

[0045] Step a7: When the error correction code area is unavailable, wait for the initialization message through the error correction module;

[0046] Step a8: When an initialized message is received through the error correction module, the target data is retrieved from the EEPROM in response to the initialized message, and the error correction code corresponding to the target data is calculated.

[0047] Step a9: Write the error correction code into the target flash memory through the error correction module, and mark the error correction code area of ​​the target flash memory as available.

[0048] Specifically, to further improve system stability and data read / write efficiency, the error correction module and read / write module provided in this embodiment do not have a specific order of operation. They both run automatically when the BMC is powered on. The error correction module and read / write module each perform their own tasks and cooperate with each other during the task execution process.

[0049] Specifically, when the BMC powers on, the read / write module first checks whether the EEPROM is initialized. If the EEPROM is initialized, it indicates that data exists in the EEPROM. The read / write module then sends an initialized message to the error correction module, informing it that it is ready to read data and requesting the error correction module to begin error correction. If the read / write module detects that the EEPROM is not initialized, indicating that the target data does not yet exist in the EEPROM, the read / write module initializes the EEPROM by writing default configuration data and marking the EEPROM as initialized. This ensures that data exists in the EEPROM before the error correction module performs data verification, preventing logical errors and improving system stability.

[0050] During the same period, upon power-on, the BMC immediately initiates the error correction module. This module checks the availability of error correction codes in the target flash memory. In this embodiment, the availability of the error correction codes stored in the target flash memory is the criterion for marking the error correction code area as available or unavailable. In this embodiment, each time the error correction module calculates the error correction code using the target data, it assumes the code is available and does not require verification. The actual availability of the error correction code is verified synchronously during subsequent error correction processes, reducing the need for repeated verification. Based on this, if the error correction code area is available, the error correction module waits for an initialization message. Once it receives the initialization message from the read / write module, the error correction module assumes data exists in the EEPROM and can immediately begin the data integrity verification task, retrieving the target data and error correction codes from both the EEPROM and the target flash memory, thus improving data reading efficiency.

[0051] In this embodiment, if the error correction code area is marked as unavailable, it indicates that the error correction code cannot correct errors correctly. The error correction module must wait for the initialization message to arrive, thus confirming that data already exists in the EEPROM. Once the error correction module confirms that data already exists in the EEPROM, it retrieves the target data from the EEPROM again, calculates the error correction code using the target data, and saves it to the target flash memory. At this point, the error correction code is assumed to be correct, and the error correction code area is marked as available. The data integrity verification process is then re-executed to ensure the accuracy of the data and the error correction code.

[0052] The solution provided by this invention involves two parallel processes: the read / write module and the error correction module. The read / write module only needs to wait when data from the other is required. Compared with related technologies that use the read / write module to read data and then perform error correction, this not only reduces task execution time but also eliminates the need for the read module to repeat the reading process multiple times if the target data or error correction code is incorrect. The error correction module in this embodiment accurately organizes the error correction code and data before the read / write module reads the data, ensuring data integrity.

[0053] In some optional embodiments, the EEPROM data management method provided by this invention further includes the following steps:

[0054] Step b1: When the verification fails, the error correction module uses error correction codes to correct the target data.

[0055] Step b2: When error correction fails, the error correction code area of ​​the target flash memory is marked as unavailable by the error correction module.

[0056] Step b3: The error correction module sends reinitialization information back to the read / write module.

[0057] Step b4: Receive reinitialization information through the read / write module.

[0058] Step b5: The EEPROM is reinitialized in response to the reinitialization information via the read / write module.

[0059] Specifically, in this embodiment of the invention, when the error correction module fails to verify the data in the EEPROM, it determines that the target data has a problem, and then uses error correction codes to correct the target data. The specific steps for using error correction codes to correct the target data are existing technology and will not be described in detail in this embodiment. Subsequently, when error correction fails, it indicates that the current error correction code has a problem and cannot correctly correct the data. Therefore, this embodiment of the invention marks the error correction code area of ​​the target flash memory as unavailable through the error correction module. This forms a closed loop with the logic in the aforementioned embodiment where the error correction module updates the error correction code when it finds it unavailable upon startup, improving the accuracy of the error correction code. Simultaneously, the error correction module feeds back re-initialization information to the read / write module, causing the read / write module to re-initialize the EEPROM, update the target data in the EEPROM, and update the error correction code in the target flash memory, improving the reliability of the target data and the error correction code.

[0060] Step b6: When the error correction is successful, the error-corrected target data is written to the EEPROM through the error correction module to update the target data in the EEPROM.

[0061] Step b7: Feedback from the error correction module is sent to the read / write module to reread the information.

[0062] Step b8: Receive the reread information through the read / write module.

[0063] Step b9 involves re-executing the step of sending a read message to the preset error correction module in response to rereading information via the read / write module.

[0064] Specifically, when error correction is successful, it means that the error correction code is correct. The error correction module then writes the corrected target data into the EEPROM to update the target data in the EEPROM and improve the accuracy of the target data. At the same time, it feeds back the reread information to the read-write module, causing the read-write module to start the data reading process again from step S101, which improves the accuracy of the target data and ensures that the correct data is read into the BMC cache.

[0065] In some optional embodiments, the EEPROM data management method provided by this invention further includes the following steps:

[0066] Step c1: Receive the second target data fed back by the server host through the read / write module;

[0067] Step c2: Write the second target data into the EEPROM using the read / write module;

[0068] Step c3: When the second target data is written to the EEPROM, the error correction module checks whether the second target data and the target data are the same.

[0069] Step c4: If the data are different, calculate the second error correction code of the second target data through the error correction module;

[0070] Step c5: Write the second error correction code into the target flash memory through the error correction module to update the error correction code in the target flash memory.

[0071] Specifically, in practical applications, the server host not only reads data from the EEPROM but also modifies the target data and stores the modified data back into the EEPROM. Based on this, in this embodiment, after receiving the modified second target data from the server host and writing the data into the EEPROM through the read-write module, the error correction module checks whether the second target data and the target data before modification are the same. If the data are different, the error correction module calculates a new second error correction code and then updates the error correction code in the target memory, thereby further ensuring the accuracy of the data and the error correction code.

[0072] In one specific embodiment, the error correction code uses CRC error correction code. CRC error correction code is an error check code composed of n information bits and k check bits. The k check bits are appended to the n data bits, and n+k is the word length of the cyclic redundancy check code; this check code is also called an (n+k,n) code. The n information bits can be represented as a message polynomial M(x), with the highest power being x. n -1, the agreed generator polynomial G(x) is a k+1 bit binary number with the highest power being x. k Multiply M(x) by x k That is, after shifting left by k bits and dividing by G(x), the k-bit remainder is the check bit. The division operation here is modulo 2 division, that is, when the first bit of the remainder is 1, the quotient is 1, otherwise the quotient is 0. Then the subtraction operation of each bit is bitwise subtraction without borrowing.

[0073] After CRC error correction codes are stored or transmitted, they undergo a verification process at the receiving end to determine if the data is erroneous. If an error is found, it is corrected. A CRC code is always divisible by a generator polynomial. Therefore, at the receiving end, the codeword is divided by the same generator polynomial. If the remainder is 0, the codeword is error-free; if the remainder is not 0, it indicates an error in a certain bit. The remainder varies depending on the error location, and the correspondence between the error location and the remainder is definite. By analyzing the remainder, it is possible to determine which bit in the data is erroneous, thus finding the erroneous bit and correcting the data, effectively correcting data errors and significantly improving the accuracy of data correction.

[0074] For example: Assuming we have information bits 1100 and a generator polynomial G(X) = 1011, we generate a checksum of 1100010 by modulo 2 division. (Refer to...) Figure 3 This refers to the correspondence between different error bits and the remainder. The original data is 1100, and G(X) = 1011. According to the algorithm definition, 4 bits of the original data plus 3 bits of error correction code form 7 bits of check data. First, 000 is padded to the end of the original data to get 1100000. G(X) is then divided modulo 2 by 1100000, and the remainder is 010 (the error correction code). Therefore, the correct check data consisting of the original data and the error correction code is 1100010. If the check data is 1100010, the result of dividing 1100010 modulo 2 by G(X) is 000, indicating that the check data is correct. If the check data is 1100011, the seventh bit is incorrect, so the result of dividing 1100011 modulo 2 by G(X) is 001. Similarly, the remainder results for each bit error are as follows... Figure 3 As shown. Therefore, the correctness of the data can be determined by checking whether the remainder result is 000. If the result is not 000, the error can be identified by the remainder result. By finding the error bit and modifying the data, the data error can be corrected.

[0075] In one specific embodiment, the EEPROM data management method provided by this invention is as follows:

[0076] like Figure 4 As shown, after the system powers on, the read / write module automatically runs, first checking whether the EEPROM is initialized. If it is not initialized (the EEPROM is marked as uninitialized during the first boot of a new machine, a system factory reset, or data errors), the read / write module loads the default configuration data from the code, writes it to the EEPROM, and sets the EEPROM to initialized. If the EEPROM is initialized, it prepares to read data into the BMC cache for use by the server host. Simultaneously, the error handling interface reserved in the read / write module receives messages from the error correction module, thus marking the data as normal, requiring reread, or requiring reinitialization. The read / write module receives information from the server host and is responsible for transmitting data to the server host or receiving modified data from the server host and writing it back to the EEPROM. If the data is modified, the read / write module notifies the error correction module to update the error correction code.

[0077] The error correction module provides error correction functionality for EEPROM data. It runs automatically after system power-on. First, it checks the availability of the error correction code area in the Flash memory. If the error correction code area is unavailable, it checks if the EEPROM data has been initialized. If the EEPROM is not initialized, it waits for initialization to complete. If the EEPROM data is initialized, it executes the error correction algorithm, calculates the error correction code for the data, writes the error correction code to the error correction code area in the Flash memory, and marks the error correction code area as available. If the error correction code area is available, it uses the error correction code to verify the integrity of the EEPROM data. If verification fails, error correction is initiated. If error correction succeeds, the EEPROM data is updated to correct data, and a message is sent to the read / write module to mark the data as needing to be reread. If error correction fails, a message is sent to the read / write module to mark the data as needing initialization, and the error correction module marks the error correction code in the Flash error correction area as unavailable. If verification passes, a message is sent to the read / write module to mark the data as normal. In addition, the error correction module waits for the read / write module to modify the data in the EEPROM. When it detects that the EEPROM data has been modified, it recalculates the error correction code and updates the error correction code area data.

[0078] This embodiment also provides an EEPROM data management device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0079] This embodiment provides an EEPROM data management device, such as... Figure 5 As shown, it includes:

[0080] The error correction notification module 401 is used to send a read message to a preset error correction module through the read / write module; for details, please refer to the relevant description of step S101 in the above method embodiment, which will not be repeated here.

[0081] The error correction data acquisition module 402 is used to receive a read message through the error correction module, and in response to the read message, acquire target data and error correction code from the EEPROM and the target flash memory respectively; for details, please refer to the relevant description of step S102 in the above method embodiment, which will not be repeated here.

[0082] The verification module 403 is used to verify the integrity of the target data by using the error correction code through the error correction module; for details, please refer to the relevant description of step S103 in the above method embodiment, which will not be repeated here.

[0083] The normal feedback module 404 is used to send normal data information to the read / write module through the error correction module when the verification is successful; for details, please refer to the relevant description of step S104 in the above method embodiment, which will not be repeated here.

[0084] The data reading module 405 is used to receive data normality information through the read / write module, and in response to the data normality information, read the target data from the EEPROM into the BMC cache. For details, please refer to the relevant description of step S105 in the above method embodiment, which will not be repeated here.

[0085] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0086] In this embodiment, an EEPROM data management device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0087] This invention also provides a computer device having the above-described features. Figure 5 The EEPROM data management device shown.

[0088] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 6 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0089] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0090] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0091] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0092] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0093] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0094] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0095] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An EEPROM data management method, characterized by, The method is applied to BMC and includes: Sending a read message to a preset error correction module via the read / write module; the step of sending a read message to the preset error correction module via the read / write module includes: when the BMC powers on, detecting whether the EEPROM is initialized via the read / write module; when the EEPROM is not initialized, writing default configuration data to the EEPROM via the read / write module and marking the EEPROM as initialized; when the EEPROM is initialized, sending an initialized message to the error correction module via the read / write module, wherein the initialized message is used as the read message; The error correction module receives the read message and, in response to the read message, retrieves target data and error correction codes from the EEPROM and target flash memory respectively. The retrieval of target data and error correction codes from the EEPROM and target flash memory in response to the read message includes: when the BMC powers on, the error correction module detects whether the error correction code area of ​​the target flash memory is available, wherein the error correction code area is marked as available when the error correction code stored in the target flash memory can correct the target data; when the error correction code area is available, the error correction module determines whether the initialized message has been received; when the initialized message is received, the error correction module retrieves target data and error correction codes from the EEPROM and target flash memory respectively. The error correction module uses the error correction code to verify the integrity of the target data; When the verification is successful, the error correction module sends data normality information back to the read / write module. The read / write module receives the data normality information and, in response to the data normality information, reads the target data from the EEPROM into the BMC cache.

2. The method of claim 1, wherein, The method further includes: When the error correction code area is unavailable, the error correction module waits for the initialized message. When the initialization message is received through the error correction module, the target data is retrieved from the EEPROM in response to the initialization message, and the error correction code corresponding to the target data is calculated. The error correction module writes the error correction code into the target flash memory and marks the error correction code area of ​​the target flash memory as available.

3. The method of claim 2, wherein, The method further includes: When the verification fails, the error correction module uses the error correction code to correct the target data. When error correction fails, the error correction module marks the error correction code area of ​​the target flash memory as unavailable; The error correction module feeds back reinitialization information to the read / write module; The re-initialization information is received through the read / write module; The read / write module reinitializes the EEPROM in response to the reinitialization information. When the error correction is successful, the error-corrected target data is written to the EEPROM through the error correction module to update the target data in the EEPROM; The error correction module feeds back the reread information to the read / write module; The reread information is received through the read / write module; The read / write module responds to the rereading information by re-executing the step of sending the read message to the preset error correction module.

4. The method according to claim 1 or 3, characterized in that, The method further includes: The read / write module receives the second target data fed back by the server host. The second target data is written into the EEPROM through the read / write module; When the second target data is written to the EEPROM, the error correction module detects whether the second target data and the target data are the same. If the data are different, the second error correction code of the second target data is calculated by the error correction module; The error correction module writes the second error correction code into the target flash memory to update the error correction code in the target flash memory.

5. The method according to claim 1, characterized in that, The step of verifying the integrity of the target data using the error correction code through the error correction module includes: The CRC error correction code is used to verify whether each bit of the target data contains an error. When all bits of the target data are verified to be correct, the integrity verification of the target data is deemed to have passed; If at least one bit of the target data is incorrect, the integrity verification of the target data is deemed to have failed.

6. An EEPROM data management device, characterized in that, The device is applied to a BMC and includes: An error correction notification module is used to send a read message to a preset error correction module via a read / write module. Sending the read message to the preset error correction module via the read / write module includes: when the BMC powers on, detecting whether the EEPROM is initialized via the read / write module; when the EEPROM is not initialized, writing default configuration data to the EEPROM via the read / write module and marking the EEPROM as initialized; when the EEPROM is initialized, sending an initialized message to the error correction module via the read / write module, wherein the initialized message serves as the read message. An error correction data acquisition module is configured to receive the read message through the error correction module, and in response to the read message, acquire target data and error correction codes from the EEPROM and the target flash memory respectively; the step of acquiring target data and error correction codes from the EEPROM and the target flash memory in response to the read message includes: when the BMC powers on, detecting whether the error correction code area of ​​the target flash memory is available through the error correction module, wherein the error correction code area is marked as available when the error correction code stored in the target flash memory can correct the target data; when the error correction code area is available, determining whether the initialized message has been received through the error correction module; when the initialized message is received, acquiring target data and error correction codes from the EEPROM and the target flash memory respectively through the error correction module; The verification module is used to verify the integrity of the target data using the error correction code through the error correction module; The normal feedback module is used to send normal data information to the read / write module through the error correction module when the verification is successful. The data reading module is used to receive the data normality information through the read / write module, and in response to the data normality information, read the target data from the EEPROM into the BMC cache.

7. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 5.

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