Striped matrix vector multiplication method and apparatus based on heterogeneous many-core processors

Abstract

The application discloses a strip matrix vector multiplication method and device based on a heterogeneous many-core processor. The method is implemented based on an acceleration domain of the heterogeneous many-core processor. The heterogeneous many-core processor comprises a general-purpose computing domain, a plurality of acceleration domains and a plurality of DDR memories. The general-purpose computing domain comprises a plurality of general-purpose CPU cores. The acceleration domain comprises a plurality of DSP cores and an on-chip global shared memory GSM. The method comprises the following steps: obtaining a strip matrix and a vector which need to be multiplied; performing format conversion on the obtained strip matrix; storing the vector and the format-converted strip matrix in the memory of the heterogeneous many-core processor; and multiplying the strip matrix and the vector in the memory of the heterogeneous many-core processor to obtain a multiplication result. The application solves the problems of limited memory access and low performance of a traditional SpMV for a strip matrix.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing, and specifically to a method and apparatus for strip matrix-vector multiplication based on heterogeneous many-core processors. Background Technology

[0002] Currently, Sparse Matrix Vector Multiplication (SpMV), as a key program in the Basic Linear Algebra Subroutine Library (BLAS), has been widely applied in scientific simulation, data analysis, deep learning, and other fields. Due to the widespread use of SpMV, research on accelerating SpMV in various high-performance architectures, such as multi-core CPUs, GPGPUs, and MICs, is constantly emerging. Sparse matrices typically employ compressed storage formats, with common formats including: Coordinate (COO), Compressed Sparse Row (CSR), ELLPACK, and Sliced ​​ELL (SELL).

[0003] Due to energy efficiency and power limitations, low-power embedded architectures are being introduced into the field of heterogeneous high-performance computing, such as digital signal processors (DSPs). Heterogeneous high-performance processors based on CPU-DSP architectures are gradually being proposed.

[0004] A matrix is ​​called a striped matrix if its non-zero elements are distributed along the main diagonal and its adjacent diagonals. Striped matrices are a common matrix type with wide applications. Many existing sparse matrices can be transformed into striped matrices using Reverse Cuthill McKee (RCM) sorting. Therefore, accelerating striped matrix vector multiplication operations on striped matrices by fully utilizing the special architecture of DSPs is a key research focus. Existing SpMV computation methods are not suitable for accelerating striped matrices because the non-zero element distribution of striped matrices is usually irregular, and traditional SpMV computation methods often result in significant memory access latency and overhead. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and apparatus for strip matrix vector multiplication based on heterogeneous many-core processors, thereby solving the problem of large computational overhead in existing strip matrix vector multiplication.

[0006] To address the aforementioned technical problems, a first aspect of this invention discloses a striped matrix-vector multiplication method based on a heterogeneous many-core processor. The method is implemented within an acceleration domain of the heterogeneous many-core processor, which includes a general-purpose computing domain, several acceleration domains, and several DDR memory units. The general-purpose computing domain includes several general-purpose CPU cores, and the acceleration domain includes several DSP cores and an on-chip global shared memory (GSM). Each DSP core includes a control core, an AM memory unit, and several acceleration cores. The DDR memory, GSM, and AM memory support DMA data transfer among themselves. The method includes:

[0007] S1, obtain the strip matrix and vector that need to be multiplied;

[0008] S2, convert the format of the obtained strip matrix, and store the vector and the converted strip matrix into the memory of the heterogeneous many-core processor;

[0009] S3, perform multiplication operations on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result.

[0010] The step of converting the acquired striped matrix and vector to a new format and storing the converted striped matrix and vector into the memory of the heterogeneous many-core processor includes:

[0011] S21, convert the obtained strip matrix into a SELL format strip matrix A to obtain the corresponding SELL format strip matrix A information;

[0012] S22, store the vector and the SELL format strip matrix A information into the DDR memory of the heterogeneous many-core processor; the SELL format strip matrix A information includes the non-zero element values, non-zero element column indices, and basic row block information of the strip matrix; the strip matrix A has a dimension of m×n; the vector X has a dimension of n; the SELL format strip matrix A includes several basic row blocks; the basic row block information includes non-zero element values, non-zero element column indices, and row block indices.

[0013] The step of performing a multiplication operation on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result includes:

[0014] S31, determine the number of row blocks N1 of the strip matrix; divide the strip matrix A and vector X to obtain a set of matrix row blocks and a set of vector segments; the set of matrix row blocks includes N1 row blocks and their corresponding row block numbers; the set of vector segments includes N1 vector segments and their corresponding segment numbers.

[0015] S32, initialize the current computation row block number i = 1;

[0016] S33, determine the row block with sequence number i as the current computation row block; use the DMA point-to-point transfer method to load the current computation row block and the corresponding vector X fragment from the DDR memory of the heterogeneous many-core processor into the on-chip global shared memory GSM of the acceleration domain;

[0017] S34, determine the number of DSP cores coreNUM contained in the acceleration domain, which is the matrix row block number coreNUM1; according to the matrix row block number coreNUM1, divide the current calculation row block evenly into coreNUM1 sub-row blocks in the row direction, and assign each sub-row block to each DSP core for parallel processing in sequence; determine the number of basic row blocks beta contained in the sub-row block.

[0018] S35, each DSP core loads the elements of the segment of vector X corresponding to the non-zero column index of the basic row block of the processed sub-row block from the on-chip global shared memory (GSM) to the AM memory of the DSP core.

[0019] S36. For each DSP core, using the DMA point-to-point transfer method, the non-zero element values ​​of the basic row blocks of the sub-row blocks it processes are loaded from the on-chip global shared memory (GSM) to the AM memory of the DSP core.

[0020] S37, each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block;

[0021] S38, after all DSP cores have calculated the first operation result of the corresponding sub-row block, the first operation results of all sub-row blocks are merged to obtain the second operation result of the current calculation row block;

[0022] Determine whether the second operation results of all row blocks have been obtained. If the second operation results of all row blocks have been obtained, execute S39. If the second operation results of all row blocks have not been obtained, increment the current calculation row block number i by 1 and execute S33.

[0023] S39: Load the second operation result of each row block into the DDR memory of the corresponding DSP core, merge the second operation results of all row blocks, and obtain the multiplication result.

[0024] Determining the number of row blocks N1 in the striped matrix includes:

[0025] S311, calculate the maximum value of the number of rows in the row block of the striped matrix, blockLenMax; the expression for calculating blockLenMax is:

[0026] blockLenMax=GSMlenMax-SBL-SBU,

[0027] Wherein, GSMlenMax is the storage space of the on-chip global shared memory GSM, SBL refers to the row number of all non-zero elements below the main diagonal of the strip matrix, the maximum value of the offset from the row number of the corresponding diagonal element in the same column, that is, the lower bandwidth of the strip matrix, and SBU refers to the column number of all non-zero elements above the main diagonal of the strip matrix, the maximum distance of the offset from the column number of the diagonal element in the same row of the main diagonal, that is, the upper bandwidth of the strip matrix.

[0028] S312, calculate the number of rows (blockLen) and the number of rows (N1) of the striped matrix. The calculation expression is as follows:

[0029] num = m / blockLenMax,

[0030] blockLen = (n + num) / (num + 1),

[0031] N1 = m / blockLen,

[0032] Where num is the first computational scalar, blockLen is the size of the row block of the strip matrix, and N1 is the number of row blocks into which the strip matrix is ​​divided;

[0033] S313, divide the strip matrix A evenly along the row direction to obtain N1 row blocks;

[0034] S314, using the column index value of the non-zero element of each row block, perform an extraction operation on the element with the corresponding index in vector X to obtain the segment of vector X corresponding to the row block;

[0035] S315, calculate the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block;

[0036] S316, Based on the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block, determine the storage space required for the segment of vector X corresponding to each row block.

[0037] The maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block are calculated using the following expressions:

[0038] X_Start = StartRow – SBL,

[0039] X_End = EndRow + SBU,

[0040] Where X_End and X_Start represent the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block, respectively, and StartRow and EndRow refer to the starting and ending row indexes of the elements in the row block, with StartRow = (i-1)*blockLen+1 and EndRow = StartRow+blockLen.

[0041] The determination of the number of basic row blocks beta contained in the sub-row block includes: the calculation expression for the number of basic row blocks beta is:

[0042] beta=blockLen / (Srow*coreNUM1),

[0043] Here, Srow represents the row dimension of the basic row block.

[0044] Each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block, including:

[0045] Each DSP, in its AM memory, performs multiplication and accumulation operations on the non-zero element value of each basic row block of its allocated sub-row block and the elements of the segment of vector X corresponding to the non-zero element column index of the basic row block to obtain the calculation result of the basic row block.

[0046] The calculation results of each basic row block of the allocated sub-row block are merged to obtain the first operation result Y of the sub-row block; the first operation result Y is expressed as [Y1,Y2,…,Ybeta], where Y1 represents the calculation result of the first basic row block of the sub-row block, and so on, and Ybeta represents the calculation result of the beta basic row block of the sub-row block.

[0047] In a second aspect of this embodiment, a strip matrix-vector multiplication device based on a heterogeneous many-core processor is disclosed, the device comprising:

[0048] Memory containing executable program code;

[0049] A processor coupled to the memory;

[0050] The processor calls the executable program code stored in the memory to execute the strip matrix-vector multiplication method based on heterogeneous many-core processors.

[0051] In a third aspect of this embodiment, a computer-storable medium is disclosed, wherein the computer storage medium stores computer instructions, and when the computer instructions are invoked, they are used to execute the strip matrix-vector multiplication method based on a heterogeneous many-core processor.

[0052] In a fourth aspect of this embodiment, an information data processing terminal is disclosed, which is used to implement the strip matrix-vector multiplication method based on heterogeneous many-core processors.

[0053] The beneficial effects of this invention are as follows:

[0054] The purpose of this invention is to design and develop efficient SpMV operations for striped matrices on heterogeneous many-core processors. Leveraging the CPU-DSP heterogeneous high-performance platform of heterogeneous many-core processors, it aims to efficiently execute SpMV operations for striped matrices and solve the following technical problems:

[0055] 1) Leveraging the rich multi-level memory architecture of heterogeneous many-core processors, this addresses the limitations of memory access and low performance inherent in traditional SpMV operations for striped matrices. In striped matrix vector multiplication, the overhead of accessing vector X is typically much greater than the overhead of accessing matrix attribute values; by using on-chip high-speed memory GSM to cache vector X, the latency of irregular memory accesses in striped matrix vector multiplication can be effectively reduced.

[0056] 2) By utilizing multiple DSP cores of a heterogeneous many-core processor, efficient parallelization of SpMV operations can be achieved. Through multi-threaded parallel execution, the degree of parallelism can be improved, thereby effectively enhancing computing performance. Attached Figure Description

[0057] Figure 1 This is a flowchart illustrating the implementation of the method of the present invention;

[0058] Figure 2 This is a schematic diagram illustrating the implementation principle of the present invention based on the MT-3000 heterogeneous many-core processor.

[0059] Figure 3 This is a schematic diagram of the partitioning of the strip matrix A according to the present invention. Detailed Implementation

[0060] To better understand the content of this invention, two embodiments are provided here.

[0061] Figure 1 This is a flowchart illustrating the implementation of the method of the present invention; Figure 2 This is a schematic diagram illustrating the implementation principle of the present invention based on the MT-3000 heterogeneous many-core processor. Figure 3 This is a schematic diagram of the partitioning of the strip matrix A according to the present invention. Figure 2 In this context, SM and SVR represent scalar storage space and scalar vector register, respectively; dma_sg represents the DMA segmented data transfer method; and dma_p2p represents the DMA point-to-point transfer method.

[0062] The heterogeneous many-core processor, which may be the MT-3000 heterogeneous many-core processor, has one general-purpose computing cluster domain and four acceleration cluster domains. The general-purpose computing domain has 16 general-purpose CPU cores, and the four acceleration domains have a total of 96 control cores and 1536 accelerator cores. Operating at 1.2 GHz, it achieves 11.6 TFLOPS double-precision performance and 45.4 GFLOPS / W power efficiency. The control cores and acceleration cores form the acceleration cluster domain, which is evenly divided into four acceleration clusters. Each cluster consists of 24 DSP cores, totaling 24 control cores, 384 acceleration cores, and 6 MB of on-chip global shared memory (GSM). Every 16 acceleration cores share 768 KB of AM (Array Memory) memory. GSM, AM, and DDR memory support efficient DMA data transfer. Simultaneously, the MT-3000 processor provides efficient indirect addressing SuperGather instructions, which can be directly applied to SpMV calculations. Since the non-zero elements of the strip matrix have a concentrated distribution, specific storage and computation methods can be used to improve the efficiency of SpMV operations based on the MT-3000 processor architecture.

[0063] Example 1:

[0064] This embodiment discloses a striped matrix-vector multiplication method based on a heterogeneous many-core processor. The method is implemented based on an acceleration domain of the heterogeneous many-core processor. The heterogeneous many-core processor includes a general-purpose computing domain, several acceleration domains, and several DDR memories. The general-purpose computing domain includes several general-purpose CPU cores. The acceleration domain includes several DSP cores and an on-chip global shared memory (GSM). Each DSP core includes a control core, an AM memory, and several acceleration cores. The DDR memory, GSM, and AM memory support DMA data transfer among themselves. The method includes:

[0065] S1, obtain the strip matrix and vector that need to be multiplied;

[0066] S2, convert the format of the obtained strip matrix, and store the vector and the converted strip matrix into the memory of the heterogeneous many-core processor;

[0067] S3, perform multiplication operations on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result.

[0068] The step of converting the acquired striped matrix and vector to a new format and storing the converted striped matrix and vector into the memory of the heterogeneous many-core processor includes:

[0069] S21, convert the obtained strip matrix into a SELL format strip matrix A to obtain the corresponding SELL format strip matrix A information;

[0070] S22, store the vector and the SELL format strip matrix A information into the DDR memory of the heterogeneous many-core processor; the SELL format strip matrix A information includes the non-zero element values, non-zero element column indices, and basic row block information of the strip matrix; the strip matrix A has a dimension of m×n; the vector X has a dimension of n; the SELL format strip matrix A includes several basic row blocks; the basic row block information includes non-zero element values, non-zero element column indices, and row block indices.

[0071] The step of performing a multiplication operation on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result includes:

[0072] S31, determine the number of row blocks N1 of the strip matrix; divide the strip matrix A and vector X to obtain a set of matrix row blocks and a set of vector segments; the set of matrix row blocks includes N1 row blocks and their corresponding row block numbers; the set of vector segments includes N1 vector segments and their corresponding segment numbers.

[0073] S32, initialize the current computation row block number i = 1;

[0074] S33, determine the row block with sequence number i as the current computation row block; use the DMA point-to-point transfer method to load the current computation row block and the corresponding vector X fragment from the DDR memory of the heterogeneous many-core processor into the on-chip global shared memory GSM of the acceleration domain;

[0075] S34, determine the number of DSP cores coreNUM contained in the acceleration domain, which is the matrix row block number coreNUM1; according to the matrix row block number coreNUM1, divide the current calculation row block evenly into coreNUM1 sub-row blocks in the row direction, and assign each sub-row block to each DSP core for parallel processing in sequence; determine the number of basic row blocks beta contained in the sub-row block; the coreNUM1 satisfies that coreNUM1 = coreNUM;

[0076] S35, each DSP core loads the elements of the segment of vector X corresponding to the non-zero column index of the basic row block of the processed sub-row block from the on-chip global shared memory (GSM) to the AM memory of the DSP core.

[0077] Each DSP core loads the elements of the vector X segment corresponding to the non-zero column index of the basic row block of the processed sub-row block from the on-chip global shared memory (GSM) to the AM memory of the DSP core. The loading can be achieved using the DMA segmented data transfer method.

[0078] S36. For each DSP core, using the DMA point-to-point transfer method, the non-zero element values ​​of the basic row blocks of the sub-row blocks it processes are loaded from the on-chip global shared memory (GSM) to the AM memory of the DSP core.

[0079] S37, each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block;

[0080] The S37 includes:

[0081] Each DSP, in its AM memory, performs multiplication and accumulation operations on the non-zero element value of each basic row block of its allocated sub-row block and the elements of the segment of vector X corresponding to the non-zero element column index of the basic row block to obtain the calculation result of the basic row block.

[0082] The calculation results of each basic row block of the allocated sub-row block are merged to obtain the first operation result Y of the sub-row block; the first operation result Y is expressed as [Y1,Y2,…,Ybeta], where Y1 represents the calculation result of the first basic row block of the sub-row block, and so on, and Ybeta represents the calculation result of the beta basic row block of the sub-row block.

[0083] The multiplication and accumulation operations involve multiplying each non-zero element value of the basic row block with the element of the corresponding segment of vector X, and then accumulating the results of the multiplication of each non-zero element value to obtain the accumulated result.

[0084] S38, after all DSP cores have calculated the first operation result of the corresponding sub-row block, the first operation results of all sub-row blocks are merged to obtain the second operation result of the current calculation row block; the merging process is to concatenate all vectors according to the row direction to obtain the concatenated vector, which is used as the second operation result of the current calculation row block;

[0085] Determine whether the second operation results of all row blocks have been obtained. If the second operation results of all row blocks have been obtained, execute S39. If the second operation results of all row blocks have not been obtained, increment the current calculation row block number i by 1 and execute S33.

[0086] S39, the second operation result of each row block is loaded into the DDR memory of the corresponding DSP core, and the second operation results of all row blocks are merged to obtain the multiplication result. The merging process involves concatenating the vectors corresponding to all operation results together in the row direction to obtain the result vector, which is the multiplication result.

[0087] The memory of the heterogeneous many-core processor can be DDR memory.

[0088] Determining the number of row blocks N1 in the striped matrix includes:

[0089] S311, calculate the maximum value of the number of rows in the row block of the striped matrix, blockLenMax; the expression for calculating blockLenMax is:

[0090] blockLenMax=GSMlenMax-SBL-SBU,

[0091] Wherein, GSMlenMax is the storage space of the on-chip global shared memory GSM, SBL refers to the row number of all non-zero elements below the main diagonal of the strip matrix, the maximum value of the offset from the row number of the corresponding diagonal element in the same column, that is, the lower bandwidth of the strip matrix, and SBU refers to the column number of all non-zero elements above the main diagonal of the strip matrix, the maximum distance of the offset from the column number of the diagonal element in the same row of the main diagonal, that is, the upper bandwidth of the strip matrix.

[0092] S312, calculate the number of rows (blockLen) and the number of rows (N1) of the striped matrix. The calculation expression is as follows:

[0093] num = m / blockLenMax,

[0094] blockLen = (n + num) / (num + 1),

[0095] N1 = m / blockLen,

[0096] Where num is the first computational scalar. For num, if it cannot be divided equally, the computation result is taken up. Where blockLen is the size of the row block of the strip matrix, and N1 is the number of row blocks into which the strip matrix is ​​divided.

[0097] S313, divide the strip matrix A evenly along the row direction to obtain N1 row blocks;

[0098] S314, using the column index value of the non-zero element of each row block, perform an extraction operation on the element with the corresponding index in vector X to obtain the segment of vector X corresponding to the row block;

[0099] S315, calculate the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block;

[0100] S316. Based on the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block, determine the storage space required for the segment of vector X corresponding to each row block.

[0101] The maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block are calculated using the following expressions:

[0102] X_Start = StartRow – SBL,

[0103] X_End = EndRow + SBU,

[0104] Where X_End and X_Start represent the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block, respectively, and StartRow and EndRow refer to the starting and ending row indexes of the elements in the row block, with StartRow = (i-1)*blockLen+1 and EndRow = StartRow+blockLen.

[0105] The determination of the number of basic row blocks beta contained in the sub-row block includes: the calculation expression for the number of basic row blocks beta is:

[0106] beta=blockLen / (Srow*coreNUM1),

[0107] Here, Srow represents the row dimension of the basic row block.

[0108] Each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block, including:

[0109] Each DSP, in its AM memory, performs multiplication and accumulation operations on the non-zero element value of each basic row block of its allocated sub-row block and the elements of the segment of vector X corresponding to the non-zero element column index of the basic row block to obtain the calculation result of the basic row block.

[0110] The calculation results of each basic row block of the allocated sub-row block are merged to obtain the first operation result Y of the sub-row block; the first operation result Y is expressed as [Y1,Y2,…,Ybeta], where Y1 represents the calculation result of the first basic row block of the sub-row block, and so on, and Ybeta represents the calculation result of the beta basic row block of the sub-row block.

[0111] Furthermore, the matrix attribute values ​​loaded into DDR memory as described in S2 include, but are not limited to, non-zero element values, column indices, etc., and should be determined according to the matrix storage format.

[0112] Furthermore, in S2, the matrix is ​​divided horizontally along the row direction. Since the elements of the strip matrix are centrally distributed, when the vector X exceeds the GSM range, the matrix is ​​divided into multiple row blocks, and the vector fragments corresponding to each row block can be moved to the GSM.

[0113] A second aspect of this invention discloses a strip matrix-vector multiplication device based on a heterogeneous many-core processor, the device comprising:

[0114] Memory containing executable program code;

[0115] A processor coupled to the memory;

[0116] The processor calls the executable program code stored in the memory to execute the strip matrix-vector multiplication method based on heterogeneous many-core processors.

[0117] A third aspect of the present invention discloses a computer-storable medium storing computer instructions, which, when invoked, are used to execute the strip matrix-vector multiplication method based on a heterogeneous many-core processor.

[0118] The fourth aspect of this invention discloses an information data processing terminal, which is used to implement the strip matrix-vector multiplication method based on heterogeneous many-core processors.

[0119] Example 2:

[0120] This embodiment discloses a striped matrix-vector multiplication method based on a heterogeneous many-core processor. The method is implemented based on an acceleration domain of the heterogeneous many-core processor. The heterogeneous many-core processor includes a general-purpose computing domain, several acceleration domains, and several DDR memories. The general-purpose computing domain includes several general-purpose CPU cores. The acceleration domain includes several DSP cores and an on-chip global shared memory (GSM). Each DSP core includes a control core, an AM memory, and several acceleration cores. The DDR memory, GSM, and AM memory support DMA data transfer among themselves. The method includes:

[0121] S1, obtain the strip matrix and vector that need to be multiplied;

[0122] S2, convert the obtained strip matrix and vector to a new format, and store the converted strip matrix and vector into the memory of the heterogeneous many-core processor;

[0123] S3, perform multiplication operations on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result.

[0124] The step of converting the acquired striped matrix and vector to a new format and storing the converted striped matrix and vector into the memory of the heterogeneous many-core processor includes:

[0125] S21, convert the obtained strip matrix and vector into SELL format strip matrix A and SELL format vector X to obtain the corresponding SELL format strip matrix A information and SELL format vector X information.

[0126] S22, the SELL format strip matrix A information and the SELL format vector X information are stored in the DDR memory of the heterogeneous many-core processor; the SELL format strip matrix A information includes the non-zero element values, non-zero element column indices, and basic row block information of the strip matrix; the strip matrix A has a dimension of m×n; the vector X has a dimension of n; the SELL format strip matrix A includes several basic row blocks; the basic row block information includes non-zero element values, non-zero element column indices, and row block indices.

[0127] The step of performing a multiplication operation on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result includes:

[0128] S31, determine the number of row blocks N1 of the strip matrix; divide the strip matrix A and vector X to obtain a set of matrix row blocks and a set of vector segments; the set of matrix row blocks includes N1 row blocks and their corresponding row block numbers; the set of vector segments includes N1 vector segments and their corresponding segment numbers.

[0129] S32, initialize the current computation row block number i1 = 1;

[0130] S33, determine the row block with sequence number i1 as the computation row block; use the DMA point-to-point transfer method to load the computation row block and the corresponding vector X fragment from the DDR memory of the heterogeneous many-core processor into the on-chip global shared memory (GSM) of the acceleration domain;

[0131] S34. Determine the matrix row block number be based on the storage space value of the AM memory of the DSP core in the acceleration domain and the number of DSP cores contained in the acceleration domain; based on the matrix row block number be, divide the calculation row block evenly into multiple sub-row blocks in the row direction, and assign each sub-row block to each DSP core for parallel processing in sequence.

[0132] S35, each DSP core loads the elements of the segment of vector X corresponding to the non-zero column index of the basic row block of the processed sub-row block from the on-chip global shared memory (GSM) to the AM memory of the DSP core.

[0133] Each DSP core loads the elements of the vector X segment corresponding to the non-zero column index of the basic row block of the processed sub-row block from the on-chip global shared memory (GSM) to the AM memory of the DSP core. The loading can be achieved using the DMA segmented data transfer method.

[0134] S36. For each DSP core, using the DMA point-to-point transfer method, the non-zero element values ​​of the basic row blocks of the sub-row blocks it processes are loaded from the on-chip global shared memory (GSM) to the AM memory of the DSP core.

[0135] S37, each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block;

[0136] The S37 includes:

[0137] Each DSP, in its AM memory, performs multiplication and accumulation operations on the non-zero element value of each basic row block of its allocated sub-row block and the elements of the segment of vector X corresponding to the non-zero element column index of the basic row block to obtain the calculation result of the basic row block.

[0138] The calculation results of each basic row block of the allocated sub-row block are merged to obtain the first operation result Y of the sub-row block; the first operation result Y is expressed as [Y1,Y2,…,Ybeta], where Y1 represents the calculation result of the first basic row block of the sub-row block, and so on, and Ybeta represents the calculation result of the beta basic row block of the sub-row block.

[0139] The multiplication and accumulation operations involve multiplying each non-zero element value of the basic row block with the element of the corresponding segment of vector X, and then accumulating the results of the multiplication of each non-zero element value to obtain the accumulated result.

[0140] S38, after all DSP cores have calculated the first operation result of the corresponding sub-row block, the first operation results of all sub-row blocks are merged to obtain the second operation result of the calculated row block;

[0141] Determine whether the second operation results of all row blocks have been obtained. If the second operation results of all row blocks have been obtained, execute S39. If the second operation results of all row blocks have not been obtained, increment the current calculation row block number i1 by 1 and execute S33.

[0142] S39: Load the second operation result of each row block into the DDR memory of the corresponding DSP core, merge the second operation results of all row blocks, and obtain the multiplication result.

[0143] Determining the number of row blocks N1 in the striped matrix includes:

[0144] S311, Set the range of the number of row blocks in the strip matrix [P1,P2];

[0145] S312, initialize the current row block count value N10 to P1;

[0146] S313, divide the strip matrix A evenly along the row direction to obtain N10 row blocks;

[0147] S314, using the column index value of the non-zero element of each row block, perform an extraction operation on the element with the corresponding index in vector X to obtain the segment of vector X corresponding to the row block;

[0148] S315, calculate the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block;

[0149] S316, Based on the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block, determine the storage space required for the segment of vector X corresponding to each row block;

[0150] S317, For each row block, determine whether the storage space required for the segment of vector X corresponding to the row block is less than or equal to the GSM storage space of the acceleration domain;

[0151] S318, when the storage space required by the segments of vector X corresponding to all row blocks is less than or equal to the GSM storage space of the acceleration domain, determine the number of row blocks N1 of the strip matrix as the current number of row blocks N10; when there is a row block corresponding to the segment of vector X that requires more storage space than the GSM storage space of the acceleration domain, increment the current number of row blocks N10 by 1, and execute S313.

[0152] The maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block are calculated using the following expressions:

[0153] X_Start = StartRow – SBL,

[0154] X_End = EndRow + SBU,

[0155] Where X_End and X_Start represent the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block, respectively; SBL refers to the column index of all non-zero elements below the diagonal of the strip matrix A, and the maximum value of the column index of the diagonal element of the corresponding row; SBU refers to the column index of all non-zero elements above the diagonal of the strip matrix A, and the maximum value of the column index of the diagonal element of the corresponding row; StartRow and EndRow refer to the starting and ending row indexes of the elements in the row block, respectively, with StartRow = (i-1)m / N1+1 and EndRow = im / N1+1, where i represents the index of the row block.

[0156] The step of determining the matrix row block number be based on the storage space value of the AM memory of the DSP cores in the acceleration domain and the number of DSP cores contained in the acceleration domain includes:

[0157] The expression for calculating the matrix row block number beta is:

[0158] blockLenMax=GSMlenMax-SBL-SBU,

[0159] num = m / blockLenMax,

[0160] blockLen = (n + num) / (num + 1),

[0161] beta=blockLen / Srow*coreNUM,

[0162] be = m / N1 * beta * Srow,

[0163] Wherein, GSMlenMax is the storage space of the on-chip global shared memory GSM, blockLenMax is the first intermediate calculation variable, num is the second intermediate calculation variable, coreNU is the number of DSP cores in an acceleration domain, Srow represents the row dimension of the basic row block, and beta is the number of basic row blocks contained in the sub-row block.

[0164] Each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block, including:

[0165] Each DSP, in its AM memory, performs multiplication and accumulation operations on the non-zero element value of each basic row block of its allocated sub-row block and the elements of the segment of vector X corresponding to the non-zero element column index of the basic row block to obtain the calculation result of the basic row block.

[0166] The calculation results of each basic row block of the allocated sub-row block are merged to obtain the first operation result Y of the sub-row block; the first operation result Y is expressed as [Y1,Y2,…,Ybeta], where Y1 represents the calculation result of the first basic row block of the sub-row block, and so on, and Ybeta represents the calculation result of the beta basic row block of the sub-row block.

[0167] Furthermore, the matrix attribute values ​​loaded into DDR memory as described in S2 include, but are not limited to, non-zero element values, column indices, etc., and should be determined according to the matrix storage format.

[0168] Furthermore, in S2, the matrix is ​​divided horizontally along the row direction. Since the elements of the strip matrix are centrally distributed, when the vector X exceeds the GSM range, the matrix is ​​divided into multiple row blocks, and the vector fragments corresponding to each row block can be moved to the GSM.

[0169] This embodiment discloses a strip matrix-vector multiplication device based on a heterogeneous many-core processor, the device comprising:

[0170] Memory containing executable program code;

[0171] A processor coupled to the memory;

[0172] The processor calls the executable program code stored in the memory to execute the strip matrix-vector multiplication method based on heterogeneous many-core processors.

[0173] This embodiment discloses a computer-storable medium storing computer instructions. When the computer instructions are invoked, they are used to execute the strip matrix-vector multiplication method based on a heterogeneous many-core processor.

[0174] This embodiment discloses an information data processing terminal, which is used to implement the strip matrix-vector multiplication method based on heterogeneous many-core processors.

[0175] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for strip matrix-vector multiplication based on heterogeneous many-core processors, characterized in that, The method is implemented based on an acceleration domain of a heterogeneous many-core processor; the heterogeneous many-core processor includes a general-purpose computing domain, several acceleration domains and several DDR memory; the general-purpose computing domain includes several general-purpose CPU cores, the acceleration domain includes several DSP cores and on-chip global shared memory (GSM), and the DSP core includes a control core, an AM memory and several acceleration cores. The DDR memory, GSM memory, and AM memory support DMA data transfer among themselves; the method includes: S1, obtain the strip matrix and vector X that need to be multiplied; S2, convert the obtained strip matrix into a SELL format strip matrix A, and store the vector X and the converted strip matrix A into the memory of the heterogeneous many-core processor; S3, perform a multiplication operation on the strip matrix A and vector X in the memory of the heterogeneous many-core processor to obtain the multiplication result, including: S31, determine the number of row blocks N1 of the strip matrix; divide the strip matrix A and vector X to obtain a set of matrix row blocks and a set of vector segments; the set of matrix row blocks includes N1 row blocks and their corresponding row block numbers; the set of vector segments includes N1 vector segments and their corresponding segment numbers. S32, initialize the current computation row block number i=1; S33, determine the row block with sequence number i as the current computation row block; use the DMA point-to-point transfer method to load the current computation row block and the corresponding vector X fragment from the DDR memory of the heterogeneous many-core processor into the on-chip global shared memory GSM of the acceleration domain; S34, determine the number of DSP cores coreNUM contained in the acceleration domain, which is the matrix row block number coreNUM1; according to the matrix row block number coreNUM1, divide the current calculation row block evenly into coreNUM1 sub-row blocks in the row direction, and assign each sub-row block to each DSP core for parallel processing in sequence; determine the number of basic row blocks beta contained in the sub-row block. S35, each DSP core loads the elements of the segment of vector X corresponding to the non-zero column index of the basic row block of the processed sub-row block from the on-chip global shared memory (GSM) to the AM memory of the DSP core. S36, for each DSP core, using the DMA point-to-point transfer method, the non-zero element values ​​of the basic row blocks of the sub-row blocks it processes are loaded from the on-chip global shared memory (GSM) to the AM memory of the DSP core; S37, each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block.

2. The strip matrix-vector multiplication method based on heterogeneous many-core processors as described in claim 1, characterized in that, The step of converting the acquired strip matrix into a SELL format strip matrix A, and storing the vector X and the converted strip matrix A into the memory of the heterogeneous many-core processor includes: S21, convert the obtained strip matrix into a SELL format strip matrix A to obtain the corresponding SELL format strip matrix A information; S22, store the vector and the SELL format striped matrix A information into the DDR memory of the heterogeneous many-core processor; the SELL format striped matrix A information includes the non-zero element values, non-zero element column indices, and basic row block information of the striped matrix; the striped matrix A has a dimension of... The vector X has the following dimensions: The SELL format strip matrix A includes several basic row blocks; the basic row block information includes non-zero element values, non-zero element column indices, and row block indices.

3. The strip matrix-vector multiplication method based on heterogeneous many-core processors as described in claim 2, characterized in that, The step of performing a multiplication operation on the strip matrix and vector in the memory of the heterogeneous many-core processor to obtain the multiplication result also includes: S38, after all DSP cores have calculated the first operation result of the corresponding sub-row block, the first operation results of all sub-row blocks are merged to obtain the second operation result of the current calculation row block; Determine whether the second operation results of all row blocks have been obtained. If the second operation results of all row blocks have been obtained, execute S39. If the second operation results of all row blocks have not been obtained, increment the current calculation row block number i by 1 and execute S33. S39: Load the second operation result of each row block into the DDR memory of the corresponding DSP core, merge the second operation results of all row blocks, and obtain the multiplication result.

4. The strip matrix-vector multiplication method based on heterogeneous many-core processors as described in claim 3, characterized in that, Determining the number of row blocks N1 in the striped matrix includes: S311, calculate the maximum number of rows in the row block of the striped matrix, blockLenMax; the expression for calculating blockLenMax is: blockLenMax = GSMlenMax - SBL - SBU, Wherein, GSMlenMax is the storage space of the on-chip global shared memory GSM, SBL refers to the row number of all non-zero elements below the main diagonal of the strip matrix, the maximum value of the offset from the row number of the corresponding diagonal element in the same column, that is, the lower bandwidth of the strip matrix, and SBU refers to the column number of all non-zero elements above the main diagonal of the strip matrix, the maximum distance of the offset from the column number of the diagonal element in the same row of the main diagonal, that is, the upper bandwidth of the strip matrix. S312, calculate the number of rows (blockLen) and the number of rows (N1) of the striped matrix. The calculation expression is as follows: num = m / blockLenMax, blockLen = (n+ num) / ( num +1), N1 = m / blockLen, Where num is the first computational scalar, blockLen is the size of the row block of the strip matrix, and N1 is the number of row blocks into which the strip matrix is ​​divided. S313, divide the strip matrix A evenly along the row direction to obtain N1 row blocks; S314, using the column index value of the non-zero element of each row block, perform an extraction operation on the element with the corresponding index in vector X to obtain the segment of vector X corresponding to the row block; S315, calculate the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block; S316. Based on the maximum and minimum index values ​​of the elements in the segment of vector X corresponding to each row block, determine the storage space required for the segment of vector X corresponding to each row block.

5. The strip matrix-vector multiplication method based on heterogeneous many-core processors as described in claim 4, characterized in that, The maximum and minimum index values ​​of the elements in the segment of vector X corresponding to the row block are calculated using the following expressions: X_Start = StartRow–SBL, X_End = EndRow + SBU, Where X_End and X_Start represent the maximum and minimum index values ​​of elements in the segment of vector X corresponding to the row block, respectively, and StartRow and EndRow refer to the starting and ending row indices of the elements in the row block. , EndRow= StartRow + blockLen.

6. The strip matrix-vector multiplication method based on heterogeneous many-core processors as described in claim 3, characterized in that, The determination of the number of basic row blocks beta contained in the sub-row block includes: the calculation expression for the number of basic row blocks beta is: beta=blockLen / ( ) Here, Srow represents the row dimension of the basic row block.

7. The method for strip matrix-vector multiplication based on heterogeneous many-core processors as described in claim 3, characterized in that, Each DSP core performs a vector multiplication operation on its allocated sub-row block and the fragment value of the corresponding vector X in its AM memory to obtain the first operation result Y of the sub-row block, including: Each DSP, in its AM memory, performs multiplication and accumulation operations on the non-zero element value of each basic row block of its allocated sub-row block and the elements of the segment of vector X corresponding to the non-zero element column index of the basic row block to obtain the calculation result of the basic row block. The calculation results of each basic row block of the allocated sub-row block are merged to obtain the first operation result Y of the sub-row block; the first operation result Y is expressed as [Y1, Y2, …,Ybeta], where Y1 represents the calculation result of the first basic row block of the sub-row block, and so on, and Ybeta represents the calculation result of the beta basic row block of the sub-row block.

8. A strip matrix-vector multiplication device based on a heterogeneous many-core processor, characterized in that, The device includes: Memory containing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the strip matrix-vector multiplication method based on a heterogeneous many-core processor as described in any one of claims 1 to 7.

9. A computer-storable medium, characterized in that, The computer storage medium stores computer instructions, which, when invoked, are used to execute the strip matrix-vector multiplication method based on a heterogeneous many-core processor as described in any one of claims 1 to 7.

10. An information data processing terminal, characterized in that, The information data processing terminal is used to implement the strip matrix-vector multiplication method based on heterogeneous many-core processors as described in any one of claims 1 to 7.

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