A system and method for detecting server board power-on anomalies

Abstract

This invention relates to the field of server anomaly detection technology, and discloses a detection system and method for server board power-on anomalies. The system includes at least one power management chip, a complex programmable logic device (CPL), a baseboard management controller (BMD), and a pin header interface. The CPL is connected to the at least one power management chip, the BMD, and the pin header interface, respectively. The pin header interface is connected to an external detection device. The CPL receives power supply signals from the power management chip and status detection signals from the BMD, stores the power supply signals to generate register information, and when the status detection signal is an abnormal status signal, cyclically transmits the register information to the pin header interface using a unipolar return-to-zero code. The pin header interface receives the register information and transmits it to the external detection device. This invention enables rapid localization of server board power-on anomalies.

Description

Technical Field

[0001] This invention relates to the field of server anomaly detection technology, specifically to a detection system and method for server board power-on anomalies. Background Technology

[0002] Currently, the server industry faces challenges such as difficulty in controlling R&D costs and difficulty in locating complex server product faults. In particular, it is difficult to capture detailed information about abnormal situations when a server fails to boot up. Even worse, when out-of-band management systems, such as the BMC (Baseboard Management Controller, used for managing server motherboards), also fail to function properly, handling abnormal issues becomes even more challenging.

[0003] However, the relevant server anomaly detection methods are inefficient and risky in locating power-on anomalies, and cannot guarantee the normal working environment after power-on. Summary of the Invention

[0004] In view of this, the present invention provides a detection system and method for server board power-on abnormalities, so as to solve the problems of low efficiency and risk in locating server power-on abnormalities.

[0005] In a first aspect, the present invention provides a detection system for abnormal power-on of a server board. The system includes: at least one power management chip, a complex programmable logic device (FPGA), a baseboard management controller, and a pin header interface. The FPGA is connected to the at least one power management chip, the baseboard management controller, and the pin header interface, respectively. The pin header interface is connected to an external detection device.

[0006] Complex programmable logic devices are used to receive power supply signals sent by power management chips and status detection signals sent by baseboard management controllers. They store the power supply signals, generate register information, and when the status detection signal is an abnormal status signal, they cyclically transmit the register information to the pin header interface through a specific unipolar return-to-zero code.

[0007] The pin header interface is used to receive register information and transmit it to external testing equipment, so that the external testing equipment can generate power-on anomaly detection results for the server board.

[0008] This invention provides a detection system for power-on anomalies on server boards. It cyclically transmits register information to a pin header interface using a specific unipolar return-to-zero code, and reads the register information from complex programmable logic devices through the pin header interface to determine the location of the power-on anomaly. This solves the problems of low efficiency and risk in locating power-on anomalies, reduces data transmission risks, and ensures that the server is not at risk due to exposed pins by placing the pin header interface on the server board. It also avoids the short-circuit risk caused by measuring the power supply signals of power management chips one by one with a multimeter, thus reducing the risks during power-on anomaly detection and improving the detection efficiency of power-on anomalies on server boards.

[0009] In one alternative implementation, a complex programmable logic device is specifically used to encode register information using a specific unipolar return-to-zero code format, generate clock signals and data signals, and transmit the clock signals and data signals to the pin header interface.

[0010] This invention provides a detection system for power-on anomalies of server boards. By encoding register information in a specific unipolar return-to-zero code format, it enables rapid acquisition of abnormal signals in the power supply signals corresponding to the register information, laying the foundation for subsequent external testing equipment to detect power-on anomalies of server boards.

[0011] In one alternative implementation, the external detection device is a host computer or a waveform measurement tool.

[0012] In one optional implementation, the pin header interface is connected to the host computer via a USB interface simulator; wherein the host computer decodes the clock signal and data signal, generates power supply information, and generates a power-on anomaly detection result for the server board based on the power supply information.

[0013] The present invention provides a detection system for abnormal power supply of server boards. The pin header interface is connected to the host computer through a USB interface simulator, which realizes the effect of quickly locating abnormal power supply.

[0014] In one optional implementation, the pin header interface is connected to a waveform measurement tool; wherein the waveform measurement tool captures the measured waveform, decodes the measured waveform, generates power supply information, and generates a power-on anomaly detection result for the server board based on the power supply information.

[0015] This invention provides a detection system for abnormal power-on of server boards. The pin header interface is connected to a waveform measurement tool, which enables rapid acquisition of the measurement waveform corresponding to the power supply signal and rapid location of abnormal power supply.

[0016] In one optional implementation, the baseboard management controller is further configured to read register information via a serial communication protocol when in a normal state, compare the register information with preset power supply information, and generate a power-on anomaly detection result for the server board based on the comparison result.

[0017] The present invention provides a detection system for power-on anomalies on server boards. By reading register information from the baseboard management controller, the system can quickly determine the location of the power-on anomaly, thus solving the problems of low efficiency and risk in locating power-on anomalies.

[0018] In one optional implementation, it further includes: a switch state switching chip;

[0019] The switch state switching chip is connected to the complex programmable logic device (CPLD) to obtain the reset signal transmitted by the CPLD and control the server to switch from the power-off state to the power-on state based on the reset signal.

[0020] The present invention provides a detection system for abnormal power-on of server boards, which can ensure that the power management chip cannot complete the power-on action when the power supply is abnormal, so as to ensure the normal working environment after subsequent power-on.

[0021] In one alternative implementation, the switch state switching chip is a southbridge chip.

[0022] In one optional implementation, the complex programmable logic device is further configured to determine the output signal status of the power management chip based on the power supply signal, and when the output signal status of the power management chip is in a normal state, a reset signal is sent to the switch state switching chip.

[0023] The present invention provides a detection system for abnormal power-on of server boards, which sends a reset signal to the switch state switching chip through a complex programmable logic device, thereby realizing effective control of power-on and power-off actions.

[0024] Secondly, the present invention provides a method for detecting abnormal power-on of a server board, applied to the aforementioned detection system for abnormal power-on of a server board, the method comprising:

[0025] The complex programmable logic device receives the power supply signal sent by the power management chip and the status detection signal sent by the baseboard management controller. It stores the power supply signal, generates register information, and when the status detection signal is an abnormal status signal, it cyclically transmits the register information to the pin header interface in the form of unipolar return-to-zero code.

[0026] The pin header interface receives register information and transmits it to an external testing device to generate a power-on anomaly detection result for the server board. Attached Figure Description

[0027] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 It is based on the structural diagram of the power-on control of the relevant server;

[0029] Figure 2 This is a structural block diagram of a server board power-on abnormality detection system according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the server power-on control and detection process according to an embodiment of the present invention;

[0031] Figure 4 This is a flowchart illustrating a method for detecting abnormal power-on of a server board according to an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] like Figure 1 As shown, in the relevant server power supply detection function, the CPLD (Complex Programmable Logic Device) actually plays a control role. When the power supply to the server to be detected is insufficient, the CPLD will not release the RST signal, thus preventing the dangerous behavior of powering on due to insufficient power supply.

[0034] After the server is powered on, the CPLD also needs power to operate, so basic power supply is essential. If even some basic STBY power (direct power supply after connecting to the power supply, such as P3V3_STBY, P1V8_STBY) is missing, there is no need to test it, because the scope of investigation is already very small. Since the enable signal of the VR chip (power management chip) is provided by the PG signal (PowerGood signal, which is output after the VR chip output voltage reaches the specification, indicating that the VR power supply is normal and complete) of the previous stage VR chip, if the PG of a certain VR chip fails to output, it usually means that the root cause is not far away.

[0035] For the power supply module that is active during the power-on process, the CPLD monitors the PG signal generated after the VR chip is fully powered. After collecting all PG signals, the CPLD releases the RSM_RST signal (indicating that the power-on preparation is complete and the device can be started via the power button). After this, the power button starts to function, and the server begins to transition from the S5 state (power off state) to the S0 state (power on state).

[0036] Under the relevant server power supply detection method, the CPLD can ensure that in S5 state, the power supply to the STBY chip is abnormal, preventing the power-on process from being completed, thus ensuring a normal operating environment after subsequent power-on. However, the problem is that when an anomaly occurs, it only indicates that a problem has occurred, but cannot quickly pinpoint the source. It requires manually measuring the enable signal input to the VR chip and the voltage output by the VR chip using a multimeter, tracing the problem upwards level by level. This method is not only time-consuming, but also prone to errors due to uncertainties in the measurement environment, such as whether to measure the entire device versus a bare board, uncertain humidity and temperature, and the sharpness of the multimeter probes. Furthermore, if the operator is not skilled, it may cause the VR chip to short-circuit and burn out surrounding components, resulting in low efficiency and risk.

[0037] This invention provides a detection system for abnormal power-on of server boards, such as... Figure 2 As shown, it includes: at least one power management chip 1 (i.e., VR chip), a complex programmable logic device 2 (CPLD), a baseboard management controller 3 (BMC), and a pin header interface 4. The CPLD 2 is connected to at least one power management chip 1, the baseboard management controller 3, and the pin header interface 4, respectively. The pin header interface 4 is connected to an external testing device.

[0038] The complex programmable logic device 2 is used to receive the power supply signal (i.e., PG signal) sent by the power management chip 1 and the status detection signal (i.e., WDT signal) sent by the baseboard management controller 3, store the power supply signal, generate register information, and when the status detection signal is an abnormal status signal, cyclically transmit the register information to the pin header interface 4 through a specific unipolar return-to-zero code.

[0039] Specifically, a specific unipolar return to zero (SURZ) code is used to cyclically transmit register information to pin header interface 4. The specific unipolar return to zero code serves as a communication protocol.

[0040] Furthermore, when the baseboard management controller 3 is not operating normally, the complex programmable logic device 2 cannot report via I2C. If the complex programmable logic device 2 detects that the baseboard management controller 3 is stuck (i.e., in an abnormal state) via the WDT signal, it can output the register information in the form of SURZ on a separate pin header interface 4.

[0041] Furthermore, the WDT acquires status detection signals. The WDT, or watchdog timer, monitors input signals at a specified frequency. If the input signal of the board management controller 3 remains unchanged for a long time, it is determined that the board management controller 3 is stuck, and the set output signal is immediately triggered to go low or high.

[0042] Pin header interface 4 is used to receive register information and transmit the register information to an external testing device, so as to generate a power-on anomaly detection result of the server board through the external testing device.

[0043] Specifically, the external testing equipment uses a host computer or waveform measurement tools.

[0044] This embodiment provides a server board power-on anomaly detection system that cyclically transmits register information to the pin header interface using a specific unipolar return-to-zero code format. The system then reads the register information from the complex programmable logic device via the pin header interface to determine the location of the power-on anomaly. This solves the problems of low efficiency and risk in locating power-on anomalies, reduces data transmission risks, and ensures that the server is not at risk due to exposed pins by placing the pin header interface on the server board. It also avoids the short-circuit risk associated with measuring the power supply signals of each power management chip individually with a multimeter, thus reducing the risks during power-on anomaly detection and improving the efficiency of power-on anomaly detection for server boards.

[0045] In some alternative implementations, the complex programmable logic device 2 is specifically used to encode register information using a specific unipolar return-to-zero code format, generate a clock signal (i.e., SURZ_CLK) and a data signal (i.e., SURZ_DATA), and transmit the clock signal and data signal to the pin header interface 4.

[0046] Specifically, a specific unipolar return-to-zero code requires two signals: a clock signal and a data signal. The clock signal uses 100kHz and is sampled on the rising edge of the I2C (Inter-Integrated Circuit, bidirectional two-wire synchronous serial bus). During clock signal sampling, if the data signal is 1 for 3 consecutive bits and then 0 for 1 bit, it is considered the start of transmission. The next 4 bits represent the total number of power supply signals, allowing up to 15 power supply signals to be detected. The next 4 bytes of data are power supply information. Even-numbered bits (bit0, bit2, bit4, bit6, etc.) are information bits, representing the power supply signal corresponding to the information in this register (default high active). Odd-numbered bits (bit1, bit3, bit5, bit7) are error prevention bits, set to the opposite value of the active bits to prevent erroneous codes due to timing issues during sampling. After the 4 bytes of data transmission are completed, there is one more byte of data. The high four bits are the checksum, which can be compared with the quantity in the first 1 byte of data to detect if any power supply signal is 0. Finally, 1 bit0 and 3 bits1 indicate the end of data transmission.

[0047] This embodiment provides a server board power-on anomaly detection system. By encoding register information in a specific unipolar return-to-zero code format, it enables rapid acquisition of abnormal signals in the power supply signals corresponding to the register information, laying the foundation for subsequent external testing equipment to detect power-on anomalies of server boards.

[0048] In some optional implementations, the pin header interface 4 is connected to the host computer via a USB (Universal Serial Bus) interface simulator; wherein the host computer decodes the clock signal and data signal, generates power supply information, and generates a power-on anomaly detection result of the server board based on the power supply information.

[0049] Specifically, in the event of an abnormal hang-up of the baseboard management controller 3, the JTAG (Joint Test Action Group, a common name for IEEE standard 1149.1, also known as Standard Test Access Port and Boundary Scan Structure) signal is simulated through a USB interface simulator to read the internal signals of the CPLD, thereby achieving the effect of quickly locating power supply abnormalities without using out-of-band means.

[0050] For example, when the decoded power supply signal is 11100111 10101010 10101000 000000000000000010010111, byte 0: 1110 0111, the high four bits indicate the start of transmission, and the low four bits indicate that the number of power supply signals is 7. Bytes 1-4: 10101010 10101000 00000000 00000000, indicating that the first seven power supply signals are normal. Byte 5: 1001 0111 indicates that the sum of all 1s in byte 1-4, when multiplied by their complement, equals 1001. This sum, when added to the number of power supply signals, equals 0, confirming that there is no power supply signal output (low). This means that the power management chip 1 is functioning correctly. The lower four bits, 0111, represent the end bit. Therefore, due to the presence of the error-proof bit, if byte 1-4 contains 111 or more consecutive 1s, it is immediately possible to determine which power management chip 1 is malfunctioning, thus allowing for troubleshooting.

[0051] This embodiment provides a detection system for abnormal power-on of server boards. The pin header interface is connected to the host computer via a USB interface simulator, which enables rapid location of power supply abnormalities.

[0052] In some optional implementations, the pin header interface 4 is connected to a waveform measurement tool; wherein the waveform measurement tool captures the measured waveform, decodes the measured waveform, generates power supply information, and generates a power-on anomaly detection result for the server board based on the power supply information.

[0053] Specifically, when a power-on failure occurs, the corresponding waveform can be directly obtained using an oscilloscope or other waveform measurement tools. Based on the obtained waveform, the power supply information corresponding to the number of register bits can be decoded and read according to the SURZ encoding method and the pre-designed specifications. Then, based on the power supply information, the power-on anomaly detection result of the server board can be generated.

[0054] This embodiment provides a detection system for abnormal power-on of server boards. The pin header interface is connected to a waveform measurement tool, which enables rapid acquisition of the measurement waveform corresponding to the power supply signal and rapid location of abnormal power supply.

[0055] In some optional implementations, the baseboard management controller 3 is also used to read register information via a serial communication protocol when in a normal state, compare the register information with preset power supply information, and generate a power-on anomaly detection result for the server board based on the comparison result.

[0056] Specifically, when the baseboard management controller 3 is working normally, the power supply signal in the register is displayed on the WEB (network) of the baseboard management controller 3 via the I2C protocol, or the register value corresponding to the power supply signal is read directly via serial port command.

[0057] Furthermore, when the baseboard management controller 3 is in normal state, it sends the SCL signal (which is the clock signal line on the I2C bus) and the SDA signal (which is the data signal line on the I2C bus) to the complex programmable logic device. When the SCL signal is high and the SDA signal transitions from high to low, the register information is read. When the SCL signal is high and the SDA signal transitions from low to high, the register information reading stops.

[0058] Furthermore, under normal operating conditions, register information is obtained through the baseboard management controller 3. The power supply signal is stored in the register of the complex programmable logic device through code. Once the power supply signal representing the completion of power-on is pulled low, the data of the corresponding bit in the register will change from 1 to 0. When the baseboard management controller 3 reads a register that should be 1 but is 0, an alarm is triggered.

[0059] This embodiment provides a server board power-on anomaly detection system that quickly determines the location of the power-on anomaly by reading register information from the baseboard management controller, thus solving the problems of low efficiency and risk in locating power-on anomalies.

[0060] In some optional implementations, it also includes: a switch state switching chip 5;

[0061] The switch state switching chip 5 is connected to the complex programmable logic device 2 and is used to obtain the reset signal (RSM_RST) transmitted by the complex programmable logic device 2, and control the server to switch from the power-off state to the power-on state based on the reset signal.

[0062] Specifically, the switch state switching chip 5 uses a southbridge chip (Platform Controller Hub, PCH).

[0063] Furthermore, RSM_RST is a reset signal sent to the switch state switching chip 5 to let the switch state switching chip 5 know that the standby voltage has returned to normal and it can work normally. Generally, when the basic voltages such as P5V_STBY (5V power supply) and P3V3_STBY (3V power supply) are normal, the complex programmable logic device 2 pulls it high, which is equivalent to releasing a valid reset signal. At this time, the switch state switching chip 5 is no longer reset, and it will only enter the power-on process after receiving the power button action.

[0064] This embodiment provides a detection system for abnormal power-on of server boards, which can ensure that the power management chip cannot complete the power-on action when the power supply is abnormal, so as to ensure the normal working environment after subsequent power-on.

[0065] In some optional implementations, the complex programmable logic device 2 is also used to determine the output signal status of the power management chip 1 based on the power supply signal. When the output signal status of the power management chip 1 is in a normal state, a reset signal is sent to the switch state switching chip 5.

[0066] This embodiment provides a server board power-on abnormality detection system that sends a reset signal to the switch state switching chip through a complex programmable logic device, thereby achieving effective control of the power-on and power-off actions.

[0067] like Figure 3 As shown below, a specific embodiment will be used to illustrate the working process of a server board power-on abnormality detection system.

[0068] Example 1:

[0069] First, the CPLD reads the PG signal output by the VR chip, and releases RSM_RST when the PG signal is complete, in order to complete the monitoring work.

[0070] Secondly, when the BMC is working normally, the PG information in the register is displayed on the BMC's web interface via the I2C protocol, or the register value corresponding to the PG information is read directly via serial port commands.

[0071] Secondly, when the BMC is not functioning properly, the CPLD cannot report via I2C. In this case, if the CPLD detects that the BMC is hanging via the WDT, it can output the register information to a separate header via SURZ, similar to the JTAG interface currently used on servers, as a debug interface. When power-on failures occur, the corresponding waveforms can be directly obtained using an oscilloscope or other waveform measurement tools.

[0072] Finally, based on the obtained waveform, the PG information corresponding to the number of register bits can be decoded and read out according to the SURZ encoding method and the pre-designed specifications.

[0073] In the above embodiments, only the signal needs to be brought out in the hardware. Using the pin header interface can achieve the following effects: it can be used in the early stages of R&D to complete debugging work. After the R&D reaches a certain stage and such bugs are no longer easily encountered, the pin headers are not processed during board making, ensuring that the finished server will not be at risk due to exposed pin headers. At the same time, this debugging method avoids the short circuit risk caused by measuring the PG signal of VR chip one by one with a multimeter, and is more efficient and accurate than measuring with a multimeter.

[0074] This invention also provides a method for detecting abnormal power-on of server boards, such as... Figure 4 As shown, it includes:

[0075] In step S401, the complex programmable logic device receives the power supply signal sent by the power management chip and the status detection signal sent by the baseboard management controller, stores the power supply signal, generates register information, and when the status detection signal is an abnormal status signal, it cyclically transmits the register information to the pin header interface in the form of unipolar return-to-zero code.

[0076] In step S402, the pin header interface receives register information and transmits the register information to an external testing device to generate a power-on anomaly detection result for the server board.

[0077] The method for detecting abnormal power-on of a server board in this embodiment is applied to, for example, Figure 2 The illustrated embodiment is a server board power-on fault detection system. Therefore, the specific implementation of steps S401 and S402 can be found in the preceding text. Figure 2 The corresponding descriptions of the illustrated embodiments are not repeated here.

[0078] It is understandable that the function and beneficial effects of the method in this embodiment are the same as those of the previous embodiment. Figure 2 The function and beneficial effects of the server board power-on abnormality detection system in the illustrated embodiment correspond to each other, and will not be repeated here.

[0079] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0080] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0081] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between apparatuses or units may be electrical, mechanical, or other forms.

[0082] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0083] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0084] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this application, essentially, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0085] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A detection system for abnormal power-on of server boards, characterized in that, The system includes: at least one power management chip, a complex programmable logic device (CPL), a substrate management controller, and a pin header interface. The CPL is connected to the at least one power management chip, the substrate management controller, and the pin header interface, respectively. The pin header interface is connected to an external testing device. The complex programmable logic device is used to receive the power supply signal sent by the power management chip and the status detection signal sent by the baseboard management controller, store the power supply signal, generate register information, and when the status detection signal is an abnormal status signal, cyclically transmit the register information to the pin header interface through a specific unipolar return-to-zero code. The pin header interface is used to receive the register information and transmit the register information to the external detection device, so as to generate a power-on anomaly detection result of the server board through the external detection device; Specifically, the complex programmable logic device is used to encode the register information using the specific unipolar return-to-zero code form, generate clock signals and data signals, and transmit the clock signals and data signals to the pin header interface. The external detection equipment is a host computer or a waveform measurement tool; The pin header interface is connected to the host computer via a USB interface simulator; wherein, the host computer decodes the clock signal and the data signal, generates power supply information, and generates a power-on anomaly detection result for the server board based on the power supply information; The pin header interface is connected to the waveform measurement tool; wherein, the waveform measurement tool captures the measured waveform, decodes the measured waveform, generates power supply information, and generates a power-on anomaly detection result for the server board based on the power supply information.

2. The system for detecting power-on anomalies on a server board card of claim 1, wherein, The baseboard management controller is also used to read the register information through a serial communication protocol when it is in a normal state, compare the register information with preset power supply information, and generate a power-on abnormality detection result of the server board based on the comparison result.

3. The system for detecting power-on anomalies on a server board card of claim 1, wherein, Also includes: Switching chip for on / off states; The switch state switching chip is connected to the complex programmable logic device (CPLD) and is used to acquire the reset signal transmitted by the CPLD and control the server to switch from the power-off state to the power-on state based on the reset signal.

4. The system for detecting power-on anomalies on a server board card of claim 3, wherein, The switch state switching chip uses a southbridge chip.

5. The system for detecting power-on anomalies on a server board card of claim 3, wherein, The complex programmable logic device is also used to determine the output signal status of the power management chip based on the power supply signal. When the output signal status of the power management chip is normal, a reset signal is sent to the switch state switching chip.

6. A method for detecting power-on anomalies on a server board card, the method comprising: The method of the detection system for abnormal power-on of server boards as described in any one of claims 1 to 5 includes: The complex programmable logic device receives the power supply signal sent by the power management chip and the status detection signal sent by the baseboard management controller. It stores the power supply signal, generates register information, and when the status detection signal is an abnormal status signal, it cyclically transmits the register information to the pin header interface in the form of unipolar return-to-zero code. The pinout interface receives the register information and transmits the register information to an external detection device to generate a power-on abnormality detection result of a server board card by the external detection device.

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