A method, device and medium for optimizing area and power consumption of an MPRM logic circuit

Abstract

The application relates to an MPRM logic circuit area and power consumption optimization method, which comprises the following steps: S1, reading a Boolean logic circuit; S2, converting the Boolean logic circuit into an MPRM logic circuit through a polarity conversion method; S3, taking minimizing the area and power consumption of the MPRM logic circuit as a target, and searching for an initial high-quality Pareto optimal solution set by adopting a wolf swarm algorithm, in the wolf swarm algorithm, the form of the MPRM logic circuit polarity is mapped onto the position of a wolf swarm individual through quantum coding; S4, updating the position of the wolf swarm individual by adopting a quantum rotation gate; S5, judging whether the current iteration number is less than the maximum iteration number, if yes, updating the high-quality Pareto optimal solution set by executing the step S3, and if no, outputting the final high-quality Pareto optimal solution set. Compared with the prior art, the application improves the optimization effect of the MPRM logic circuit area and power consumption.

Description

Technical Field

[0001] This invention relates to the field of logic circuit area and power consumption optimization, and in particular to an MPRM logic circuit area and power consumption optimization method, device and medium. Background Technology

[0002] Early IC (Integrated Circuit) designs primarily focused on Boolean logic. However, digital circuits can also be implemented using Reed-Muller (RM) logic based on XNOR / XOR operations, achieving complete logical functions. Research shows that digital circuits using RM-based logic (such as arithmetic logic circuits and parity check circuits) offer advantages over traditional Boolean logic in terms of power consumption, area, speed, and testability. RM logic functions can be categorized into fixed-polarity RM (Fixed-Polarity Reed-Muller, FPRM) expressions and mixed-polarity RM (Mixed-Polarity Reed-Muller, MPRM) expressions based on the variable value form. Polarity determines the representation of the MPRM logic circuit, thus affecting the circuit's power and area. For a logic function with n input variables, there are 3n mixed-polarity and 2n fixed-polarity expressions, corresponding to 3n mixed-polarity expressions and 2n fixed-polarity expressions, respectively. All fixed-polarity expressions are contained within mixed-polarity expressions. Therefore, MPRM logic circuits have a larger optimization space than FPRM logic circuits, but the corresponding optimization process is also more complex. With the development of integrated circuit technology and the continuous increase in circuit scale, integrated circuit optimization design has shifted from early single-objective circuit performance optimization to multi-objective circuit performance comprehensive optimization. Therefore, area and power consumption have become one of the important factors hindering the development of large-scale and very-large-scale integrated circuits.

[0003] Existing MPRM logic circuit area and power consumption optimization methods are mostly based on traditional intelligent optimization algorithms such as weighted coefficient methods, non-dominated sorting genetic algorithms, and multi-objective particle swarm optimization. While the weighted coefficient method is relatively intuitive, the setting of weights is sensitive, and multiple runs are required to find the Pareto non-dominated set. Multi-objective optimization methods based on non-dominated sorting genetic algorithms, while robust and scalable, suffer from low population diversity, slow convergence, and susceptibility to local optima. Multi-objective optimization methods based on particle swarm optimization perform well in small-scale circuits, but lack testing for large-scale circuits with increased input variables. Furthermore, the need to consider parameter weights and particle boundary handling leads to lower robustness and efficiency.

[0004] Due to inherent limitations of algorithms such as the weighted coefficient method, non-dominated sorting genetic algorithm, and multi-objective particle swarm optimization (PSO), optimization methods for MPRM logic circuit area and power consumption based on these algorithms suffer from problems such as low solution set quality, slow convergence speed, and susceptibility to local optima. These limitations make it difficult to meet the need for fast and efficient optimization of the optimal area and power consumption for medium- to large-scale MPRM logic circuits. Therefore, researching an area and power consumption optimization method that can quickly converge to the Pareto optimality front is urgently needed in the field of MPRM logic circuit area and power consumption optimization. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, and medium for optimizing the area and power consumption of MPRM logic circuits to improve the optimization effect.

[0006] The objective of this invention can be achieved through the following technical solutions:

[0007] An MPRM logic circuit area and power consumption optimization method includes the following steps:

[0008] S1. Read the Boolean logic circuit;

[0009] S2. The Boolean logic circuit is converted into an MPRM logic circuit by means of polarity conversion.

[0010] S3. With the goal of minimizing the area and power consumption of the MPRM logic circuit, the wolf pack algorithm is used to search for an initial high-quality Pareto optimal solution set. In the wolf pack algorithm, the polarity of the MPRM logic circuit is mapped to the position of individual wolves through quantum encoding.

[0011] S4. Update the position of the individual wolves using a quantum rotating gate;

[0012] S5. Determine whether the current iteration number is less than the maximum iteration number. If yes, execute step S3 to update the high-quality Pareto optimal solution set. If no, output the final high-quality Pareto optimal solution set.

[0013] Furthermore, the quantum encoding is binary encoding, represented as:

[0014]

[0015] Where α and β represent the probability values ​​of the occurrence of "0" and "1" of the qubit, respectively, and satisfy the normalization condition |α| 2 +|β| 2 =1.

[0016] Furthermore, the expression for minimizing the area and power consumption of the MPRM logic circuit is as follows:

[0017]

[0018] Where p represents the polarity of the MPRM circuit, F(p) represents the fitness estimate for that polarity, A(p) represents the circuit area under that polarity, i.e., the total number of two-input gates of polarity p in the MPRM circuit; E(p) represents the circuit power consumption under that polarity, i.e., the switching activity rate of polarity p in the MPRM circuit; U represents the set of two-input gates; m OR and m XNOR These represent the number of two-input OR gates and the number of two-input XNOR gates, respectively; OR and l XNOR Let l represent the output signal probabilities of the two-input OR gate and the two-input XNOR gate, respectively. i E represents the i-th two-input gate. i The signal probability at its output terminal, E, can be used. i =2l i .

[0019] Furthermore, the specific steps for updating the location of the individual wolves include:

[0020] The quantum rotating gate is updated by changing the rotation angle;

[0021] Calculate the updated positions of individual wolves based on the updated quantum rotating gate;

[0022] Based on the updated positions of individual wolves, determine whether the wolf pack is trapped in a local optimum. If so, execute a mutation strategy to update the positions of the individual wolves; otherwise, continue executing the strategy.

[0023] Furthermore, the expression for the rotation angle is:

[0024] Δθ ij (t+1)=θ ij (t)+φ ij ·(θ kj (t)-θ ij (t))

[0025] Where, θ ij φ represents the rotation angle of the quantum rotation gate corresponding to the j-th qubit of the i-th individual. ij It is a random number between [-1, 1], k ≠ i, and t represents the current iteration number.

[0026] Furthermore, the expression for the updated position of the individual wolves is:

[0027] P it =[sin(θ)]i1 (t)+Δθ i1 (t+1)),…,sin(θ iD (t)+Δ(θ iD (t+1))]

[0028] Among them, P it The solution represents the position of the sine wave, and Δθ represents the rotation angle.

[0029] Furthermore, the expression for the mutation strategy is:

[0030]

[0031] Where, π′ t Let π represent the wolf after the t-th iteration mutation. α , π β and π δ They represent the alpha wolf, the scout wolf, and the fierce wolf, respectively. and γ represents the γ-th dimension of each wolf type in the t-th iteration; rand() represents a random number between (0,1), and z is set to 1 as a control constant. This indicates that the γth element of the π-th wolf is moved d units to the right or left.

[0032] Furthermore, if the number of iterations for an individual wolf exceeds a set threshold and the individual's position remains unchanged, the wolf is considered to be trapped in a local optimum.

[0033] The present invention also provides an electronic device, comprising: one or more processors; a memory; and one or more programs stored in the memory, said one or more programs including instructions for performing an MPRM logic circuit area and power consumption optimization method as described above.

[0034] The present invention also provides a computer-readable storage medium including one or more programs executable by one or more processors of an electronic device, said one or more programs including instructions for performing an MPRM logic circuit area and power consumption optimization method as described above.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] (1) This invention optimizes the area and power consumption of MPRM logic circuits by combining the wolf pack algorithm with quantum theory, which enables the area and power consumption of MPRM logic circuits to converge quickly to Pareto optimality, thereby improving the efficiency and effectiveness of MPRM logic circuit area and power consumption optimization.

[0037] (2) This invention enhances population diversity and reduces the risk of the algorithm getting stuck in local optima by implementing a mutation strategy when individuals get stuck in local optima. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0039] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0040] This embodiment provides a method for optimizing the area and power consumption of MPRM logic circuits, such as... Figure 1 As shown, the method includes the following steps:

[0041] S1, Read Boolean logic circuit.

[0042] This step is to obtain circuit information in Boolean logic circuits, including logic gates, inputs, and outputs.

[0043] S2. The Boolean logic circuit is converted into an MPRM logic circuit by means of polarity conversion.

[0044] For each logic gate in a Boolean logic circuit, polarity conversion is performed based on its function and the polarity of its input signals. Polarity conversion is the process of converting the polarity of the input and output signals of a Boolean logic gate to that of an MPRM logic gate. This can be determined using the truth table or logic function of the logic gate. Based on the converted polarity information, the MPRM logic circuit is constructed. An MPRM logic circuit is a multi-valued reversible logic circuit that can be implemented using different logic gate types and polarity information.

[0045] S3. With the goal of minimizing the area and power consumption of the MPRM logic circuit, the wolf pack algorithm is used to search for an initial high-quality Pareto optimal solution set. In the wolf pack algorithm, the polarity representation of the MPRM logic circuit is mapped to the position of individual wolves through quantum encoding.

[0046] First, the population size, maximum number of iterations, number of scouting wolves, and siege distance are initialized, and then the initial population is randomly generated.

[0047] The polarity representation of the MPRM logic circuit is mapped to the location of individual wolves using quantum encoding. In this embodiment, the quantum encoding used is binary encoding, represented as follows:

[0048]

[0049] Where α and β represent the probability values ​​of the occurrence of "0" and "1" of the qubit, respectively, and satisfy the normalization condition |α| 2 +|β| 2 =1.

[0050] In this step, the area of ​​the MPRM logic circuit is represented by the sum of the number of terms in XNOR and OR, the switching activity rate is obtained by calculating the probability of the output signal, and the power consumption of the MPRM logic circuit is represented by the switching activity rate.

[0051] Minimizing the area and power consumption of the MPRM logic circuit is the objective of the algorithm, which searches for a high-quality Pareto optimal solution set. The expression is:

[0052]

[0053] Where p represents the polarity of the MPRM circuit, F(p) represents the fitness estimate for that polarity, A(p) represents the circuit area under that polarity, i.e., the total number of two-input gates of polarity p in the MPRM circuit; E(p) represents the circuit power consumption under that polarity, i.e., the switching activity rate of polarity p in the MPRM circuit; U represents the set of two-input gates; m OR and m XNOR These represent the number of two-input OR gates and the number of two-input XNOR gates, respectively; OR and l XNOR Let l represent the output signal probabilities of the two-input OR gate and the two-input XNOR gate, respectively. i E represents the i-th two-input gate. i The signal probability at its output terminal, E, can be used. i =2l i .

[0054] S4. Use a quantum rotating gate to update the position of the wolf pack individuals.

[0055] This step performs a position update operation. To reduce the risk of the algorithm getting trapped in local optima, a mutation strategy is implemented to enhance population diversity. Specific steps include:

[0056] S4.1 The quantum rotating door is updated by changing the rotation angle, defined as:

[0057] Δθ ij (t+1)=θ ij (t)+φ ij ·(θ kj (t)-θ ij (t))

[0058] Where, φ ijIt is a random number between [-1, 1], k ≠ i, θ ij Let t represent the k-th element of individual i, and t represent the current iteration number.

[0059] S4.2 Calculate the updated individual position, defined as:

[0060] P it =[sin(θ)] i1 (t)+Δθ i1 (t+1)),…,sin(θ iD (t)+Δ(θ iD (t+1))]

[0061] Among them, P it The solution represents the position of the sine wave, and Δθ represents the rotation angle.

[0062] S4.3 When an individual gets stuck in a local optimum, a mutation strategy is initiated, defined as:

[0063]

[0064] Where, π α , π β and π δ They represent the alpha wolf, the scout wolf, and the fierce wolf, respectively. and γ represents the γ-th dimension of each wolf type in the t-th iteration; π′ represents the mutated wolf; rand() represents a random number between (0,1); and z is set to 1 as a control constant. This indicates that the γth element of the π-th wolf is moved d units to the right or left.

[0065] Implementing mutation strategies helps enhance population diversity, preventing the algorithm from getting trapped in local optima. Mutation strategies can be achieved by randomly perturbing the quantum encoding of individuals. This introduces new solutions and helps the algorithm explore a wider region of the search space. Updating position refers to adjusting the quantum encoding of an individual according to the operation of a quantum rotation gate. This can be achieved by applying an appropriate quantum rotation gate operation to change the individual's position. The purpose of updating position is to bring the individual closer to the optimal solution so as to obtain a better set of Pareto optima in the next iteration.

[0066] S5. Determine whether the current iteration number is less than the maximum iteration number. If yes, execute step S3 to update the high-quality Pareto optimal solution set. If no, output the final high-quality Pareto optimal solution set.

[0067] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0068] Example 2

[0069] This embodiment provides an electronic device, including: one or more processors; a memory; and one or more programs stored in the memory, the one or more programs including instructions for executing an MPRM logic circuit area and power consumption optimization method as described in Embodiment 1.

[0070] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0071] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0072] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0073] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

Claims

1. A method for optimizing the area and power consumption of an MPRM logic circuit, characterized in that, Includes the following steps: S1. Read the Boolean logic circuit; S2. The Boolean logic circuit is converted into an MPRM logic circuit by means of polarity conversion. S3. To minimize the area and power consumption of the MPRM logic circuit, a wolf pack algorithm is used to search for an initial high-quality Pareto optimal solution set. In the wolf pack algorithm, the polarity representation of the MPRM logic circuit is mapped to the position of individual wolves through quantum encoding. The expression for minimizing the area and power consumption of the MPRM logic circuit is as follows: in, Indicates the polarity of the MPRM circuit. This represents the fitness estimate for that polarity. This represents the circuit area under this polarity, i.e., the polarity in the MPRM circuit. The total number of two-input gates; This indicates the circuit power consumption under this polarity, i.e., the polarity in the MPRM circuit. Switching activity rate; Represents the set of two-input gates; and These represent the number of two-input OR gates and the number of two-input XNOR gates, respectively. and These represent the output signal probabilities of the two-input OR gate and the two-input XNOR gate, respectively. Indicates the first A two-input gate The signal probability at its output terminal can be used. ; S4. Update the position of the individual wolves using a quantum rotating gate; S5. Determine whether the current iteration number is less than the maximum iteration number. If yes, execute step S3 to update the high-quality Pareto optimal solution set. If no, output the final high-quality Pareto optimal solution set.

2. The method for optimizing the area and power consumption of an MPRM logic circuit according to claim 1, characterized in that, The quantum encoding is binary encoding, represented as: in, and These represent the probability values ​​of a quantum bit "0" and "1" occurring, respectively, and satisfy the normalization condition. .

3. The method for optimizing the area and power consumption of an MPRM logic circuit according to claim 1, characterized in that, The specific steps for updating the location of the individual wolves include: The quantum rotating gate is updated by changing the rotation angle; Calculate the updated positions of individual wolves based on the updated quantum rotating gate; Based on the updated positions of individual wolves, determine whether the wolf pack is trapped in a local optimum. If so, execute a mutation strategy to update the positions of the individual wolves; otherwise, continue executing the strategy.

4. The method for optimizing the area and power consumption of an MPRM logic circuit according to claim 3, characterized in that, The expression for the rotation angle is: in, Indicates the first The individual's first The rotation angle of the quantum rotation gate corresponding to each qubit. It is a random number between [-1, 1]. , This indicates the current iteration number.

5. The method for optimizing the area and power consumption of an MPRM logic circuit according to claim 3, characterized in that, The updated expression for the position of the individual wolves is: in, The solution representing the position of the sine wave. Indicates the rotation angle.

6. The method for optimizing the area and power consumption of an MPRM logic circuit according to claim 3, characterized in that, The expression for the mutation strategy is: in, Indicates the first The wolf after the next iteration mutation. , and They represent the alpha wolf, the scout wolf, and the fierce wolf, respectively. , and They represent the first time in the second month. In the nth iteration, the first... Dimension; Represents a random number between (0,1). It is set to 1 as a control constant. Indicates the first Sekiro's first The element moves to the right or left. Units.

7. The method for optimizing the area and power consumption of an MPRM logic circuit according to claim 3, characterized in that, If the number of iterations for an individual wolf exceeds a set threshold and the individual's position remains unchanged, the wolf is considered to be trapped in a local optimum.

8. An electronic device, characterized in that, include: One or more processors; Memory; and One or more programs stored in memory, the one or more programs including instructions for executing an MPRM logic circuit area and power consumption optimization method as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, Includes one or more programs executable by one or more processors of an electronic device, said one or more programs including instructions for performing an MPRM logic circuit area and power consumption optimization method as described in any one of claims 1-7.

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