A clock signal conditioning circuit and display device

Abstract

This invention discloses a clock signal adjustment circuit and a display device. The clock signal adjustment circuit includes an input terminal, an output terminal, a first capacitor, and at least one voltage divider branch. The first capacitor is connected between the input terminal and the output terminal. At least one voltage divider branch is connected between the output terminal and a ground terminal. The voltage divider branch includes a second capacitor and a voltage divider control unit connected in series. The control terminal of the voltage divider control unit is electrically connected to a voltage divider control signal line. The voltage divider control unit is configured to turn on or off under the control of a voltage divider control signal provided by the voltage divider control signal line, thereby turning the voltage divider branch on or off. The technical solution of this invention can adjust the clock signal, thereby achieving clock signal clipping or changing the effective pulse width, thus improving electromagnetic interference to the display panel and avoiding high-temperature screen flickering.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a clock signal conditioning circuit and a display device. Background Technology

[0002] With the development of display technology, display panels are being used more and more widely, and the requirements for the display effect of display panels are also getting higher and higher.

[0003] Display panels typically include several pixel units, requiring gate drive signals to activate these units and control the display. However, as those skilled in the art know, gate drive signals are generally converted from clock signals. Clock signals undergo a significant abrupt transition from high to low levels, generating high-frequency electromagnetic components that can cause electromagnetic interference, affecting the normal operation of the display panel. Furthermore, the conversion of clock signals into gate drive signals can lead to fluctuations in the gate drive signal under high-temperature conditions, resulting in screen flickering due to high temperatures. Summary of the Invention

[0004] This invention provides a clock signal adjustment circuit and a display device, which can adjust the clock signal to achieve clock signal beveling or change the effective pulse width, thereby improving electromagnetic interference to the display panel and avoiding the phenomenon of high temperature screen flickering.

[0005] In a first aspect, embodiments of the present invention provide a clock signal conditioning circuit, including an input terminal, an output terminal, a first capacitor, and at least one voltage divider branch;

[0006] The first capacitor is connected between the input terminal and the output terminal;

[0007] The at least one voltage divider branch is connected between the output terminal and the ground terminal, and the voltage divider branch includes a second capacitor and a voltage divider control unit connected in series.

[0008] The control terminal of the voltage divider control unit is electrically connected to the voltage divider control signal line. The voltage divider control unit is configured to turn on or off under the control of the voltage divider control signal provided by the voltage divider control signal line, so as to turn on or off the voltage divider branch.

[0009] Secondly, embodiments of the present invention also provide a display device, including a clock signal adjustment circuit as described in any of the first aspects of the present invention.

[0010] This invention provides a clock signal conditioning circuit and a display device. The clock signal conditioning circuit includes an input terminal, an output terminal, a first capacitor, and at least one voltage divider branch. The first capacitor is connected between the input terminal and the output terminal. At least one voltage divider branch is connected between the output terminal and a ground terminal. The voltage divider branch includes a second capacitor and a voltage divider control unit connected in series. The control terminal of the voltage divider control unit is electrically connected to a voltage divider control signal line. The voltage divider control unit is configured to be turned on or off under the control of a voltage divider control signal provided by the voltage divider control signal line, thereby turning the voltage divider branch on or off. The technical solution of this invention, by controlling the conduction of the voltage divider branch in the clock signal conditioning circuit, can perform voltage divider control on the clock signal input to the clock signal conditioning circuit, so that the output terminal outputs a voltage-divided clock signal, thereby achieving clock signal conditioning. This helps to achieve clock signal clipping or pulse width reduction, thus solving the problem of electromagnetic interference from the clock signal affecting the normal operation of the display panel and the problem of high-temperature screen flickering in the display panel, improving the display quality of the display panel, and thus improving the user's viewing experience. Attached Figure Description

[0011] Figure 1 This is a circuit structure diagram of a gate drive circuit in related technologies;

[0012] Figure 2 yes Figure 1 The control timing diagram of the gate drive circuit is shown below.

[0013] Figure 3 This is a circuit structure diagram of a clock signal conditioning circuit provided in an embodiment of the present invention;

[0014] Figure 4 yes Figure 3 The diagram shows a control timing diagram for a clock signal conditioning circuit.

[0015] Figure 5 yes Figure 3 Another control timing diagram of the clock signal conditioning circuit shown;

[0016] Figure 6 yes Figure 3 The diagram shows another control timing diagram for the clock signal conditioning circuit.

[0017] Figure 7 This is a circuit structure diagram of another clock signal conditioning circuit provided in an embodiment of the present invention;

[0018] Figure 8 yes Figure 7 The diagram shows a control timing diagram for a clock signal conditioning circuit.

[0019] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0020] Figure 10 This is a schematic diagram of the structure of a display device provided in another embodiment of the present invention. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0022] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0024] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish the corresponding contents and are not used to limit the order or interdependence.

[0025] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0026] Figure 1 This is a circuit structure diagram of a gate drive circuit in related technologies. Figure 2 yes Figure 1 The control timing diagram of the gate drive circuit shown is for reference. Figure 1 , Figure 2In related technologies, the pixel circuit of a display panel typically receives the gate scan signal from a gate driving circuit. In this circuit, the clock signal is input at the CK / XCK terminal, and the scan pulse signal, i.e., the gate driving signal, is output from the G(N) terminal to the gate of the thin-film transistor (TFT) in the pixel circuit. Since there is usually a parasitic capacitance between the gate and source of the TFT, when the level of the scan pulse signal applied to the gate of the TFT changes, such as from high to low, the gate potential experiences a significant drop. Due to the parasitic capacitance, the source potential also experiences a significant drop, causing a sudden change in the current flowing through the light-emitting element connected to the TFT. This leads to flickering and image retention issues on the display panel. Furthermore, since the clock signal is generally a square wave signal, the sudden change from high to low essentially creates a high-frequency component. This high-frequency component generates significant electromagnetic interference, affecting the normal operation of the internal circuitry of the display panel and causing display defects.

[0027] like Figure 1 and Figure 2 As shown, to solve the above problems, related technologies add a branch containing transistor T3 to the gate drive circuit. This branch controls the output signal of the gate drive circuit's output terminal G(N). By controlling the conduction of transistor T3 through the CT control signal, the scanning pulse signal output from the gate drive circuit's output terminal G(N) can achieve beveling, thereby solving the aforementioned display defects in the display panel. However, this technical solution requires adding transistor T3 to each stage of the gate drive circuit and adding two additional signal lines, making the gate drive circuit wiring more complex. Furthermore, the method of achieving beveling by adding transistors suffers from the short linear region of the transistors, making it difficult to accurately control the magnitude of the signal CT to ensure the beveling depth. Additionally, the increased load leads to higher power consumption in the gate drive circuit.

[0028] To address the aforementioned technical issues, this invention provides a clock signal adjustment circuit. Figure 3 This is a circuit structure diagram of a clock signal conditioning circuit provided in an embodiment of the present invention, for reference. Figure 3 It includes an input terminal CLK, an output terminal CLK', a first capacitor C1, and at least one voltage divider branch 20; the first capacitor C1 is connected between the input terminal CLK and the output terminal CLK'; at least one voltage divider branch 20 is connected between the output terminal CLK' and the ground terminal GND, and the voltage divider branch 20 includes a second capacitor C2 and a voltage divider control unit 22 connected in series; the control terminal 221 of the voltage divider control unit 22 is electrically connected to the voltage divider control signal line (not shown in the figure), and the voltage divider control unit 22 is configured to be turned on or off under the control of the voltage divider control signal CT provided by the voltage divider control signal line, so as to turn the voltage divider branch 20 on or off.

[0029] First, this clock signal conditioning circuit is mainly used to regulate the waveform of the clock signal input at the input terminal CLK by voltage division. Specifically, the first capacitor C1 and the voltage divider branch 20 in this clock signal conditioning circuit essentially form a series circuit connected between the clock signal input terminal CLK and the ground terminal GND. Since the clock signal is an AC signal, a capacitor voltage divider circuit is formed here using the first capacitor C1 and the second capacitor C2 in the voltage divider branch 20. A voltage divider output terminal is set at the connection node between the first capacitor C1 and the second capacitor C2, forming the clock signal output terminal CLK', which is used to output the divided clock signal. According to the impedance formula of a capacitor... As can be seen from the voltage divider principle, the clock signal output by the output terminal CLK' satisfies... Simplifying, we get: CLK'=(C1 / (C1+C2))*CLK.

[0030] In addition, the clock signal conditioning circuit in this embodiment also connects a voltage divider control unit 22 in series in the voltage divider branch 20. This unit is mainly used to control the on / off state based on the voltage divider control signal CT, thereby controlling whether the clock signal input terminal CLK is voltage-divided using the voltage divider branch 20. Therefore, by properly setting the timing of the voltage divider control signal CT, the clock signal can be voltage-divided in accordance with the timing of the clock signal. Specifically, please refer to... Figure 2 The control timing shown indicates that the voltage divider control signal CT is set to conduct the voltage divider control unit 22 during a portion of the time before the clock signal transitions from high to low at the end of its effective level. This allows the voltage divider branch 20 to divide the clock signal at the end of its effective level, lowering the potential. Since the capacitor undergoes a charging and discharging process, the voltage division process of the second capacitor C2 is actually a gradual process. Therefore, the clock signal gradually decreases in potential at the end of its effective level, thus achieving the beveling of the clock signal.

[0031] The above-described method of using a voltage divider control signal CT to adjust the clock signal to achieve beveling is only one application of the clock signal adjustment circuit provided in this embodiment of the invention. In other embodiments, a suitable voltage divider control signal CT can also be used to adjust the effective pulse width of the clock signal, which will not be described in detail here.

[0032] As can be seen from the above, the clock signal adjustment circuit provided in this embodiment of the invention can adjust the waveform of the clock signal, enabling the output terminal CLK' to output a beveled clock signal. When applied to the gate drive circuit, it can reduce the sudden change in source potential caused by parasitic capacitance, and also reduce electromagnetic interference caused by electromagnetic high-frequency components generated during the process of the clock signal abruptly changing from a high level to a low level. Furthermore, it solves problems such as flickering and poor image retention on the display panel caused by the abrupt change from a high level to a low level in the gate drive signal converted from the clock signal. In addition, this embodiment of the invention can also adjust the waveform of the clock signal to enable the output terminal CLK' to output clock signals with different effective pulse widths, thereby compensating for fluctuations in the gate drive signal generated under high-temperature conditions, balancing the gate drive signals at each stage, and thus helping to solve the problem of high-temperature screen flickering in the display panel.

[0033] Furthermore, it should be noted that in the above embodiments, the voltage divider control signal CT is input via the voltage divider control signal line. That is, the clock signal adjustment circuit in this embodiment of the invention needs to include both a voltage divider control signal line and a ground signal line. However, since each stage of the gate drive circuit in the display panel only requires one clock signal from this clock signal adjustment circuit, in terms of circuit design complexity, this embodiment of the invention can simply add this clock signal adjustment circuit without changing the gate drive circuit. This avoids power consumption issues in the gate drive circuit and also avoids increasing wiring problems in the gate drive circuit.

[0034] This invention provides a clock signal conditioning circuit, including an input terminal, an output terminal, a first capacitor, and at least one voltage divider branch. The first capacitor is connected between the input terminal and the output terminal. At least one voltage divider branch is connected between the output terminal and a ground terminal. The voltage divider branch includes a second capacitor and a voltage divider control unit connected in series. The control terminal of the voltage divider control unit is electrically connected to a voltage divider control signal line. The voltage divider control unit is configured to be turned on or off under the control of a voltage divider control signal provided by the voltage divider control signal line, thereby turning the voltage divider branch on or off. The technical solution of this invention, by controlling the conduction of the voltage divider branch in the clock signal conditioning circuit, can perform voltage divider control on the clock signal input to the clock signal conditioning circuit, so that the output terminal outputs a voltage-divided clock signal, thereby achieving clock signal conditioning. This helps to achieve clock signal clipping or pulse width reduction, thus solving the problem of electromagnetic interference from the clock signal affecting the normal operation of the display panel and the problem of high-temperature screen flickering in the display panel, improving the display quality of the display panel, and thus improving the user's viewing experience.

[0035] Optionally, Figure 4 yes Figure 3 The diagram shown is a control timing diagram of a clock signal conditioning circuit, for reference. Figure 4In one specific embodiment, the voltage divider branch 20 may include multiple output cycles, each output cycle including an active phase T1 and an inactive phase T2; in the active phase T1, the clock signal is at an active level; in the inactive phase T2, the clock signal is at an inactive level; the active phase T1 is divided into a normal phase T3 and a voltage divider phase T4, with the voltage divider phase T4 following the normal phase T3 in the time dimension; the voltage divider control signal CT is configured such that: in the normal phase T3, the voltage divider control signal CT is at an inactive level; and in the voltage divider phase T4, the voltage divider control signal CT is at an active level. In different output cycles, the duration of the voltage divider phase T4 within the active phase T1 is the same to ensure consistent chamfering in each cycle.

[0036] For details, please refer to Figure 3 , Figure 4 The capacitance of the first capacitor C1 is greater than that of the second capacitor C2, and CLK' = (C1 / (C1+C2))*CLK. It can be seen that the voltage output from the output terminal CLK', after being divided by C2, still accounts for most of the input voltage of the input terminal CLK, ensuring that the turn-on voltage of the subsequent transistors is met. In the effective phase T1 of each output cycle, the voltage divider control signal line provides the voltage divider control signal CT to the voltage divider control unit 22. In the normal phase T3 of the effective phase T1, the voltage divider control signal CT is at an invalid level. At this time, the voltage divider control unit 22 is not turned on, and the clock signal output from the corresponding output terminal CLK' is not divided by the first capacitor C1 and the second capacitor C2. In the voltage divider phase T4 of the effective phase T1, the voltage divider control signal CT is at an effective level. At this time, the voltage divider control signal line outputs a high level to the voltage divider control unit 22, and the voltage divider control unit 22 is turned on. The clock signal output from the corresponding output terminal CLK' is the cut-off clock signal after being divided by the first capacitor C1 and the second capacitor C2.

[0037] Optionally, Figure 5 yes Figure 3 Another control timing diagram of the clock signal conditioning circuit shown is provided for reference. Figure 3 , Figure 5 In another embodiment of the present invention, the duration of the voltage divider stage T4 in the effective stage T1 can be set to be the same or different in different output cycles, and the duration of the voltage divider stage T4 in the effective stage T1 in any output cycle is in the range of 0 to 100%.

[0038] Specifically, under high-temperature conditions, the electrical characteristics of the transistors in the gate drive circuit of the display panel will shift, which will cause the gate scan signal generated by the gate drive circuit according to the clock signal to be unstable, thus causing the display screen to flicker. Therefore, in this embodiment, when the voltage divider control signal CT is provided to the voltage divider control unit 22 through the voltage divider control signal line in the effective phase T1 of each output cycle, since the voltage divider control signal CT is invalid in the normal phase T3 of the effective phase T1, the voltage divider control unit 22 is not turned on at this time, and the clock signal output by the corresponding output terminal CLK' is not divided by the first capacitor C1 and the second capacitor C2; while in the voltage divider phase T4 of the effective phase T1, the voltage divider control signal CT is valid, and the voltage divider control signal line outputs a high level to the voltage divider control unit 22, the voltage divider control unit 22 is turned on, and the clock signal output by the corresponding output terminal CLK' is divided by the first capacitor C1 and the second capacitor C2, wherein the capacitance value of the first capacitor C1 is less than the capacitance value of the second capacitor C2. According to CLK'=(C1 / C1+C2)*CLK, in the normal phase T3, the clock signal output by the output terminal CLK' is not divided by the second capacitor C2, which satisfies the turn-on voltage of the subsequent light-emitting transistor. However, in the voltage division phase T4, the clock signal output by the output terminal CLK' is divided by the second capacitor C2, and the output part is the part divided by the first capacitor C1. The capacitance value of the first capacitor C1 is less than the capacitance value of the second capacitor C2, making the clock signal output by the output terminal CLK' small enough to not turn on the subsequent transistor. Thus, only the clock signal in the normal phase T3 can turn on the subsequent transistor, achieving the effect of reducing the pulse width of the output clock signal.

[0039] In one specific embodiment, the ratio of the capacitance value of the optional second capacitor C2 to the capacitance value of the first capacitor C1 is greater than or equal to 9. 。 Specifically, based on the typical turn-on voltage threshold of a transistor, when the voltage level of the voltage divider stage T4 is less than 1 / 10 of the voltage level of the normal stage T3, it can be ensured that the voltage level of the voltage divider stage T4 cannot turn on subsequent transistors. Based on this, and using the voltage formula CLK' = (C1 / C1 + C2) * CLK, it can be derived that C2 = 9C1.

[0040] Figure 6 yes Figure 3 Another control timing diagram of the clock signal conditioning circuit shown is provided for reference. Figure 6In another embodiment of the present invention, the optional voltage divider branch includes multiple output cycles, each output cycle including an active phase T1 and an inactive phase T2; in the active phase T1, the clock signal is at an active level; in the inactive phase T2, the clock signal is at an inactive level; the voltage divider control signal CT is configured such that in any output cycle, the voltage divider control signal CT is at an active level.

[0041] At this time, the voltage divider control signal CT can turn on the voltage divider control unit 22 in any output cycle, so that the clock signal always passes through the voltage divider branch 20, thereby reducing the effective level voltage of the clock signal output by the output terminal CLK'. This helps to generate a gate scan signal with a reduced effective level using the clock signal with the reduced effective level, which in turn helps to stabilize the gate scan signal generated by the panel gate drive circuit under high temperature conditions and avoid the high temperature screen shaking phenomenon caused by the fluctuation of the gate scan signal at high temperature.

[0042] Figure 7 This is a circuit structure diagram of another clock signal conditioning circuit provided in an embodiment of the present invention, for reference. Figure 7 At least one voltage divider branch 20 includes a first voltage divider branch 23 and a second voltage divider branch 24; the capacitance value of the second capacitor C2 in the first voltage divider branch 23 is less than the capacitance value of the second capacitor C3 in the second voltage divider branch 24. Figure 8 yes Figure 7 The diagram shown is a control timing diagram of a clock signal conditioning circuit, for reference. Figure 8 The clock signal conditioning circuit includes multiple output cycles, each output cycle including an active phase T1 and an inactive phase T2. In the active phase T1, the clock signal is at an active level; in the inactive phase T2, the clock signal is at an inactive level. The active phase T1 is divided into a normal phase T3, a first voltage divider phase T5, and a second voltage divider phase T6. In the time dimension, the normal phase T3, the first voltage divider phase T5, and the second voltage divider phase T6 are arranged sequentially. The voltage divider control signal CT / CV is configured as follows: in the normal phase T3, the voltage divider control signal CT / CV is at an inactive level; in the first voltage divider phase T5, the voltage divider control signal CT in the first voltage divider branch 23 is at an active level; in the second voltage divider phase T6, the voltage divider control signal CV in the second voltage divider branch 24 is at an active level.

[0043] Specifically, in one embodiment of the present invention, under the control of voltage divider control signals CT and CV, the clock signal adjustment circuit can both bevel the clock signal and reduce the pulse width of the clock signal; in different output cycles, the duration of the first voltage divider stage T5 in the effective stage T1 is the same to ensure consistent bevel in each cycle; and since the width of the clock signal needs to be adjusted differently in each cycle, the duration of the second voltage divider stage T6 in the effective stage T1 is the same or different in different output cycles. Different durations of the second voltage divider stage T6 in the effective stage T1 correspond to clock signals with different widths, and in any output cycle, the duration of the second voltage divider stage T6 in the effective stage T1 is within the range of 0 to 100%; in the effective stage T1 of an output cycle, the voltage divider control signal lines of the first voltage divider branch 23 and the second voltage divider branch 24 provide voltage divider control signals to the voltage divider control unit 22, while in the normal stage T3 of the effective stage T1, the voltage divider control signal CT is at an invalid level, and the voltage divider control unit 22 is not turned on at this time. The clock signal output from the corresponding output terminal CLK' is not divided by the second capacitor C2; while in the first voltage division stage T5 of the effective stage T1, the voltage division control signal CT provided by the voltage division control signal line of the first voltage division branch 23 to the voltage division control unit 22 is at an effective level. At this time, under the control of the voltage division unit, the first voltage division branch 23 is turned on, and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2 in the first voltage division branch 23. After being divided by the second capacitor C2, the square wave clock signal becomes a chamfered clock signal; in the second voltage division stage T6... At this time, the voltage divider control signal CV provided by the voltage divider control signal line of the second voltage divider branch 24 to the voltage divider control unit 22 is at an effective level. Under the control of the voltage divider unit, the second voltage divider branch 24 is turned on. The capacitance value of the first capacitor C1 is less than the capacitance value of the second capacitor C3 in the second voltage divider branch 24. After voltage division by the second capacitor C3, the pulse width of the square wave clock signal decreases. The voltage divider control unit 22 in the first voltage divider branch 23 includes the first transistor Q1, and the voltage divider control unit 22 in the second voltage divider branch 24 includes the second transistor Q2.

[0044] Therefore, this embodiment can achieve the adjustment of the clock signal's chamfer and effective pulse width by setting two voltage divider branches and controlling them with the voltage divider control signals on the two voltage divider branches. This helps to solve the problem of electromagnetic interference affecting the normal operation of the display panel and stabilize the gate scanning signal generated by the panel gate drive circuit under high temperature conditions, avoiding the high-temperature screen shaking phenomenon caused by fluctuations in the gate scanning signal at high temperatures.

[0045] Based on the same concept, embodiments of the present invention also provide a display device. Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, for reference. Figure 9The display device 100 includes any of the clock signal adjustment circuits provided in the embodiments of the present invention (not shown in the figure). Since the display device 100 includes the clock signal adjustment circuits provided in the embodiments of the present invention, it has the same or similar beneficial effects as the clock signal adjustment circuits provided in the embodiments of the present invention, which will not be described in detail here.

[0046] In one embodiment of the present invention, as described above Figure 7 As shown, its clock signal conditioning circuit also includes at least one voltage divider control signal generation circuit, which generates a voltage divider control signal CT. The voltage divider control signal generation circuit is electrically connected to the control terminal of the voltage divider control unit on a voltage divider branch via a voltage divider control signal line. The voltage divider branch includes multiple output cycles, each output cycle including an active phase T1 and an inactive phase T2. In the active phase T1, the clock signal is at an active level; in the inactive phase T2, the clock signal is at an inactive level. The active phase T1 is divided into a normal phase T3 and a voltage divider phase T4, with the voltage divider phase T4 following the normal phase T3 in the time dimension. The voltage divider control signal CT is configured such that: in the normal phase T3, the voltage divider control signal CT is at an inactive level; and in the voltage divider phase T4, the voltage divider control signal CT is at an active level.

[0047] Based on the above embodiments, refer to Figure 9 The display device 100 also includes a display panel 110 and a driver chip 120. In one embodiment of the present invention, when the duration of the voltage dividing stage T4 in the effective stage T1 is the same in different output cycles of the voltage dividing branch, since the effective stage T1 of the clock signal output by the output terminal CLK' has the same chamfer, the required periodic control signal is simple, and the voltage dividing control signal CT generation circuit 130 electrically connected to the voltage dividing branch can be integrated into the display panel 110.

[0048] Figure 10 This is a schematic diagram of a display device according to another embodiment of the present invention. In another embodiment of the present invention, when the duration of the voltage dividing stage T4 in the effective stage T1 is different in at least a portion of the output cycle of the voltage dividing branch, the reference... Figure 10 Since the timing of the voltage divider control signal CV is relatively complex and the non-periodic signal is quite special, the voltage divider control signal CV generation circuit 130, which is electrically connected to the voltage divider branch, is integrated into the driver chip 120.

[0049] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A clock signal conditioning circuit, characterized in that, Includes an input terminal, an output terminal, a first capacitor, and at least one voltage divider branch; The first capacitor is connected between the input terminal and the output terminal; The at least one voltage divider branch is connected between the output terminal and the ground terminal, and the voltage divider branch includes a second capacitor and a voltage divider control unit connected in series. The control terminal of the voltage divider control unit is electrically connected to the voltage divider control signal line. The voltage divider control unit is configured to turn on or off under the control of the voltage divider control signal provided by the voltage divider control signal line, so as to turn on or off the voltage divider branch. The voltage divider branch includes multiple output cycles, each output cycle including an active phase and an inactive phase; during the active phase, the clock signal is at an active level; during the inactive phase, the clock signal is at an inactive level. The effective phase is divided into a normal phase and a voltage divider phase, with the voltage divider phase following the normal phase in the time dimension; the voltage divider control signal is configured such that: in the normal phase, the voltage divider control signal is at an invalid level; and in the voltage divider phase, the voltage divider control signal is at an effective level.

2. The clock signal conditioning circuit according to claim 1, characterized in that, In different output cycles, the duration of the voltage dividing phase in the effective phase is the same.

3. The clock signal conditioning circuit according to claim 2, characterized in that, The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

4. The clock signal conditioning circuit according to claim 1, characterized in that, In different output cycles, the duration of the voltage dividing phase in the effective phase may be the same or different, and in any one output cycle, the duration of the voltage dividing phase in the effective phase is in the range of 0 to 100%.

5. The clock signal conditioning circuit according to claim 4, characterized in that, The capacitance value of the first capacitor is less than the capacitance value of the second capacitor.

6. The clock signal conditioning circuit according to claim 5, characterized in that, The ratio of the capacitance value of the second capacitor to the capacitance value of the first capacitor is greater than or equal to 9.

7. The clock signal conditioning circuit according to claim 1, characterized in that, The voltage divider control unit includes transistors.

8. The clock signal conditioning circuit according to claim 1, characterized in that, At least one voltage divider branch includes a first voltage divider branch and a second voltage divider branch; The capacitance value of the second capacitor in the first voltage divider branch is less than the capacitance value of the second capacitor in the second voltage divider branch.

9. The clock signal conditioning circuit according to claim 8, characterized in that, The clock signal conditioning circuit includes multiple output cycles, each output cycle including an active phase and an inactive phase; during the active phase, the clock signal is at an active level; during the inactive phase, the clock signal is at an inactive level. The effective phase is divided into a normal phase, a first voltage division phase, and a second voltage division phase, which are arranged sequentially in the time dimension. The voltage divider control signal is configured such that: in the normal phase, the voltage divider control signal is at an invalid level; in the first voltage divider phase, the voltage divider control signal in the first voltage divider branch is at an active level; and in the second voltage divider phase, the voltage divider control signal in the second voltage divider branch is at an active level.

10. The clock signal conditioning circuit according to claim 9, characterized in that, In different output cycles, the duration of the first voltage division phase in the effective phase is the same. In different output cycles, the duration of the second voltage divider phase in the effective phase may be the same or different, and in any one output cycle, the duration of the second voltage divider phase in the effective phase is in the range of 0 to 100%.

11. The clock signal conditioning circuit according to claim 10, characterized in that, The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor in the first voltage divider branch, and the capacitance value of the first capacitor is less than the capacitance value of the second capacitor in the second voltage divider branch.

12. The clock signal conditioning circuit according to claim 10, characterized in that, The voltage divider control unit in the first voltage divider branch includes a first transistor, and the voltage divider control unit in the second voltage divider branch includes a second transistor.

13. The clock signal conditioning circuit according to claim 1, characterized in that, It also includes at least one voltage divider control signal generation circuit, which is used to generate the voltage divider control signal; The voltage divider control signal generation circuit is electrically connected to the control terminal of the voltage divider control unit on one of the voltage divider branches via the voltage divider control signal line.

14. A display device, characterized in that, Includes the clock signal conditioning circuit as described in any one of claims 1-13.

15. The display device according to claim 14, characterized in that, The display device also includes a display panel and a driver chip; The clock signal conditioning circuit further includes at least one voltage divider control signal generation circuit, which is used to generate the voltage divider control signal. The voltage divider control signal generation circuit is electrically connected to the control terminal of the voltage divider control unit on one of the voltage divider branches via the voltage divider control signal line. The voltage divider branch includes multiple output cycles, each output cycle including an active phase and an inactive phase; during the active phase, the clock signal is at an active level; during the inactive phase, the clock signal is at an inactive level. The effective phase is divided into a normal phase and a pressure-dividing phase, with the pressure-dividing phase occurring after the normal phase in the time dimension. The voltage divider control signal is configured such that: during the normal phase, the voltage divider control signal is at an invalid level; and during the voltage divider phase, the voltage divider control signal is at an active level. When the duration of the voltage dividing phase in the effective phase is the same in different output cycles of the voltage dividing branch, the voltage dividing control signal generation circuit corresponding to the voltage dividing branch is integrated into the display panel. When the duration of the voltage dividing phase in the effective phase differs in at least a portion of the output cycle of the voltage dividing branch, the voltage dividing control signal generation circuit correspondingly connected to the voltage dividing branch is integrated into the driver chip.

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