Display apparatus and method of operating the same

Abstract

A display device and an operating method thereof are disclosed. A display device includes a first pixel circuit, a second pixel circuit, a first gate line, a second gate line, a first transfer line, and a second transfer line. The first pixel circuit is to emit light in accordance with a data signal and to charge in accordance with a first gate signal. The second pixel circuit is to emit light in accordance with the data signal and to charge in accordance with a second gate signal. The first gate line is between the first pixel circuit and the second pixel circuit and is to provide the first gate signal. The second gate line is to provide the second gate signal. The first transfer line is to provide the second gate signal to the second gate line. The second transfer line is between the first transfer line and the second pixel circuit, across the second gate line, and is to provide the first gate signal to the first gate line.

Description

Technical Field

[0001] This disclosure relates to a display technology, and more particularly to a display device and a method of operating the display device. Background Technology

[0002] In a display device, the pixel circuits emit light according to corresponding gate signals. However, capacitive coupling between the gate lines transmitting the gate signals and the pixel circuits and data lines can cause abnormal brightness in the display device. Therefore, designing a solution to this problem is an important issue in this field. Summary of the Invention

[0003] This invention includes a display device. The display device includes a first pixel circuit, a second pixel circuit, a first gate line, a second gate line, a first transmission line, and a second transmission line. The first pixel circuit is used to emit light according to a data signal and to charge according to a first gate signal. The second pixel circuit is used to emit light according to the data signal and to charge according to a second gate signal. The first gate line is located between the first pixel circuit and the second pixel circuit and is used to provide a first gate signal. The second gate line is used to provide a second gate signal. The first transmission line is used to provide the second gate signal to the second gate line. The second transmission line is located between the first transmission line and the second pixel circuit, crosses the second gate line, and is used to provide the first gate signal to the first gate line.

[0004] This invention includes an operating method for a display device. The operating method includes: at a first moment, adjusting a first gate signal on a first transmission line from a first voltage level to a second voltage level to maintain a voltage level on a data line capacitively coupled to the first transmission line; at the first moment, adjusting a second gate signal on a second transmission line from a second voltage level to a first voltage level to maintain a voltage level on a data line capacitively coupled to the second transmission line; after the first moment, charging a first pixel circuit based on the second gate signal and a data signal on the data line; and before the first moment, charging a second pixel circuit based on the first gate signal and the data signal. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0006] Figure 2 As illustrated in one embodiment of this case Figure 1 A schematic diagram showing further details of the display device.

[0007] Figure 3 As illustrated in one embodiment of this case Figure 1 The timing diagram for the operation of the display device is shown.

[0008] Figure 4 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0009] Figure 5 As illustrated in one embodiment of this case Figure 4 The timing diagram for the operation of the display device is shown.

[0010] Figure 6 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0011] Figure 7 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0012] Figure 8 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0013] Symbol Explanation

[0014] 100, 400, 600, 700, 800: Display devices

[0015] 110, 130: Edge areas

[0016] 120: Illuminated area

[0017] X, Y: Direction

[0018] L11: Length

[0019] HG1~HG4, HG42, HG43: Gate lines

[0020] VG2, VG3, VG42, VG43, VG62, VG63, VG81: Transmission lines

[0021] LDT1, LDT2, LDT4: Data cables

[0022] LVS1, LVS2, LVS81: Reference voltage lines

[0023] VS2, VS3, VS81: Through-hole structure

[0024] SS1~SS8: Source structure

[0025] B1~B4, R1~R4, B41~B417: Pixel circuit

[0026] VSS: Reference voltage signal

[0027] LDP1~LDP5, LDP7, LDP41~LDP44: Data cable section

[0028] DS1~DS8: Drain structure

[0029] T1~T8: Transistors

[0030] SG1~SG4, SG42, SG43: Gate signals

[0031] DT1, DT2, DT4: Data signals

[0032] 300, 500: Timing Diagram

[0033] P31~P34, P51~P54: Period

[0034] M31~M35, M51~M53: Timetable

[0035] VH, VL, VD1~VD4: Voltage levels

[0036] RC1, GC1, BC1, RC2, GC2, BC2: Pixel circuit array Detailed Implementation

[0037] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the scope of this application.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this case pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context and this case, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0040] The following describes several embodiments of this invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the invention. That is, these practical details are not essential in some embodiments of this disclosure. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0041] Figure 1 This is a schematic diagram illustrating a display device 100 according to an embodiment of this case. Figure 1 As shown, the display device 100 includes edge regions 110 and 130 and a light-emitting region 120. The edge regions 130, 120, and 110 are arranged sequentially in the Y direction. The light-emitting region 120 has a length L11 in the Y direction.

[0042] In some embodiments, the display device 100 further includes various circuits, such as light-emitting circuits and control circuits. The control circuits are used to generate data signals (e.g., Figure 2 The data signals DT1 and DT2 are shown. A light-emitting circuit is used to emit light according to the data signals. In some embodiments, the light-emitting circuit is located in the light-emitting region 120, and the control circuit is located in the edge regions 110 and / or 130. In some embodiments, the circuit located in the edge regions 110 or 130 does not emit light.

[0043] Figure 2 As illustrated in one embodiment of this case Figure 1 A schematic diagram showing further details of the display device 100. (See attached diagram.) Figure 2 As shown, the display device 100 includes gate lines HG1 to HG4, transmission lines VG2 and VG3, data lines LDT1 and LDT2, reference voltage lines LVS1 and LVS2, through-hole structures VS2 and VS3, source structures SS1 to SS8, and pixel circuits B1 to B4 and R1 to R4.

[0044] like Figure 2 As shown, each of the gate lines HG1 to HG4 extends in the X direction, and the gate lines HG1 to HG4 are arranged sequentially in the Y direction. In some embodiments, the X direction is perpendicular to the Y direction.

[0045] like Figure 2 As shown, transmission line VG2 extends in the Y direction and crosses gate lines HG3 and HG4. Transmission line VG3 extends in the Y direction and crosses gate line HG4. Reference voltage line LVS1 extends in the Y direction and crosses gate line HG1. Reference voltage line LVS2 extends in the Y direction and crosses gate lines HG1 and HG2.

[0046] In some embodiments, reference voltage lines LVS1 and LVS2 are used to provide a reference voltage signal VSS to at least one of pixel circuits B1-B4 and R1-R4. In some embodiments, the reference voltage signal VSS has a fixed voltage value, such that reference voltage lines LVS1 and LVS2 do not capacitively couple with other components.

[0047] like Figure 2 As shown, via structure VS2 is located above gate line HG2 and is used to couple gate line HG2 and transmission line VG2, so that gate line HG2 and transmission line VG2 have the same voltage level. Via structure VS3 is located above gate line HG3 and is used to couple gate line HG3 and transmission line VG3, so that gate line HG3 and transmission line VG3 have the same voltage level.

[0048] like Figure 2 As shown, pixel circuits B1 to B4 are arranged sequentially in the Y direction, and pixel circuits R1 to R4 are also arranged sequentially. Each of pixel circuits B2 and R2 is located between gate lines HG1 and HG2. Each of pixel circuits B3 and R3 is located between gate lines HG2 and HG3. Each of pixel circuits B4 and R4 is located between gate lines HG3 and HG4.

[0049] like Figure 2 As shown, source structure SS1 is coupled to each of gate line HG1 and pixel circuit B1. Source structure SS2 is coupled to each of gate line HG2 and pixel circuit B2. Source structure SS3 is coupled to each of gate line HG3 and pixel circuit B3. Source structure SS4 is coupled to each of gate line HG4 and pixel circuit B4. Source structure SS5 is coupled to each of gate line HG1 and pixel circuit R1. Source structure SS6 is coupled to each of gate line HG2 and pixel circuit R2. Source structure SS7 is coupled to each of gate line HG3 and pixel circuit R3. Source structure SS8 is coupled to each of gate line HG4 and pixel circuit R4.

[0050] like Figure 2As shown, the data line LDT1 includes data line portions LDP1 to LDP4 and drain structures DS1 to DS4. The drain structures DS1 to DS4 are located above the gate lines HG1 to HG4, respectively. In the X direction, each of the data line portions LDP1 to LDP4 is located between two columns of pixel circuits. For example, in... Figure 2 In the embodiment shown, each of the data line portions LDP1 to LDP4 is located between a column of pixel circuits containing pixel circuits B1 to B4 and another column of pixel circuits containing pixel circuits R1 to R4.

[0051] like Figure 2 As shown, each of the data line portions LDP1 and LDP2 extends in the Y direction and crosses each of the gate lines HG1 to HG4. In the X direction, the data line portion LDP1, transmission lines VG2, VG3, and data line portion LDP2 are arranged sequentially. In some embodiments, the distance between transmission line VG2 and data line portion LDP1 is less than the distance between transmission line VG2 and data line portion LDP2, and the distance between transmission line VG3 and data line portion LDP2 is less than the distance between transmission line VG3 and data line portion LDP1.

[0052] like Figure 2 As shown, each of the data line portions LDP3 and LDP4 extends in the X direction. Data line portion LDP3 is used to couple one end of data line portions LDP1 and LDP2, and data line portion LDP4 is used to couple the other end of data line portions LDP1 and LDP2. In the Y direction, each of the gate lines HG1 to HG4 is located between data line portions LDP3 and LDP4.

[0053] In some variations, data line LDT1 may not include data line portion LDP4. In the above variations, data line portions LDP1 and LDP2 are coupled to each other only via data line portion LDP3.

[0054] Please refer to Figure 2 and Figure 1 In some embodiments, data line portions LDP3 and LDP4 are located in edge regions 110 and 130, respectively. One end of each of data line portions LDP1 and LDP2 is located in edge region 110, and the other end of each of data line portions LDP1 and LDP2 is located in edge region 130. The length of each of data line portions LDP1 and LDP2 in the Y direction is greater than the length L11.

[0055] like Figure 2As shown, the data line LDT2 includes a data line portion LDP5 and drain structures DS5 to DS8. The drain structures DS5 to DS8 are located on the gate lines HG1 to HG4, respectively. The data line portion LDP5 extends in the Y direction and crosses each of the gate lines HG1 to HG4.

[0056] In some embodiments, gate lines HG1-HG4, drain structures DS1-DS8, and source structures SS1-SS8 are used to operate corresponding transistors. For example... Figure 2 As shown, gate line HG1, drain structure DS1, and source structure SS1 correspond to transistor T1. Gate line HG2, drain structure DS2, and source structure SS2 correspond to transistor T2. Gate line HG3, drain structure DS3, and source structure SS3 correspond to transistor T3. Gate line HG4, drain structure DS4, and source structure SS4 correspond to transistor T4. Gate line HG1, drain structure DS5, and source structure SS5 correspond to transistor T5. Gate line HG2, drain structure DS6, and source structure SS6 correspond to transistor T6. Gate line HG3, drain structure DS7, and source structure SS7 correspond to transistor T7. Gate line HG4, drain structure DS8, and source structure SS8 correspond to transistor T8.

[0057] In some embodiments, transmission line VG2 is used to transmit the gate signal SG2 to gate line HG2 through via structure VS2. Transmission line VG3 is used to transmit the gate signal SG3 to gate line HG3 through via structure VS3. In some embodiments, gate line HG1 is used to receive the gate signal SG1 from a transmission line different from transmission lines VG2 and VG3. Gate line HG4 is used to receive the gate signal SG4 from a transmission line different from transmission lines VG2 and VG3.

[0058] In some embodiments, data lines LDT1 and LDT2 are used to receive data signals DT1 and DT2, respectively. Transistor T1 is used to provide data signal DT1 to pixel circuit B1 according to gate signal SG1. Transistor T2 is used to provide data signal DT1 to pixel circuit B2 according to gate signal SG2. Transistor T3 is used to provide data signal DT1 to pixel circuit B3 according to gate signal SG3. Transistor T4 is used to provide data signal DT1 to pixel circuit B4 according to gate signal SG4. Each of pixel circuits B1 to B4 emits light according to data signal DT1.

[0059] In some embodiments, the data line LDT1 is capacitively coupled to each of the transmission lines VG2 and VG3, such that the voltage level of the data signal DT1 is affected by the voltage level changes of the gate signals SG2 and / or SG3.

[0060] In some embodiments, transistor T5 is used to provide data signal DT2 to pixel circuit R1 according to gate signal SG1. Transistor T6 is used to provide data signal DT2 to pixel circuit R2 according to gate signal SG2. Transistor T7 is used to provide data signal DT2 to pixel circuit R3 according to gate signal SG3. Transistor T8 is used to provide data signal DT2 to pixel circuit R4 according to gate signal SG4. Each of pixel circuits R1 to R4 emits light according to data signal DT2.

[0061] Figure 3 As illustrated in one embodiment of this case Figure 1 The timing diagram 300 shows the operation of the display device 100. (See diagram 300 for details.) Figure 3 As shown, the timing diagram 300 includes sequentially arranged periods P31 to P34. Period P31 begins at time M31 and ends at time M32. Period P32 begins at time M32 and ends at time M33. Period P33 begins at time M33 and ends at time M34. Period P34 begins at time M34 and ends at time M35.

[0062] like Figure 3 As shown, during periods P31 to P34, gate signals SG1 to SG4 vary between voltage levels VH and VL. Data signal DT1 has approximately voltage levels VD1 to VD4 during periods P31 to P34. In some embodiments, voltage level VH is greater than voltage level VL. Please refer to... Figure 2 and Figure 3 For each of transistors T1 to T8, voltage level VL is the disable voltage level, and voltage level VH is the enable voltage level. In other words, each of transistors T1 to T8 is turned off according to voltage level VL and turned on according to voltage level VH.

[0063] At time M31, the gate signal SG1 changes from voltage level VL to voltage level VH, causing pixel circuit B1 to begin charging. In some embodiments, the transmission line used to transmit the gate signal SG1 to the gate line SG1 is located far from pixel circuits B1-B4 and data line LDT1, for example, separated by the width of two or more pixel circuits in the X direction, so that the voltage level change of the gate signal SG1 does not affect the voltage level of pixel circuits B1-B4 and data line LDT1 via capacitive coupling. Correspondingly, at time M31, the voltage level of pixel circuits B1-B4 and data line LDT1 remains unchanged.

[0064] During period P31, the gate signal SG1 has a voltage level VH, causing each of transistors T1 and T5 to conduct. At this time, pixel circuit B1 is charged according to data signal DT1 with a data voltage level VD1, and pixel circuit R1 is charged according to data signal DT2.

[0065] At time M32, gate signal SG1 changes from voltage level VH to voltage level VL, and gate signal SG2 changes from voltage level VL to voltage level VH, causing pixel circuit B1 to stop charging and pixel circuit B2 to start charging. After time M32, pixel circuit B1 emits light according to data voltage level VD1.

[0066] In some embodiments, at time M32, the voltage level of transmission line VG2 is pulled high by gate signal SG2, and affects the voltage level of data line portion LDP1 via capacitive coupling, causing the voltage level of pixel circuit B1 to be pulled high.

[0067] During period P32, the gate signal SG2 has a voltage level VH, causing each of transistors T2 and T6 to conduct. At this time, pixel circuit B2 is charged according to data signal DT1 with a data voltage level VD2, and pixel circuit R2 is charged according to data signal DT2.

[0068] At time M33, gate signal SG2 changes from voltage level VH to voltage level VL, and gate signal SG3 changes from voltage level VL to voltage level VH, causing pixel circuit B2 to stop charging and pixel circuit B3 to start charging. At this time, the voltage level of transmission line VG2 is pulled low by gate signal SG2, and the voltage level of data line LDP1 is pulled low via capacitive coupling. On the other hand, the voltage level of transmission line VG3 is pulled high by gate signal SG3, and the voltage level of data line LDP2 is pulled high via capacitive coupling. Correspondingly, the pulling low of gate signal SG2 and the pulling high of gate signal SG3 cancel each other out on data line LDT1, causing data line LDT1 to remain at voltage level VD2. At this time, the voltage level of pixel circuit B2 coupled to data line LDT1 also remains unchanged. After time M33, pixel circuit B2 emits light according to the data voltage level VD2.

[0069] During period P33, the gate signal SG3 has a voltage level VH, causing each of transistors T3 and T7 to conduct. At this time, pixel circuit B3 is charged according to data signal DT1 with a data voltage level VD3, and pixel circuit R3 is charged according to data signal DT2.

[0070] At time M34, gate signal SG3 changes from voltage level VH to voltage level VL, and gate signal SG4 changes from voltage level VL to voltage level VH, causing pixel circuit B3 to stop charging and pixel circuit B4 to start charging. At this time, transmission line VG3 does not capacitively couple with either pixel circuits B3 or B4, allowing pixel circuit B3 to maintain the data voltage level VD3, and minimizing the impact on pixel circuit B4 during charging after time M34. After time M34, pixel circuit B3 emits light according to the data voltage level VD3.

[0071] In some embodiments, at time M34, transmission line VG3 is not capacitively coupled to either pixel circuits B3 or B4 because the distance between transmission line VG3 and either pixel circuits B3 or B4 is relatively large. For example, the distance between transmission line VG3 and pixel circuit B3 is greater than the distance between transmission line VG2 and pixel circuit B3. Correspondingly, the capacitive coupling between transmission line VG3 and pixel circuit B3 is less than the capacitive coupling between transmission line VG2 and pixel circuit B3.

[0072] In some implementations, the arrangement of the transmission lines providing the gate signals in the display device is poor, resulting in a small distance between the transmission lines and the pixel circuitry. Consequently, during the pixel circuitry's charging operation, capacitive coupling occurs simultaneously between the transmission lines and the pixel circuitry, as well as between the transmission lines and the data lines, severely pulling down the voltage level of the pixel circuitry. This leads to abnormal brightness issues in the display device.

[0073] Compared to the above approach, in some embodiments of this disclosure, the pixel circuit B4, the data line portion LDP1, and the transmission lines VG2 and VG3 are arranged sequentially in the X direction, such that the distance between the transmission line VG3 and the pixel circuit B4 is relatively large. As a result, the voltage level of the pixel circuit B4 is not affected by changes in the voltage level of the transmission line VG3. Correspondingly, the brightness of the display device 100 is abnormally reduced.

[0074] like Figure 3 As shown, during period P34, the gate signal SG4 has a voltage level VH, causing each of transistors T4 and T8 to conduct. At this time, pixel circuit B4 is charged according to data signal DT1 with a data voltage level VD4, and pixel circuit R4 is charged according to data signal DT2.

[0075] At time M35, the gate signal SG4 changes from voltage level VH to voltage level VL, causing pixel circuit B4 to stop charging. After time M35, pixel circuit B4 emits light according to data voltage level VD4.

[0076] Figure 4This is a schematic diagram illustrating a display device 400 according to an embodiment of this case. Figure 4 As shown, the display device 400 includes gate lines HG42, HG43, transmission lines VG42, VG43, data line LDT4, and pixel circuit arrays RC1, GC1, BC1, RC2, GC2, and BC2.

[0077] In some embodiments, pixel circuit arrays RC1 and RC2 are used to emit red light, pixel circuit arrays GC1 and GC2 are used to emit green light, and pixel circuit arrays BC1 and BC2 are used to emit blue light. In various embodiments, pixel circuit arrays RC1, GC1, BC1, RC2, GC2, and BC2 can emit light of various colors.

[0078] like Figure 4 As shown, each of gate lines HG42 and HG43 extends in the X direction, and gate lines HG42 and HG43 are arranged sequentially in the Y direction. Transmission line VG42 extends in the Y direction and is coupled to gate line HG42. Transmission line VG43 extends in the Y direction and is coupled to gate line HG43.

[0079] like Figure 4 As shown, transmission line VG42 receives the gate signal SG42 and transmits it to gate line HG42. Transmission line VG43 receives the gate signal SG43 and transmits it to gate line HG43. Data line LDT4 receives the data signal DT4.

[0080] like Figure 4 As shown, data line LDT4 comprises data line portions LDP41 to LDP44. In the X direction, each of data line portions LDP41 to LDP44 is located between pixel circuit columns BC1 and RC2. Each of data line portions LDP41 and LDP42 extends in the Y direction. In the X direction, data line portion LDP41, transmission lines VG42, VG43, and data line portion LDP42 are arranged sequentially.

[0081] like Figure 4 As shown, each of the data line portions LDP43 and LDP44 extends in the X direction. Data line portion LDP43 is used to couple one end of data line portions LDP41 and LDP42, and data line portion LDP44 is used to couple the other end of data line portions LDP41 and LDP42. In the Y direction, pixel circuit arrays RC1, GC1, BC1, RC2, GC2, and BC2 are located between data line portions LDP43 and LDP44.

[0082] Please refer to Figure 4 and Figure 1In some embodiments, data line portions LDP43 and LDP44 are located in edge regions 110 and 130, respectively. One end of each of data line portions LDP41 and LDP42 is located in edge region 110, and the other end of each of data line portions LDP41 and LDP42 is located in edge region 130. The length of each of data line portions LDP41 and LDP42 in the Y direction is greater than the length L11.

[0083] like Figure 4 As shown, pixel circuit array BC1 includes pixel circuits B41 to B417. Pixel circuits B41 to B417 are arranged sequentially in the Y direction. Each of pixel circuits B41 to B417 is coupled to the data line portion LDP41. Pixel circuits B47 and B412 are coupled to gate lines HG42 and HG43, respectively.

[0084] Please refer to Figure 4 and Figure 2 The display device 400 is a variation of the display device 100. Gate lines HG42 and HG43, transmission lines VG42 and VG43, and data line LDT4 correspond to gate lines HG2 and HG3, transmission lines VG2 and VG3, and data line LDT1, respectively. Data lines LDP41 to LDP44 correspond to LDP1 to LDP4, respectively. Gate signals SG42 and SG43, and data signal DT4 correspond to gate signals SG2 and SG3, and data signal DT1, respectively. Pixel circuits B47 and B412 correspond to pixel circuits B2 and B3, respectively. Therefore, some descriptions will not be repeated.

[0085] Figure 5 As illustrated in one embodiment of this case Figure 4 The timing diagram 500 shows the operation of the display device 400. (See diagram 500 for details.) Figure 5 As shown, the timing diagram 500 includes sequentially arranged periods P51 to P54. Period P51 begins at time M51. Period P52 ends at time M52, and period P53 begins at time M52. Period P54 ends at time M53.

[0086] Before time M51, the gate lines (not shown) corresponding to pixel circuits B41 to B46 are sequentially changed from voltage level VL to voltage level VH. At time M51, the gate signal SG42 changes from voltage level VL to voltage level VH. In some embodiments, due to the capacitive coupling between transmission line VG42 and data line portion LDP41, the data signal DT4 is slightly pulled high at time M51.

[0087] During periods P51-P52, the gate signal SG42 has a voltage level VH. During period P51, pixel circuits B43-B46 are sequentially charged according to data signal DT4 and sequentially begin emitting light. During period P52, pixel circuit B47 is charged according to data signal DT4. In some embodiments, period P51 is referred to as the pre-charge period of pixel circuit B47, and period P52 is referred to as the main-charge period of pixel circuit B47.

[0088] Before time M52, the gate lines (not shown) corresponding to pixel circuits B48 to B411 sequentially change from voltage level VL to voltage level VH. At time M52, gate signal SG42 changes from voltage level VH to voltage level VL, and gate signal SG43 changes from voltage level VL to voltage level VH. At this time, the voltage level of transmission line VG42 is pulled low by gate signal SG42, and affects the voltage level of data line LDP41 via capacitive coupling. On the other hand, the voltage level of transmission line VG43 is pulled high by gate signal SG43, and affects the voltage level of data line LDP42 via capacitive coupling. Correspondingly, the pulling low of gate signal SG42 and the pulling high of gate signal SG43 cancel each other out on data line LDT4, so that the voltage level of data line LDT4 remains unchanged. At this time, the voltage level of pixel circuit B47 coupled to data line LDT4 also remains unchanged. After time M52, pixel circuit B47 begins to emit light.

[0089] During periods P53-P54, gate signal SG43 has a voltage level VH. During period P53, pixel circuits B48-B411 are sequentially charged according to data signal DT4 and sequentially begin emitting light. During period P54, pixel circuit B412 is charged according to data signal DT4. In some embodiments, period P53 is referred to as the pre-charging period of pixel circuit B412, and period P54 is referred to as the main charging period of pixel circuit B412.

[0090] At time M53, the gate signal SG43 changes from voltage level VH to voltage level VL. In some embodiments, due to the capacitive coupling between the transmission line VG43 and the data line portion LDP42, the data signal DT4 is slightly pulled low at time M53. After time M53, the pixel circuit B412 begins to emit light.

[0091] Figure 6 This is a schematic diagram illustrating a display device 600 according to an embodiment of this case. Please refer to... Figure 2 and Figure 6The display device 600 is a variation of the display device 200. Some components of the display device 600 use the same designation as those of the display device 200. For the sake of brevity, the discussion will focus on the parts of the display device 600 that differ from the display device 200, rather than their similarities.

[0092] Please refer to Figure 2 and Figure 6 Compared to display device 200, display device 600 includes transmission lines VG62 and VG63 instead of transmission lines VG2 and VG3. Transmission lines VG62 and VG63 are variations of transmission lines VG2 and VG3, respectively. Therefore, some details will not be repeated.

[0093] like Figure 6 As shown, each of transmission lines VG62 and VG63 extends in the Y direction and crosses gate lines HG1 to HG4. Data line portion LDP1, transmission lines VG62 and VG63, and data line portion LDP2 are arranged sequentially in the X direction. Transmission line VG62 is used to transmit the gate signal SG2 to gate line HG2. Transmission line VG63 is used to transmit the gate signal SG3 to gate line HG3.

[0094] Please refer to Figure 3 and Figure 6 In some embodiments, the display device 600 operates according to timing diagram 300. At time M33, the voltage level of transmission line VG62 is pulled low by gate signal SG2, and this affects the voltage level of data line portion LDP1 via capacitive coupling. On the other hand, the voltage level of transmission line VG63 is pulled high by gate signal SG3, and this also affects the voltage level of data line portion LDP2 via capacitive coupling. Correspondingly, the pulling low of gate signal SG2 and the pulling high of gate signal SG3 cancel each other out on data line LDT1, causing data line LDT1 to remain at voltage level VD2.

[0095] In some embodiments, the longer the transmission lines VG62 and VG63 are, the stronger the capacitive coupling between the transmission lines VG62 and VG63 and the data line LDT1. Correspondingly, the transmission lines VG62 and VG63 can influence the data line LDT1 more quickly, allowing the data line LDT1 to be maintained more stably at the voltage level VD2.

[0096] Figure 7 This is a schematic diagram illustrating a display device 700 according to an embodiment of this case. Please refer to... Figure 2 and Figure 7 The display device 700 is a variation of the display device 200. Some components of the display device 700 use the same designation as those of the display device 200. For the sake of simplicity, the discussion will focus on the parts of the display device 700 that differ from the display device 200, rather than their similarities.

[0097] Please refer to Figure 2 and Figure 7 Compared to display device 200, display device 700 also includes a data cable section LDP7. For example... Figure 7 As shown, the data line portion LDP7 extends in the Y direction and crosses gate lines HG1 to HG4. Data line portion LDP1, transmission line VG62, data line portion LDP7, transmission line VG3, and data line portion LDP2 are arranged sequentially in the X direction. One end of data line portion LDP7 is coupled to data line portion LDP3, and the other end of data line portion LDP7 is coupled to data line portion LDP4. In some embodiments, data line portion LDP7 is included within data line LDT1.

[0098] In some embodiments, the data line portion LDP7 is capacitively coupled to each of the transmission lines VG2 and VG3. Please refer to... Figure 3 and Figure 7 In some embodiments, the display device 700 operates according to timing diagram 300. At time M33, in response to the gate signal SG2 being pulled low, transmission line VG2 pulls down the voltage level of the data line portion LDP7, and in response to the gate signal SG3 being pulled high, transmission line VG3 pulls up the voltage level of the data line portion LDP7. Correspondingly, the pulling down of the gate signal SG2 and the pulling up of the gate signal SG3 cancel each other out on the data line portion LDP7, so that the voltage level of the data line LDT1 remains unchanged.

[0099] Figure 8 This is a schematic diagram illustrating a display device 800 according to one embodiment of this case. Please refer to... Figure 2 and Figure 8 The display device 800 is a variation of the display device 200. Some components of the display device 800 use the same numbering system as the display device 200. For the sake of simplicity, the discussion will focus on the parts of the display device 800 that differ from the display device 200, rather than their similarities.

[0100] Please refer to Figure 2 and Figure 8 Compared to display device 200, display device 800 further includes transmission line VG81, through-hole structure VS81, and reference voltage line LVS81. For example... Figure 8 As shown, transmission line VG81 extends in the Y direction, crossing gate lines HG2 to HG4. In the X direction, transmission lines VG2, VG81, and VG3 are arranged sequentially. Via structure VS81 is located above gate line HG1 and couples gate line HG1 and transmission line VG81. Reference voltage line LVS81 is located between reference voltage lines LVS1 and LVS2.

[0101] In some embodiments, transmission line VG81 is used to receive gate signal SG1 and to transmit gate signal SG1 to gate line HG1 through via structure VS81. Reference voltage line LVS81 is used to provide reference voltage signal VSS.

[0102] Please refer to Figure 3 and Figure 8 In some embodiments, the display device 800 operates according to timing diagram 300. For example... Figure 8 As shown, transmission line VG81 is located between transmission lines VG2 and VG3. Compared to transmission lines VG2 and VG3, transmission line VG81 is farther away from data line LDT1, pixel circuits B1-B4, and resistors R1-R4. Correspondingly, when the display device 800 is operating, changes in the voltage level of transmission line VG81 do not affect data line LDT1, pixel circuits B1-B4, and resistors R1-R4.

[0103] Please refer to Figure 2 and Figure 8 The display device 800 can be implemented in a larger size, and the display device 200 can be implemented in a smaller size. For example, the display device 800 corresponds to a 75-inch or 85-inch screen, and the display device 200 corresponds to a 65-inch screen.

[0104] Although this disclosure has been disclosed above with reference to embodiments, it is not intended to limit the scope of this disclosure. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A display device, comprising: The first pixel circuit (B2) is used to emit light according to the data signal and to charge according to the first gate signal (SG2); The second pixel circuit (B3) is used to emit light according to the data signal and to charge according to the second gate signal (SG3); Data lines (LDT1, LDT2) are used to transmit the data signals (DT1, DT2); The first gate line (HG2) is located between the first pixel circuit (B2) and the second pixel circuit (B3) and is used to provide the first gate signal; The second gate line (HG3) is used to provide the second gate signal; The first transmission line (VG3) is used to provide the second gate signal to the second gate line; as well as The second transmission line (VG2) is located between the first transmission line and the second pixel circuit, spans the second gate line, and is used to provide the first gate signal to the first gate line. The data line is capacitively coupled to the first transmission line and the second transmission line.

2. The display device as claimed in claim 1, wherein the data cable comprises: The first data line portion (LDP1) spans each of the first gate line and the second gate line; and The second data line portion (LDP2) is coupled to the first data line portion and spans each of the first gate line and the second gate line. The first data line portion, the second transmission line, the first transmission line, and the second data line portion are arranged in sequence.

3. The display device as claimed in claim 2, wherein the data cable further comprises: The third data line section (LDP3) is used to couple the first end of the first data line section and the first end of the second data line section; and The fourth data line section (LDP4) is used to couple the second end of the first data line section and the second end of the second data line section. Each of the first gate line and the second gate line is located between the third data line portion and the fourth data line portion.

4. The display device as claimed in claim 2, wherein the data cable further comprises: The fifth data line portion (LDP7) is coupled to the first data line portion and the second data line portion, and is located between the first transmission line and the second transmission line.

5. The display device as claimed in claim 1, further comprising: The third pixel circuit (B1) is used to emit light according to the data signal and to charge according to the third gate signal; and The third transmission line (VG81) is located between the first transmission line and the second transmission line, spanning each of the first gate line and the second gate line, and is used to provide the third gate signal to the third pixel circuit. The first pixel circuit is located between the third pixel circuit and the second pixel circuit.

6. The display device of claim 1, wherein the first transmission line crosses each of the first gate line and the second gate line, and the second transmission line further crosses the first gate line.

7. A method of operating the display device according to claim 1, comprising: At the first moment, the second gate signal (SG3) on the first transmission line (VG3) is adjusted from the first voltage level (VL) to the second voltage level (VH) to maintain the voltage level of the data line capacitively coupled to the first transmission line; At that first moment, the first gate signal (SG2) on the second transmission line (VG2) is adjusted from the second voltage level (VH) to the first voltage level (VL) to maintain the voltage level of the data line that is capacitively coupled to the second transmission line; Following the first moment, the second pixel circuit (B3) is charged according to the second gate signal (SG3) and the data signal on the data line; and Prior to the first moment, the first pixel circuit (B2) is charged according to the first gate signal (SG2) and the data signal.

8. The operating method as described in claim 7, further comprising: At that first moment, the voltage level of the first data line portion of the data line is pulled down via the first transmission line; and At that first moment, the voltage level of the second data line portion of the data line is pulled high via the second transmission line. The first data line portion, the second transmission line, the first transmission line, and the second data line portion are arranged in sequence.

9. The operating method as described in claim 7, further comprising: At that first moment, the voltage level of the data line portion of the data line is pulled low via the first transmission line; and At that first moment, the voltage level of the data line portion of the data line is pulled high via the second transmission line. The data line portion is located between the first transmission line and the second transmission line.

10. The operating method as described in claim 7, further comprising: At a second time point prior to the first time point, the third gate signal on the third transmission line is adjusted from the first voltage level to the second voltage level; and Prior to the second moment, the third pixel circuit is charged according to the third gate signal and the data signal. The third transmission line is located between the first transmission line and the second transmission line, and The first pixel circuit is located between the second pixel circuit and the third pixel circuit.

Images