Display panel and display device

Abstract

The application discloses a display panel and a display device. The working process of a pixel circuit in the display panel comprises a first mode and a second mode. The data refresh frequency of the pixel circuit in the first mode is a first data refresh frequency F1, the data refresh frequency of the pixel circuit in the second mode is a second data refresh frequency F2, one frame refresh time of the pixel circuit comprises a pre-stage and a light-emitting stage, the time length of the light-emitting stage in the first mode is L1, the time length of the light-emitting stage in the second mode is L2, and (F1-F2) x (L1-L2) < 0. The display panel and the display device provided in the application prolong the time length of the light-emitting stage when the data refresh frequency is low, shorten the time length of the light-emitting stage when the data refresh frequency is high, and reduce the display brightness difference of the display panel under different data refresh frequencies, thereby solving the problem of uneven display brightness of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Display panels typically contain pixel circuits and light-emitting elements. The driving transistors in the pixel circuits can generate driving currents based on the data signals they receive, thereby driving the light-emitting elements to emit light, so that the display panel can display a picture with the corresponding brightness.

[0003] Because display panels operate in different modes under different application scenarios, the brightness of the display panel varies under different operating modes, resulting in poor uniformity of the display panel's brightness. Summary of the Invention

[0004] The present invention provides a display panel and a display device to solve the problem of poor uniformity of screen brightness in display panels.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] Pixel circuits and light-emitting elements;

[0007] The operation of the pixel circuit includes a first mode and a second mode.

[0008] In the first mode, the data refresh frequency of the pixel circuit is a first data refresh frequency F1, and in the second mode, the data refresh frequency of the pixel circuit is a second data refresh frequency F2.

[0009] The refresh time of the pixel circuit per frame includes a pre-processing stage and a light-emitting stage. In the first mode, the duration of the light-emitting stage is L1, and in the second mode, the duration of the light-emitting stage is L2.

[0010] (F1-F2)×(L1-L2)<0.

[0011] According to another aspect of the present invention, a display device is provided, comprising the display panel described in the first aspect.

[0012] The display panel and display device provided in this embodiment of the invention include a first mode and a second mode in the operation of the pixel circuit. In the first mode, the data refresh frequency of the pixel circuit is a first data refresh frequency F1, and in the second mode, the data refresh frequency of the pixel circuit is a second data refresh frequency F2. In the first mode, the duration of the light-emitting phase in one frame refresh time is L1, and in the second mode, the duration of the light-emitting phase in one frame refresh time is L2. Specifically, by setting (F1-F2)×(L1-L2)<0, when the data refresh rate is low, the duration of the light-emitting phase in one frame refresh time is longer, resulting in a longer light-emitting time for the light-emitting element in one frame refresh time, improving the light-emitting efficiency of the light-emitting element, compensating for the brightness of the screen display, and improving the screen display brightness. When the data refresh rate is high, the duration of the light-emitting phase in one frame refresh time is shorter, resulting in a shorter light-emitting time for the light-emitting element in one frame refresh time, reducing the light-emitting efficiency of the light-emitting element, and reducing the screen display brightness. In this way, the difference in screen display brightness caused by the difference in brightness attenuation of the frame under different data refresh rates can be reduced, making the screen display brightness of the display panel more uniform in the first and second modes, and solving the problem of uneven screen display brightness of the display panel.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0020] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0021] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0022] Figure 8 A driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0023] Figure 9 A driving timing diagram for another pixel circuit provided in an embodiment of the present invention;

[0024] Figure 10 A driving timing diagram for yet another pixel circuit provided in an embodiment of the present invention;

[0025] Figure 11 A driving timing diagram for another pixel circuit provided in an embodiment of the present invention;

[0026] Figure 12 A driving timing diagram for yet another pixel circuit provided in an embodiment of the present invention;

[0027] Figure 13 A driving timing diagram for another pixel circuit provided in an embodiment of the present invention;

[0028] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0029] Figure 15 A driving timing diagram for yet another pixel circuit provided in an embodiment of the present invention;

[0030] Figure 16 A driving timing diagram of a pixel circuit in a first mode and a second mode is provided for embodiments of the present invention;

[0031] Figure 17 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention;

[0032] Figure 18 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention;

[0033] Figure 19 A driving timing diagram of another pixel circuit provided in the embodiments of the present invention in the first mode and the second mode;

[0034] Figure 20 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention;

[0035] Figure 21 A driving timing diagram of another pixel circuit provided in the embodiments of the present invention in the first mode and the second mode;

[0036] Figure 22 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention;

[0037] Figure 23 A driving timing diagram of another pixel circuit provided in the embodiments of the present invention in the first mode and the second mode;

[0038] Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, such as... Figure 1As shown, the display panel provided in this embodiment of the invention includes a pixel circuit 10 and a light-emitting element 11. The operation of the pixel circuit 10 includes a first mode and a second mode. In the first mode, the data refresh frequency of the pixel circuit 10 is a first data refresh frequency F1, and in the second mode, the data refresh frequency of the pixel circuit 10 is a second data refresh frequency F2. The refresh time of one frame of the pixel circuit 10 includes a pre-processing stage and a light-emitting stage. In the first mode, the duration of the light-emitting stage is L1, and in the second mode, the duration of the light-emitting stage is L2; ​​wherein, (F1-F2)×(L1-L2)<0.

[0042] Specifically, such as Figure 1 As shown, the display panel may include multiple pixel circuits 10 arranged in an array and multiple light-emitting elements 11 arranged in an array. The arrangement of the multiple pixel circuits 10 and multiple light-emitting elements 11 can be set according to actual needs.

[0043] Continue to refer to Figure 1 Multiple pixel circuits 10 and multiple light-emitting elements 11 are electrically connected to each other. The pixel circuit 10 is used to provide driving current to the light-emitting elements 11 that are electrically connected to it, so as to drive the light-emitting elements 11 to emit light.

[0044] The light-emitting element 11 can be an organic light-emitting diode (OLED), but is not limited to it. In other embodiments, the light-emitting element 11 may also include a micro light-emitting diode (such as a Micro-LED, Mini-LED) or other types of light-emitting devices.

[0045] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, as shown below. Figures 2-7As shown, optionally, the pixel circuit 10 includes a data writing module 11, a driving module 12, and a compensation module 13. The driving module 12 includes a driving transistor T2, which provides driving current to the light-emitting element 11. The data writing module 11 is connected to the first terminal (N2 node) of the driving transistor T2 and provides data signals to the driving transistor T2. The compensation module 13 is connected between the gate (N1 node) and the second terminal (N3 node) of the driving transistor T2 and compensates for the threshold voltage of the driving transistor T2.

[0046] In addition, the pixel circuit 10 may also include a reset module 15 for providing a reset signal Vref to the gate of the driving transistor T2; an initialization module 16 for providing an initialization signal Vini to the light-emitting element 11; and a light-emitting control module 17 for selectively allowing the light-emitting element 11 to enter the light-emitting stage. Optionally, the light-emitting control module 17 includes a first light-emitting control module 171 and a second light-emitting control module 172. The first light-emitting control module 171 is connected between the first power supply signal terminal and one pole of the driving transistor T2, and the second light-emitting control module 172 is connected between the other pole of the driving transistor T2 and the light-emitting element 11.

[0047] Optionally, in this embodiment, the control terminal of the data writing module 11 receives a first scan signal S1, which controls the opening and closing of the data writing module 11; the control terminal of the compensation module 13 receives a second scan signal S2, which controls the opening and closing of the compensation module 13; the control terminal of the reset module 15 receives a third scan signal S3, which controls the opening and closing of the reset module 15; the control terminal of the initialization module 16 receives a fourth scan signal S4, which controls the opening and closing of the initialization module 16; and the control terminal of the light emission control module 17 receives a light emission control signal EM, which controls the opening and closing of the light emission control module 17.

[0048] Alternatively, in this embodiment, the data writing module 11 includes a data writing transistor T1, and a first scan signal S1 controls the turning on and off of the data writing transistor T1; the compensation module 13 includes a compensation transistor T3, and a second scan signal S2 controls the turning on and off of the compensation transistor T3; the reset module 15 includes a reset transistor T5, and a third scan signal S3 controls the turning on and off of the reset transistor T5; the initialization module 16 includes an initialization transistor T6, and a fourth scan signal S4 controls the turning on and off of the initialization transistor T6; the first light-emitting control module 171 includes a first light-emitting control transistor T7, and the second light-emitting control module 172 includes a second light-emitting control transistor T8, and a light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T7 and the second light-emitting control transistor T8.

[0049] It should be noted that, as Figures 4-7 As shown, the pixel circuit may further include a bias adjustment module 14 for providing a bias adjustment signal to the driving transistor T2. Optionally, as... Figure 4 and Figure 6 As shown, the bias adjustment module 14 is connected to the first terminal (i.e., node N2) of the driving transistor T2; as Figure 5 and Figure 7 As shown, the bias adjustment module 14 is connected to the second terminal (i.e., node N3) of the driving transistor T2. Optionally, the control terminal of the bias adjustment module 14 receives a bias adjustment control signal SV, which controls the switching on and off of the bias adjustment module 14. The bias adjustment module 14 includes a bias adjustment transistor T4, which is switched on and off by the bias adjustment control signal SV.

[0050] Additionally, it should be noted that, as Figure 2 , Figure 4 , Figure 5 The pixel circuit 10 shown has a PMOS transistor driving transistor T2. The pixel circuit 10 also includes a storage capacitor C1. The first terminal of the storage capacitor C1 is connected to the first power supply signal terminal, and the second terminal is connected to the gate of the driving transistor T2, for storing the signal transmitted to the gate of the driving transistor T2. Figure 3 , Figure 6 , Figure 7 The pixel circuit 10 shown has an NMOS transistor driving transistor T2. The pixel circuit 10 also includes a storage capacitor C1. The first terminal of the storage capacitor C1 is connected to the light-emitting element 11, and the second terminal is connected to the gate of the driving transistor T2. The storage capacitor C1 is used to store the signal transmitted to the gate of the driving transistor T2.

[0051] In this embodiment, the light-emitting control module 17, the driving transistor T2, and the light-emitting element 11 are connected in series between the first power signal terminal and the second power signal terminal. A driving current is generated through the potential difference between the first power signal PVDD and the second power signal PVEE, thereby driving the light-emitting element 11 to emit light. The first power signal terminal provides the first power signal PVDD, and the second power signal terminal provides the second power signal PVEE, with the voltage of the first power signal PVDD being greater than that of the second power signal PVEE.

[0052] also, Figures 2-7 This embodiment only provides examples of several pixel circuit structures, and does not include all of them. It will not be described in detail here.

[0053] Figure 8 A driving timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 8As shown, within one frame refresh time F of the display panel, the operation of the pixel circuit 10 includes a pre-processing stage t10 and a light-emitting stage t20. In some cases, the pre-processing stage t10 and the light-emitting stage t20 can be performed sequentially.

[0054] Within one frame refresh time F, the pre-stage t10 is the stage where the light-emitting element 11 does not emit light, and the light-emitting stage t20 is the stage where the light-emitting element 11 emits light.

[0055] Specifically, such as Figures 2-8 As shown, in the pre-stage t10, the light-emitting control signal EM is an invalid pulse, and the control terminal of the light-emitting control module 17 is turned off under the action of the light-emitting control signal EM. At this time, the light-emitting element 11 does not emit light. In the light-emitting stage t20, the light-emitting control signal EM is an effective pulse, and the control terminal of the light-emitting control module 17 is turned on under the action of the light-emitting control signal EM. At this time, the driving current generated by the driving transistor T2 can be transmitted to the light-emitting element 11, thereby controlling the light-emitting element 11 to enter the light-emitting stage and emit light.

[0056] It should be noted that the effective pulse of the light emission control signal EM can be set according to the channel type of the transistor in the light emission control module 17.

[0057] For example, such as Figures 2-8 As shown, the first light-emitting control module 171 includes a first light-emitting control transistor T7, and the second light-emitting control module 172 includes a second light-emitting control transistor T8. Taking PMOS transistors as an example, both first and second light-emitting control transistors T7 and T8 receive a light-emitting control signal EM at their gates. In the pre-amplification stage t10, the invalid pulse of the light-emitting control signal EM is high, and the first and second light-emitting control transistors T7 and T8 are turned off under the control of the light-emitting control signal EM. In the light-emitting stage t20, the valid pulse of the light-emitting control signal EM is low, and the first and second light-emitting control transistors T7 and T8 are turned on under the control of the light-emitting control signal EM, so that when the driving transistor T2 is turned on, the driving current generated by the driving transistor T2 is transmitted to the light-emitting element 11, and the light-emitting element 11 emits light.

[0058] It is understandable that when the transistor in the light-emitting control module 17 is an NMOS type transistor, the invalid pulse of the light-emitting control signal EM is low level, and the valid pulse of the light-emitting control signal EM is high level, which will not be elaborated here.

[0059] It should be noted that the refresh time of one frame is calculated based on the minimum cycle of the drive current written to the light-emitting element 11. In one refresh cycle of the light-emitting control signal EM, the light-emitting control module 17 can be turned on once, and the drive current can be transmitted to the light-emitting element 11, thereby the light-emitting element 11 enters the light-emitting stage.

[0060] Figure 9 This is a driving timing diagram for another pixel circuit provided in an embodiment of the present invention, wherein, Figure 9 The timing shown can correspond to Figure 2 The pixel circuit structure shown is as follows: Figure 2 and Figure 9 As shown, during at least one frame refresh time, the pre-processing phase t10 of the pixel circuit 10 may include a reset phase t11.

[0061] During the reset phase t11, the third scan signal S3 is a high-level valid signal, which turns on the reset transistor T5. The reset signal Vref is transmitted to the gate of the driving transistor T2 (i.e., node N1) through the turned-on reset transistor T5, thereby resetting the gate of the driving transistor T2. At this time, the potential of the gate of the driving transistor T2 (i.e., node N1) is consistent with the reset signal Vref to avoid the data signal of the previous frame carried on the gate of the driving transistor T2 from affecting the writing of the data signal of the next frame.

[0062] Continue to refer to Figure 2 and Figure 9 During at least one frame refresh time, the pre-processing stage t10 of the pixel circuit 10 may also include a data writing stage t12.

[0063] During the data writing phase t12, the first scan signal S1 is a low-level active pulse, and the second scan signal S2 is a high-level active pulse, causing the data writing transistor T1 and the compensation transistor T3 to conduct. Simultaneously, the gate potential of the driving transistor T2 is aligned with the reset signal Vref, and driving transistor T2 also conducts. The data signal Vdata passes through the data writing transistor T1, driving transistor T2, and compensation transistor T3, and is applied to the gate of driving transistor T2 (i.e., node N1). The potential of node N1 gradually increases until driving transistor T2 is turned off. When driving transistor T2 is turned off, its gate potential is V0. data -|V th |, where V data Let |V_data be the voltage value of the data signal V_data. th | represents the threshold voltage for driving transistor T2.

[0064] Continue to refer to Figure 2 and Figure 9During at least one frame refresh time, after the data writing phase t12 ends, the display panel can enter the illumination phase t20.

[0065] During the light-emitting stage t20, the light-emitting control signal EM is a low-level active pulse, and the first light-emitting control transistor T7 and the second light-emitting control transistor T8 are turned on. Because the first light-emitting control transistor T7 is turned on, the first power supply signal PVDD is transmitted to the first terminal of the driving transistor T2. Therefore, the voltage difference between the first terminal and the gate of the driving transistor T2 is V. PVDD -(V data -|V th |), so that the driving current generated by the driving transistor T2 is K*(V data -V PVDD ) 2 K is a coefficient related to the size and material of the driving transistor T2. Thus, the driving current generated by the driving transistor T2 is related to its own threshold voltage |V th |Irrelevant, the driving current is transmitted to the anode of the light-emitting element 11 through the conducting second light-emitting control transistor T8, causing the light-emitting element 11 to emit light.

[0066] Continue to refer to Figure 2 and Figure 9 During at least one frame refresh time, the pre-processing phase t10 of the pixel circuit 10 may also include an initialization phase t13.

[0067] During the initialization phase t13, the fourth scan signal S4 is a low-level effective pulse, which turns on the initialization transistor T6. The initialization signal Vini is transmitted to the anode of the light-emitting element 11 through the initialization transistor T6 to initialize the anode of the light-emitting element 11 and prevent the driving current provided to the anode of the light-emitting element 11 in the previous frame from affecting the display brightness of the light-emitting element 11 in the next frame.

[0068] Figure 10 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, wherein, Figure 10 The timing sequence shown can correspond to Figure 4 The pixel circuit structure shown is as follows: Figure 4 and Figure 10 As shown, during at least one frame refresh time, the pre-processing stage t10 of the pixel circuit 10 may also include a bias adjustment stage t14.

[0069] During the bias adjustment stage t14, the bias adjustment control signal SV is a low-level effective pulse, which turns on the bias adjustment transistor T4. The bias adjustment signal V0 is input to the first terminal (i.e., node N2) of the driving transistor T2 to adjust the voltage difference between the gate of the driving transistor T2 and the first terminal (i.e., node N2), thereby eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, and preventing the threshold voltage of the driving transistor T2 from shifting, which helps to reduce the flickering phenomenon.

[0070] For example, when the driving transistor T2 is a PMOS transistor, during the bias adjustment stage t14, the potential of the first or second terminal of the driving transistor T2 can be raised by the bias adjustment signal V0 to increase the voltage difference between the first or second terminal of the driving transistor T2 and the gate, thereby counteracting the reverse electric field generated inside the driving transistor T2 and solving the bias problem, but it is not limited to this.

[0071] Continue to refer to Figure 4 and Figure 10 During the bias adjustment phase t14, the second scan signal S2 can be a high-level effective pulse, which turns on the compensation transistor T3. At this time, the bias adjustment signal V0 can be transmitted to the gate of the driving transistor T2 through the compensation transistor T3, so that the gate of the driving transistor T2 is consistent with the potential of the first pole (i.e., the N2 node), which can further improve the threshold voltage offset phenomenon of the driving transistor T2, thereby reducing the flickering phenomenon.

[0072] In an optional embodiment, the channel type of the initialization transistor T6 can be the same as that of the bias adjustment transistor T4. In this way, the bias adjustment control signal SV and the fourth scan signal S4 can be set to the same signal, so that the initialization transistor T6 and the bias adjustment transistor T4 can be turned on or off simultaneously.

[0073] It is understood that the above description only illustrates the type of each transistor in the pixel circuit 10 and the corresponding driving process. In the embodiments of the present invention, when the type of each transistor in the pixel circuit 10 changes, the driving process can be similar to that described above by changing the signal received by the gate of each transistor, which will not be repeated here.

[0074] Furthermore, in order to reduce power consumption and meet users' needs for different display modes, the pixel circuits in the display panel need to have refresh modes that correspond to different data refresh frequencies.

[0075] In this embodiment of the application, the operation of the pixel circuit 10 includes a first mode and a second mode. The data refresh frequency of the pixel circuit 10 in the first mode is a first data refresh frequency F1, and the data refresh frequency of the pixel circuit 10 in the second mode is a second data refresh frequency F2. The first data refresh frequency F1 and the second data refresh frequency F2 are different.

[0076] In a display panel, the frame refresh rate is the frequency at which the smallest unit of image refresh changes (the frame). The frame refresh rate can be equal to the number of times a frame is refreshed per second. The data refresh rate, on the other hand, refers to the frequency at which the data signal Vdata is written to the gate of the driving transistor in the pixel circuit. The data refresh rate can also be equal to the number of times the data signal Vdata is written to the gate of the driving transistor in the pixel circuit per second.

[0077] Furthermore, the operation of the pixel circuit includes a data write frame and a hold frame. The data write frame includes a data write stage, in which the data write module writes a data signal to the gate of the driving transistor. The hold frame does not include a data write stage.

[0078] When the display panel displays data at a data refresh rate lower than the frame refresh rate, a frame skipping method is generally used to reduce the frequency. That is, a hold frame is inserted after the data write frame in each data refresh cycle. The duration of the data write frame can be the same under different refresh rates. By adjusting the duration of the hold frame, the actual display effect can meet the corresponding data refresh rate.

[0079] For example, taking a display panel with a frame refresh rate of 120Hz as an example, when the data refresh rate is 60Hz, it means that one data refresh cycle includes one data write frame and one hold frame; when the data refresh rate is 30Hz, it means that one data refresh cycle includes one data write frame and three hold frames, and so on.

[0080] It is understandable that the data refresh frequency is the frequency at which data is written and frames appear. When the first data refresh frequency F1 is greater than the second data refresh frequency F2, the number of hold frames included in one data refresh cycle of the pixel circuit 10 in the first mode is less than the number of hold frames included in one data refresh cycle of the pixel circuit 10 in the second mode. Similarly, when the first data refresh frequency F1 is less than the second data refresh frequency F2, the number of hold frames included in one data refresh cycle of the pixel circuit 10 in the first mode is greater than the number of hold frames included in one data refresh cycle of the pixel circuit 10 in the second mode.

[0081] The inventors discovered that when the pixel circuit has different operating modes corresponding to different data refresh frequencies (such as the first mode and the second mode), the display panel has a problem of uneven screen brightness.

[0082] Further research by the inventors revealed that the reason for the above-mentioned problem is that, in the low data refresh frequency operating mode, the pixel circuit inserts a large number of hold frames after the data is written within a data refresh cycle. For example, taking a frame refresh frequency of 120Hz and a data refresh frequency of 1Hz as an example, the data refresh cycle is 1 second, and one data refresh cycle includes one data write frame and 119 hold frames after the data write frame.

[0083] It is understandable that within the 119 hold frames in one data refresh cycle, the gate of the driving transistor in the pixel circuit needs to always hold the data signal written in the data write frame of that data refresh cycle. However, since the duration of 119 hold frames is relatively long, the gate voltage of the driving transistor will change due to factors such as leakage current over time, causing the light emission brightness of the light-emitting element driven by the pixel circuit to decrease.

[0084] The lower the data refresh rate, the more frames are held in one data refresh cycle, and the longer the overall duration of all held frames in one data refresh cycle. Consequently, the brightness of the corresponding light-emitting element will decrease more significantly, and the screen display brightness will be reduced more noticeably.

[0085] Therefore, when the pixel circuit operates at a lower data refresh rate, the brightness of the light-emitting element decreases significantly, resulting in lower screen brightness. Conversely, when the pixel circuit operates at a higher data refresh rate, the brightness of the light-emitting element decreases, resulting in higher screen brightness. Consequently, when the pixel circuit operates in different data refresh rate modes (e.g., the first mode and the second mode), the display panel exhibits uneven screen brightness.

[0086] Based on the above technical issues Figure 11 This is a driving timing diagram for another pixel circuit provided in an embodiment of the present invention. Figure 12 A driving timing diagram for another pixel circuit provided in an embodiment of the present invention, such as... Figure 11 and Figure 12 As shown, in this embodiment of the invention, the duration of the light-emitting phase of the pixel circuit in the first mode is L1, and the duration of the light-emitting phase of the pixel circuit in the second mode is L2, and (F1-F2)×(L1-L2)<0 is set.

[0087] Specifically, such as Figure 11 and Figure 12As shown, in the first mode, the data refresh frequency of the pixel circuit 10 is the first data refresh frequency F1, and the frame refresh time corresponding to the first data refresh frequency F1 is f1; in the second mode, the data refresh frequency of the pixel circuit is the second data refresh frequency F2, and the frame refresh time corresponding to the second data refresh frequency F2 is f2.

[0088] Among them, such as Figure 11 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, F1-F2>0. The number of frames held by the pixel circuit in one data refresh cycle in the second mode is greater than the number of frames held by the pixel circuit in one data refresh cycle in the first mode. As a result, the overall duration of all held frames in one data refresh cycle in the second mode is longer than the overall duration of all held frames in one data refresh cycle in the first mode. Therefore, the degree of attenuation of the light emission brightness of the light-emitting element driven by the pixel circuit in the second mode is greater than the degree of attenuation of the light emission brightness of the light-emitting element driven by the pixel circuit in the first mode, resulting in the screen display brightness in the second mode being lower than the screen display brightness in the first mode. In this embodiment, L1-L2<0 is set, meaning that the duration L2 of the light-emitting phase t20 in one frame refresh time f2 of the second mode is greater than the duration L1 of the light-emitting phase t20 in one frame refresh time f1 of the first mode. This makes the duration L2 of the light-emitting phase t20 longer in the second mode, thereby making the light-emitting element emit light for a longer time in one frame refresh time f2 in the second mode. This improves the light-emitting efficiency of the light-emitting element in the second mode, compensates for the brightness of the screen display in the second mode, and ultimately makes the screen display brightness in the second mode approach the screen display brightness in the first mode, thus improving the problem of uneven screen display brightness in the display panel.

[0089] Similarly, in another embodiment, such as Figure 12 As shown, when the first data refresh frequency F1 is less than the second data refresh frequency F2, F1-F2<0, then the screen display brightness in the second mode will be higher than that in the first mode. In this embodiment, L1-L2>0 is set, that is, the duration L2 of the light-emitting phase t20 in one frame refresh time f2 in the second mode is less than the duration L1 of the light-emitting phase t20 in one frame refresh time f1 in the first mode. This makes the duration L1 of the light-emitting phase t20 in the first mode longer, thereby making the light-emitting element in the first mode emit light for a longer time in one frame refresh time f1, thus improving the light-emitting efficiency of the light-emitting element in the first mode, compensating for the screen display brightness in the first mode, and ultimately making the screen display brightness in the first mode approach the screen display brightness in the second mode, thus improving the problem of uneven screen display brightness in the display panel.

[0090] Understandably, a lower data refresh rate results in more held frames per refresh cycle, a longer overall duration for all held frames, and a greater attenuation of the light-emitting element's brightness. This leads to a more noticeable decrease in screen brightness. Therefore, extending the duration of the light-emitting phase within a single refresh frame (i.e., setting a longer light-emitting phase) increases the duration of light emission within that frame, thereby improving the light-emitting element's efficiency and compensating for the reduced screen brightness. Conversely, a higher data refresh rate results in fewer held frames per refresh cycle, a shorter overall duration for all held frames, and a smaller attenuation of the light-emitting element's brightness. This leads to a less noticeable decrease in screen brightness. Therefore, shortening the duration of the light-emitting phase within a single refresh frame further reduces the light-emitting element's efficiency and decreases screen brightness. Ultimately, by reducing the difference in screen brightness between high and low refresh rates, the screen brightness of the display panel becomes more uniform across both high and low refresh rates.

[0091] In summary, the display panel provided in this embodiment of the invention includes a first mode and a second mode in the operation of the pixel circuit. In the first mode, the data refresh frequency of the pixel circuit is a first data refresh frequency F1, and in the second mode, the data refresh frequency of the pixel circuit is a second data refresh frequency F2. In the first mode, the duration of the light-emitting phase in one frame refresh time is L1, and in the second mode, the duration of the light-emitting phase in one frame refresh time is L2. Specifically, by setting (F1-F2)×(L1-L2)<0, when the data refresh rate is low, the duration of the light-emitting phase in one frame refresh time is longer, resulting in a longer light-emitting time for the light-emitting element in one frame refresh time, improving the light-emitting efficiency of the light-emitting element, compensating for the brightness of the screen display, and improving the screen display brightness. When the data refresh rate is high, the duration of the light-emitting phase in one frame refresh time is shorter, resulting in a shorter light-emitting time for the light-emitting element in one frame refresh time, reducing the light-emitting efficiency of the light-emitting element, and reducing the screen display brightness. In this way, the difference in screen display brightness caused by the difference in brightness attenuation of the frame under different data refresh rates can be reduced, making the screen display brightness of the display panel more uniform in the first and second modes, and solving the problem of uneven screen display brightness of the display panel.

[0092] Figure 13 Another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 13As shown, optionally, the operation of the pixel circuit includes a first time period D1 and a second time period D2. During the first time period D1, the pixel circuit operates in a first mode, and during the second time period D2, the pixel circuit operates in a second mode.

[0093] Users have different requirements for the data refresh rate of the display panel in different usage scenarios. For example, in application scenarios such as competitive gaming and high-definition dynamic video viewing, a higher data refresh rate is needed to ensure fast screen refresh and improve the user experience. In application scenarios such as reading e-books, a lower data refresh rate can be set to meet the needs of static display screens or other application scenarios that do not require a high data refresh rate, while also helping to reduce the power consumption of the display panel.

[0094] In this embodiment, as Figure 13 As shown, the settings can be configured according to different application scenarios. The pixel circuit can be set to work in different modes at different times to achieve different data refresh frequencies at different times, thereby meeting the usage requirements of different application scenarios.

[0095] For example, such as Figure 13 As shown, taking an example where the first data refresh rate F1 is greater than the second data refresh rate F2, during the first time period D1, the pixel circuit operates in the first mode. At this time, the data refresh rate of the pixel circuit is the first data refresh rate F1 to ensure fast screen refresh and meet the user's needs in application scenarios such as competitive games and high-definition dynamic video viewing. During the second time period D2, the pixel circuit operates in the second mode. At this time, the data refresh rate of the pixel circuit is the second data refresh rate F2 to meet the needs of static displays or other application scenarios that do not require a high data refresh rate, and also helps reduce the power consumption of the display panel.

[0096] Among them, such as Figure 13 As shown, the duration L2 of the light-emitting phase t20 in the one-frame refresh time f2 of the second mode is greater than the duration L1 of the light-emitting phase t20 in the one-frame refresh time f1 of the first mode. That is, the duration L2 of the light-emitting phase t20 in the second mode is longer, which makes the light-emitting element in the one-frame refresh time f2 of the second mode emit light for a longer time. This can improve the light-emitting efficiency of the light-emitting element in the second mode, compensate for the brightness of the screen display in the second mode, and ultimately make the brightness of the screen display in the second mode approach that of the screen display in the first mode. This allows the brightness of the screen display panel to be comparable in the first time period D1 and the second time period D2, avoiding screen flickering when the display panel switches between the first mode and the second mode in the first time period D1 and the second time period D2.

[0097] Similarly, when the first data refresh frequency F1 is less than the second data refresh frequency F2, the pixel circuit can be selected to work in the first mode or the second mode at different time periods according to different application scenarios, so as to meet the user's usage needs at different time periods. This will not be elaborated here.

[0098] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 14 As shown, optionally, the display panel provided in the embodiment of the present invention includes a first display area 21 and a second display area 22. The pixel circuit of the first display area 21 operates in a first mode, and the pixel circuit of the second display area 22 operates in a second mode.

[0099] Specifically, such as Figure 14 As shown, the display panel includes different display areas (e.g., the first display area 21 and the second display area 22). In some usage scenarios, the functional requirements for different display areas are reflected in the difference in data refresh rate. For example, as... Figure 14 As shown, the first display area 21 is used for playing movies, games, and other content, requiring a higher data refresh rate to ensure fast screen refresh and improve user experience. The second display area 22, on the other hand, displays text, time information, and other content, and therefore does not require a high data refresh rate; a lower refresh rate is sufficient.

[0100] Therefore, in this embodiment, the pixel circuit can operate in different modes in different display areas to meet the display requirements of different display areas.

[0101] For example, such as Figure 14 As shown, taking the example of a first data refresh rate F1 being greater than a second data refresh rate F2, since the human eye is more sensitive to the image display in the middle area of ​​the display panel and less sensitive to the image display in the peripheral area of ​​the display panel, the middle area of ​​the display panel can be set as the first display area 21 and the peripheral area as the second display area 22. In the first display area 21, the pixel circuit operates in the first mode. At this time, the data refresh rate of the pixel circuit in the first display area 21 is the first data refresh rate F1, so that the image refresh rate in the middle area of ​​the display panel is higher to meet user needs, while the image refresh rate in the peripheral area is lower, thereby reducing the power consumption of the display panel without affecting the user experience.

[0102] Of course, the present invention is not limited to this. In other embodiments, for example, for instrument-type display products, only the area displaying the numbers needs to be updated. In this case, the area displaying the numbers can be set as the first display area 21, and the other display areas can be set as the second display area 22. For e-book display products, it may only be necessary to update the area displaying the specific text content of each chapter, while the illustrations or titles do not need to be updated. In this case, the area displaying the specific text content of each chapter can be set as the first display area 21, and the area displaying the illustrations or titles can be set as the second display area 22, so as to reduce the power consumption of the display panel while meeting user needs. The embodiments of the present invention do not limit this.

[0103] It is understood that those skilled in the art can arbitrarily set the positions of the first display area 21 and the second display area 22 according to actual needs, and select whether the pixel circuit in the first display area 21 and the second display area 22 works in a first mode or a second mode to meet the user's usage needs in different display areas.

[0104] Referring to the principle description in the above embodiments, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration of the light-emitting phase in one frame refresh time is shorter in the first display area 21 operating in the first mode; and the duration of the light-emitting phase in one frame refresh time is longer in the second display area 22 operating in the second mode. This allows the display brightness of the screen in the first display area 21 operating in the first mode to be comparable to that of the screen in the second display area 22 operating in the second mode, thereby avoiding the problem of uneven display brightness in the first display area 21 and the second display area 22.

[0105] Similarly, when the first data refresh frequency F1 is less than the second data refresh frequency F2, the duration of the light-emitting phase in one frame refresh time of the first display area 21 is greater than the duration of the light-emitting phase in one frame refresh time of the second display area 22. This makes the display brightness of the first display area 21 operating in the first mode comparable to that of the second display area 22 operating in the second mode, thereby avoiding the problem of uneven display brightness in the first display area 21 and the second display area 22. This will not be elaborated further here.

[0106] Continue to refer to Figure 11 Optional, F1 > F2, F1 / F2 > L2 / L1.

[0107] Specifically, such as Figure 11 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration L2 of the light emission phase t20 in the frame refresh time f2 of the second mode is greater than the duration L1 of the light emission phase t20 in the frame refresh time f1 of the first mode.

[0108] The inventors discovered that if the ratio between the duration L2 of the light-emitting phase t20 in the frame refresh time f2 of the second mode and the duration L1 of the light-emitting phase t20 in the frame refresh time f1 of the first mode is too large, it may cause the display panel to fail to emit light normally in the first mode due to the short duration of the light-emitting phase t20. Alternatively, in the second mode, the display panel may severely compress the duration of the pre-amplifier phase t10 due to the excessive duration of the light-emitting phase t20, resulting in the data signal being unable to be properly written into the gate of the driving transistor in the pixel circuit, thus affecting the display effect.

[0109] Based on the aforementioned technical issues, in this embodiment, by setting F1 / F2 > L2 / L1, that is, by setting the ratio between the duration L2 of the light-emitting phase t20 in one frame refresh time f2 in the second mode and the duration L1 of the light-emitting phase t20 in one frame refresh time f1 in the first mode, which is less than the ratio between the first data refresh frequency F1 and the second data refresh frequency F2, the ratio relationship between L2 and L1 is reasonably set so that the duration L2 of the light-emitting phase t20 in one frame refresh time f2 in the second mode and the duration L1 of the light-emitting phase t20 in one frame refresh time f1 in the first mode will not cause the display panel to fail to display normally due to excessive difference.

[0110] Continue to refer to Figure 11 Optional, F1 > F2, L1 / L2 > 1 / 2.

[0111] Specifically, such as Figure 11 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration L2 of the light emission phase t20 in the frame refresh time f2 of the second mode is greater than the duration L1 of the light emission phase t20 in the frame refresh time f1 of the first mode.

[0112] Referring to the above embodiments, if the ratio between the duration L1 of the light-emitting phase t20 in the first mode and the duration L2 of the light-emitting phase t20 in the second mode is too small, the display panel may be unable to emit light normally in the first mode due to the short duration of the light-emitting phase t20. Alternatively, in the second mode, the display panel may severely compress the duration of the pre-amplifier phase t10 due to the excessive duration of the light-emitting phase t20, resulting in the data signal not being accurately written into the gate of the driving transistor in the pixel circuit, thus affecting the display effect.

[0113] Based on the above technical problems, in this embodiment, by setting L1 / L2 > 1 / 2, that is, the duration L1 of the light-emitting phase t20 in one frame refresh time f1 in the first mode is more than half of the duration L2 of the light-emitting phase t20 in one frame refresh time f2 in the second mode, the ratio between L1 and L2 is reasonably set so that the duration L1 of the light-emitting phase t20 in one frame refresh time f1 in the first mode and the duration L2 of the light-emitting phase t20 in one frame refresh time f2 in the second mode will not cause the display panel to fail to display normally due to excessive difference.

[0114] Continue to refer to Figure 11 and Figure 12 Optionally, in the first mode, the time length of the pre-stage t10 is W1, and in the second mode, the time length of the pre-stage t10 is W2; where (F1-F2)×(W1-W2)≥0.

[0115] Specifically, such as Figure 11 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, F1-F2>0. In the second mode, the duration L2 of the light emission stage t20 in one frame refresh time f2 is greater than the duration L1 of the light emission stage t20 in one frame refresh time f1 in the first mode. This is to compensate for the screen display brightness in the second mode, so that the screen display brightness in the second mode is close to that in the first mode, thus improving the problem of uneven screen display brightness in the display panel.

[0116] At this point, setting W1-W2>0, i.e. (F1-F2)×(W1-W2)>0, makes the time length W2 of the pre-stage t10 in the frame refresh time f2 of the second mode less than the time length W1 of the pre-stage t10 in the frame refresh time f1 of the first mode. Under the condition that the frame refresh frequency remains unchanged, it can provide sufficient extension space for the time length L2 of the light emission stage t20 in the frame refresh time f2 of the second mode. Thus, while compensating for the brightness of the screen display in the second mode, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals according to a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0117] Similarly, in another embodiment, such as Figure 12As shown, when the first data refresh frequency F1 is less than the second data refresh frequency F2, F1-F2<0. In the second mode, the duration L2 of the light emission phase t20 in the frame refresh time f2 is less than the duration L1 of the light emission phase t20 in the frame refresh time f1 in the first mode. This is to compensate for the screen display brightness in the first mode, so that the screen display brightness in the first mode is close to that in the second mode, thereby improving the problem of uneven screen display brightness in the display panel.

[0118] At this point, setting W1-W2<0, i.e. (F1-F2)×(W1-W2)>0, makes the time length W2 of the pre-stage t10 in the frame refresh time f2 of the second mode greater than the time length W1 of the pre-stage t10 in the frame refresh time f1 of the first mode. Under the condition that the frame refresh frequency remains unchanged, it can provide sufficient extension space for the time length L1 of the light emission stage t20 in the frame refresh time f1 of the first mode. Thus, while compensating for the brightness of the screen display in the first mode, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals according to a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0119] Understandably, to minimize the difference in screen brightness between high and low refresh rates, and to achieve more uniform brightness across the display, a lower refresh rate results in a longer light-emitting phase within a single frame, thus increasing brightness. In this case, the pre-refresh phase can be shortened to maintain a consistent refresh time, reducing the complexity of the driver chip's output signal and improving driving stability. Conversely, a higher refresh rate results in a shorter light-emitting phase within a single frame, reducing brightness. In this case, the pre-refresh phase can be lengthened to maintain a consistent refresh time, reducing the complexity of the driver chip's output signal and improving driving stability.

[0120] Figure 15 A driving timing diagram for another pixel circuit provided in an embodiment of the present invention, such as... Figure 15As shown, optionally, W1 can be set to W2, meaning that the duration W2 of the pre-processing phase t10 in the frame refresh time f2 of the second mode is equal to the duration W1 of the pre-processing phase t10 in the frame refresh time f1 of the first mode. In this case, (F1-F2)×(W1-W2)=0. With this setting, the duration t10 of the pre-processing phase of the pixel circuit remains unchanged in both the first and second modes. This helps to ensure the accuracy and stability of the data signal writing to the gate of the driving transistor in the pre-processing phase t10 of the pixel circuit in both modes, reducing the impact on the display panel's image display effect.

[0121] Continue to refer to Figure 11 and Figure 12 Optional, W1+L1=W2+L2.

[0122] Specifically, such as Figure 11 and Figure 12 As shown, in the first mode, the sum of the time length W1 of the pre-stage t10 and the time length L1 of the luminous stage t20 is the frame refresh time f1 in the first mode. In the second mode, the sum of the time length W2 of the pre-stage t10 and the time length L2 of the luminous stage t20 is the frame refresh time f2 in the second mode.

[0123] In this embodiment, by setting W1+L1=W2+L2, the frame refresh time f1 in the first mode and the frame refresh time f2 in the second mode can be made equal. That is, the frame refresh time of the pixel circuit is the same when the pixel circuit is working in the first mode and the second mode. At this time, the frame refresh frequency of the pixel circuit is the same when the pixel circuit is working in the first mode and the second mode. The driver chip can provide display signals to the pixel circuit according to the fixed frame refresh frequency, which helps to reduce the complexity of the display signal output by the driver chip, and thus reduces the process complexity and manufacturing cost of the driver chip and the display panel.

[0124] Continue to refer to Figure 15 Optional, F1>F2, W1+L1<W2+L2.

[0125] Specifically, such as Figure 15 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration L2 of the light emission stage t20 in the frame refresh time f2 of the second mode is greater than the duration L1 of the light emission stage t20 in the frame refresh time f1 of the first mode. This is to compensate for the screen display brightness in the second mode, so that the screen display brightness in the second mode is close to that in the first mode, thereby improving the problem of uneven screen display brightness in the display panel.

[0126] In this embodiment, W1+L1 < W2+L2 is set, meaning that the frame refresh time f1 in the first mode is less than the frame refresh time f2 in the second mode. Under the condition that L2 > L1, that is, while compensating for the brightness of the screen display in the second mode, the time length W1 of the pre-stage t10 in the frame refresh time f1 in the first mode and the time length W2 of the pre-stage t10 in the frame refresh time f2 in the second mode do not need to be adjusted accordingly. This helps to ensure the accuracy and stability of the pixel circuit writing the data signal to the gate of the driving transistor in the pre-stage t10 in the first and second modes, and avoids affecting the screen display effect of the display panel.

[0127] Furthermore, when adjusting the duration L1 of the light-emitting stage t20 in the first mode and the duration L2 of the light-emitting stage t20 in the second mode according to the first data refresh frequency F1 and the second data refresh frequency F2, sufficient adjustment space can be provided for the duration L1 of the light-emitting stage t20 in the first mode and the duration L2 of the light-emitting stage t20 in the second mode by shortening the one-frame refresh time f1 in the first mode and / or extending the one-frame refresh time f2 in the second mode. This eliminates the limitation imposed by the duration of the preceding stage t10, thus increasing the design freedom of the duration L1 of the light-emitting stage t20 in the first mode and the duration L2 of the light-emitting stage t20 in the second mode. Simultaneously, the duration L1 of the light-emitting stage t20 in the first mode and the duration L2 of the light-emitting stage t20 in the second mode, as well as the duration W1 of the preceding stage t10 in the first mode and the duration W2 of the preceding stage t10 in the second mode, can all be adjusted independently, which helps the display panel meet the usage requirements of more application scenarios.

[0128] Optionally, the data refresh frequency of the pixel circuit includes a first frequency band and a second frequency band. The data refresh frequency span of the first frequency band is ΔF1, and the duration of the light emission phase within the first frequency band remains unchanged. The data refresh frequency span of the second frequency band is ΔF2, and the duration of the light emission phase within the second frequency band remains unchanged. The first data refresh frequency F1 is located in the first frequency band, and the second data refresh frequency F2 is located in the second frequency band.

[0129] The inventors discovered that when the data refresh frequency of the pixel circuit does not change much, for example, when the data refresh frequency of the pixel circuit is 110Hz and 120Hz respectively, the number of holding frames in one data refresh cycle will not change significantly. Therefore, the overall duration of all holding frames in one data refresh cycle will not have a significant difference, and the degree of attenuation of the light emission brightness of the corresponding light-emitting element will not have a significant difference. As a result, the change in the brightness of the screen display is not obvious.

[0130] Therefore, when the difference between the first data refresh rate F1 and the second data refresh rate F2 is very small, that is, when the difference between the screen display brightness in the first mode and the screen display brightness in the second mode is very small, setting the time length L1 of the light emission stage t20 in the first mode and the time length L2 of the light emission stage t20 in the second mode to be different may lead to overcorrection, causing uneven screen display brightness of the display panel in the first mode and the second mode.

[0131] Based on the above-mentioned technical problems, in this embodiment, a first frequency band and a second frequency band are set, and there is no data refresh frequency in the first frequency band and the second frequency band.

[0132] The data refresh frequency span of the first frequency band is △F1, and the data refresh frequency span of the second frequency band is △F2. The data refresh frequency span refers to the span between the highest and lowest data refresh frequencies in the frequency band, or the difference between the highest and lowest data refresh frequencies in the frequency band.

[0133] For example, taking a first frequency band including 60Hz to 90Hz and a second frequency band including 90Hz to 120Hz as an example, the data refresh frequency span ΔF1 of the first frequency band is equal to 30Hz, and the data refresh frequency span ΔF2 of the second frequency band is equal to 30Hz.

[0134] When the data refresh frequency of the pixel circuit changes within the first frequency band, the range of change of the data refresh frequency of the pixel circuit will be limited to within the data refresh frequency span △F1. At this time, the difference in screen display brightness of the pixel circuit under different data refresh frequencies is small. Thus, the duration of the light emission stage within the first frequency band can be kept constant to avoid the problem of overcorrection.

[0135] Similarly, when the data refresh frequency of the pixel circuit changes within the second frequency band, the range of change of the data refresh frequency of the pixel circuit will be limited to within the data refresh frequency span ΔF2. At this time, the difference in screen display brightness of the pixel circuit under different data refresh frequencies is small. Thus, the duration of the light emission stage within the first frequency band can be kept constant to avoid the problem of overcorrection.

[0136] Furthermore, the first data refresh frequency F1 is located in the first frequency band. Since the duration of the light-emitting phase remains constant within the first frequency band, the duration L1 of the light-emitting phase in one frame refresh time in the first mode will not change regardless of whether the first data refresh frequency F1 is any data refresh frequency within the first frequency band. The second data refresh frequency F2 is located in the second frequency band. Since the duration of the light-emitting phase remains constant within the second frequency band, the duration L2 of the light-emitting phase in one frame refresh time in the second mode will not change regardless of whether the second data refresh frequency F2 is any data refresh frequency within the second frequency band.

[0137] In this embodiment, by setting the first data refresh frequency F1 and the second data refresh frequency F2 in different frequency bands (e.g., in the first frequency band and the second frequency band), a large difference can be made between the first data refresh frequency F1 and the second data refresh frequency F2, thereby ensuring that there is a large difference in the display brightness of the screen in the first mode and the second mode. At this time, by adjusting the time length L1 of the light emission phase in one frame refresh time in the first mode to be different from the time length L2 of the light emission phase in one frame refresh time in the second mode, the problem of overcorrection can be avoided.

[0138] It should be noted that the first frequency band and the second frequency band can be continuous frequency bands (for example, the first frequency band is 60Hz to 90Hz and the second frequency band is 90Hz to 120Hz), or they can be non-continuous frequency bands (for example, the first frequency band is 30Hz to 60Hz and the second frequency band is 90Hz to 120Hz). The embodiments of the present invention do not impose specific limitations on this.

[0139] In feasible embodiments, the data refresh frequency of the pixel circuit may include multiple frequency bands. When the data refresh frequency of the pixel circuit changes within any of these frequency bands, the duration of the light-emitting phase remains constant to avoid overcorrection. Conversely, when the data refresh frequency of the pixel circuit switches from one frequency band to another, the duration of the light-emitting phase changes accordingly to compensate for uneven screen brightness and resolve the issue of inconsistent screen brightness.

[0140] The first frequency band and the second frequency band can be any two different frequency bands among the above-mentioned multiple frequency bands, and the embodiments of the present invention do not specifically limit this.

[0141] It should be noted that the data refresh frequency range for each frequency band can be adjusted according to the actual situation. For example, the data refresh frequency range can be 5Hz, 10Hz, 15Hz, 20Hz, 30Hz, 40Hz, 50Hz, 60Hz or 80Hz, etc.

[0142] Accordingly, in this embodiment, the data refresh frequency span of the first frequency band, ΔF1, can be set to 5Hz, 10Hz, 15Hz, 20Hz, 30Hz, 40Hz, 50Hz, 60Hz, or 80Hz; the data refresh frequency span of the second frequency band, ΔF2, can be set to 5Hz, 10Hz, 15Hz, 20Hz, 30Hz, 40Hz, 50Hz, 60Hz, or 80Hz, but is not limited to these.

[0143] It is understandable that the larger the data refresh frequency range of the frequency band, the greater the difference between the first data refresh frequency F1 and the second data refresh frequency F2 in different frequency bands. The difference in screen brightness between the first mode and the second mode is large. Therefore, by adjusting the length of the light emission phase L1 in the first mode and the length of the light emission phase L2 in the second mode, the problem of overcorrection can be avoided.

[0144] The smaller the data refresh frequency range of the frequency band, the smaller the difference between the first data refresh frequency F1 and the second data refresh frequency F2 in different frequency bands. The difference in screen display brightness between the first mode and the second mode is smaller. By adjusting the time length L1 of the light emission phase in one frame refresh time in the first mode to be different from the time length L2 of the light emission phase in one frame refresh time in the second mode, the screen display brightness in the first mode and the second mode can be compensated more precisely.

[0145] Optionally, △F1 = △F2.

[0146] In this way, by setting the data refresh frequency span of the first frequency band to be equal to ΔF1 and the data refresh frequency span of the second frequency band to be equal to ΔF2, for example, the data refresh frequency span of the first frequency band ΔF1 and the data refresh frequency span of the second frequency band ΔF2 are both 10Hz, the setting logic of the first frequency band and the second frequency band can be simplified and easy to implement.

[0147] Optionally, F1 < F2, △F1 < △F2.

[0148] The inventors discovered that when the data refresh frequency of the pixel circuit is high, for example, when the data refresh frequency of the pixel circuit changes from 120Hz to 60Hz, although the data refresh frequency span is large (the data refresh frequency span is 60Hz), the number of holding frames in one data refresh cycle only increases by 1. At this time, the overall duration of all holding frames in one data refresh cycle will not have a large difference, and the degree of attenuation of the light emission brightness of the corresponding light-emitting element will not have a large difference, so the change in the brightness of the screen display is not obvious.

[0149] When the data refresh rate of the pixel circuit is low, for example, when the data refresh rate of the pixel circuit changes from 10Hz to 1Hz, although the data refresh rate span is small (the data refresh rate span is only 9Hz), the number of holding frames in one data refresh cycle increases by more than a hundred. At this time, the overall duration of all holding frames in one data refresh cycle will have a large difference, and the corresponding attenuation of the light emission brightness of the light-emitting element will also have a large difference, and the change in the brightness of the screen display is more obvious.

[0150] Therefore, in this embodiment, when the first data refresh frequency F1 is less than the second data refresh frequency F2, the first data refresh frequency F1 is smaller, and the data refresh frequency span ΔF1 of the first frequency band where the first data refresh frequency F1 is located is smaller. Thus, when the data refresh frequency of the pixel circuit is low, the small range of change in the data refresh frequency of the pixel circuit will exceed the current frequency band. At this time, by adjusting the duration of the light emission phase in a frame refresh time, the brightness of the screen display can be compensated more intensively, thereby better improving the problem of uneven screen display brightness in the display panel when the data refresh frequency of the pixel circuit is low.

[0151] Meanwhile, the second data refresh frequency F2 is relatively large, and the data refresh frequency span ΔF2 of the second frequency band in which the second data refresh frequency F2 is located is relatively large. Therefore, when the data refresh frequency of the pixel circuit is high, the data refresh frequency of the pixel circuit will change by a large range before exceeding the current frequency band. At this time, adjusting the length of the light emission stage in a frame refresh time can avoid the problem of overcorrection.

[0152] Figure 16 This invention provides a driving timing diagram for a pixel circuit in a first mode and a second mode, according to an embodiment of the invention. Figure 17 Another driving timing diagram of a pixel circuit in the first and second modes provided in an embodiment of the present invention. Figure 18 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention, such as Figures 16-18 As shown, optionally, the operation of the pixel circuit includes a data writing frame 31 and a holding frame 32. In the first mode M1, the duration of the light emission phase t20 of the data writing frame 31 is L11, and the duration of the light emission phase t20 of the holding frame 32 is L12; in the second mode M2, the duration of the light emission phase t20 of the data writing frame 31 is L21, and the duration of the light emission phase t20 of the holding frame 32 is L22; wherein, (F1-F2)×(L11-L21)<0; and / or, (F1-F2)×(L12-L22)<0.

[0153] Specifically, such as Figures 16-18As shown, the operation of the pixel circuit includes a data writing frame 31 and a holding frame 32. The data writing frame 31 includes a data writing stage t12, in which a data signal is written to the gate of the driving transistor.

[0154] Furthermore, the data writing frame 31 may also include at least one of the reset phase t11, the initialization phase t13, and the bias adjustment phase t14. The specific process can be referred to the above embodiments, and will not be repeated here.

[0155] Continue to refer to Figures 16-18 Hold frame 32 does not include the data writing phase. By adjusting the number of hold frames within one data refresh cycle, the actual display effect can meet the corresponding data refresh frequency.

[0156] Furthermore, the holding frame 32 may include at least one of the initialization phase t13 and the bias adjustment phase t14, the specific process of which can be referred to the above embodiments and will not be repeated here.

[0157] like Figure 16 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, F1-F2>0. The number of frames 32 held by the pixel circuit in one data refresh cycle under the second mode M2 ​​is greater than the number of frames 32 held by the pixel circuit in one data refresh cycle under the first mode M1. As a result, the overall duration of all held frames 32 in one data refresh cycle under the second mode M2 ​​is longer than the overall duration of all held frames 32 in one data refresh cycle under the first mode M1. Therefore, the degree of attenuation of the light-emitting element driven by the pixel circuit under the second mode M2 ​​is greater than the degree of attenuation of the light-emitting element driven by the pixel circuit under the first mode M1, resulting in the screen display brightness under the second mode M2 ​​being lower than the screen display brightness under the first mode M1. In this embodiment, L11-L21 < 0 can be set. At this time, (F1-F2)×(L11-L21) < 0, so the time length L21 of the light emission stage t20 of the data writing frame 31 in the second mode M2 ​​is greater than the time length L11 of the light emission stage t20 of the data writing frame 31 in the first mode M1. This makes the time length of the light emission stage t20 in one data refresh cycle in the second mode M2 ​​longer, thus making the light emission duration of the light-emitting element in one frame refresh time longer in the second mode M2. This can improve the light emission efficiency of the light-emitting element in the second mode M2, compensate for the screen display brightness in the second mode M2, and finally make the screen display brightness in the second mode M2 ​​approach the screen display brightness in the first mode M1, thereby improving the problem of uneven screen display brightness in the display panel.

[0158] Similarly, in another embodiment, if the first data refresh frequency F1 is less than the second data refresh frequency F2, i.e., F1-F2<0, then the screen display brightness in the second mode M2 ​​will be higher than that in the first mode M1. In this embodiment, L11-L21>0 can be set. At this time, (F1-F2)×(L11-L21)<0, so the duration L21 of the light emission phase t20 of the data writing frame 31 in the second mode M2 ​​is less than the duration L11 of the light emission phase t20 of the data writing frame 31 in the first mode M1. This makes the duration t20 of the light emission phase in one data refresh cycle in the first mode M1 longer, thereby making the light emission duration of the light-emitting element in one data refresh cycle longer in the first mode M1. This improves the light emission efficiency of the light-emitting element in the first mode M1, compensates for the screen display brightness in the first mode M1, and ultimately makes the screen display brightness in the first mode M1 approach the screen display brightness in the second mode M2, thus improving the problem of uneven screen display brightness in the display panel.

[0159] like Figure 17 As shown, optionally, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, i.e. F1-F2>0, L12-L22<0 can also be set. In this case, (F1-F2)×(L12-L22)<0, so the duration L22 of the light emission phase t20 of frame 32 in the second mode M2 ​​is greater than the duration L12 of the light emission phase t20 of frame 32 in the first mode M1. This makes the duration of the light emission phase t20 in one data refresh cycle in the second mode M2 ​​longer, thus making the light emission duration of the light emission element in one frame refresh time longer in the second mode M2. This can improve the light emission efficiency of the light emission element in the second mode M2, compensate for the screen display brightness in the second mode M2, and improve the problem of uneven screen display brightness in the display panel.

[0160] Similarly, in another embodiment, if the first data refresh frequency F1 is less than the second data refresh frequency F2, i.e., F1-F2<0, then L12-L22>0 can be set. In this case, (F1-F2)×(L12-L22)<0, so the duration L22 of the light emission phase t20 of frame 32 in the second mode M2 ​​is less than the duration L12 of the light emission phase t20 of frame 32 in the first mode M1. This results in a longer duration of the light emission phase t20 in one data refresh cycle in the first mode M1, thereby making the light emission duration of the light-emitting element in one data refresh cycle longer in the first mode M1. This improves the light emission efficiency of the light-emitting element in the first mode M1, compensates for the screen display brightness in the first mode M1, and improves the problem of uneven screen display brightness in the display panel.

[0161] like Figure 18As shown, optionally, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, i.e. F1-F2>0, L11-L21<0 and L12-L22<0 can also be set simultaneously. At this time, (F1-F2)×(L11-L21)<0 and (F1-F2)×(L12-L22)<0, which can further extend the time length of the light emission stage t20 in one data refresh cycle under the second mode M2, so that the light emission duration of the light emission element in one frame refresh time under the second mode M2 ​​is longer, thereby improving the light emission efficiency of the light emission element under the second mode M2, compensating for the screen display brightness under the second mode M2, and improving the problem of uneven screen display brightness in the display panel.

[0162] Similarly, if the first data refresh frequency F1 is less than the second data refresh frequency F2, i.e., F1-F2<0, L11-L21>0 and L12-L22>0 can be set simultaneously. At this time, (F1-F2)×(L11-L21)<0 and (F1-F2)×(L12-L22)<0, which can further extend the duration of the light-emitting phase t20 in one data refresh cycle under the first mode M1. This makes the light-emitting element in one data refresh cycle under the first mode M1 emit light for a longer time, improves the light-emitting efficiency of the light-emitting element under the first mode M1, compensates for the brightness of the screen display under the first mode M1, and improves the problem of uneven screen display brightness on the display panel.

[0163] Continue to refer to Figure 18 Optional, |L11-L21|=|L12-L22|.

[0164] Among them, such as Figure 18 As shown, by setting |L11-L21|=|L12-L22|, the variation range of the light emission stage t20 of the data writing frame 31 in the first mode and the light emission stage t20 of the holding frame 32 is the same as the variation range of the light emission stage t20 in the second mode. This setting helps to make the refresh time of one frame of the data writing frame 31 and the holding frame 32 the same in the same mode, making the driving timing of the pixel circuit simpler and easier to implement.

[0165] Figure 19 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention, as shown below. Figure 19 As shown, it is optional that |L11-L21|≠|L12-L22|.

[0166] As mentioned earlier, in both the first and second modes, the pixel circuit includes one data write frame within one data refresh cycle. The difference in the number of hold frames within one data refresh cycle, and the difference in the degree of brightness decay of the display in the first and second modes, are mainly based on the difference in the number of hold frames within one data refresh cycle in the first and second modes.

[0167] Therefore, in this embodiment, as Figure 19 As shown, by setting |L11-L21|≠|L12-L22|, the variation range of the light emission phase t20 of the data writing frame 31 and the light emission phase t20 of the holding frame 32 can be different in the first mode and the second mode. With this setting, the light emission phase t20 can be adjusted for the data writing frame 31 and the holding frame 32 respectively according to the number of holding frames in one data refresh cycle in the first mode and the second mode, which helps to improve the problem of uneven brightness of the display panel.

[0168] In addition, such as Figure 19 As shown, the working processes of data writing frame 31 and holding frame 32 are different. In data writing frame 31, more display signals need to be written to the pixel circuit, while in holding frame 32, fewer display signals need to be written to the pixel circuit. Therefore, the duration of the light-emitting stage t20 can be adjusted separately for data writing frame 31 and holding frame 32. Based on the characteristics of the working processes of data writing frame 31 and holding frame 32, the duration of the light-emitting stage t20 can be adjusted independently for each frame. This improves the flexibility of adjusting the duration of the light-emitting stage t20 in data writing frame 31 and holding frame 32, and helps the display panel meet the usage requirements of more application scenarios.

[0169] Continue to refer to Figure 16 and Figure 17 Alternatively, |L11-L21|=0, |L12-L22|≠0; or, |L11-L21|≠0, |L12-L22|=0.

[0170] Specifically, such as Figure 17 As shown, in this embodiment, L11 = L21 and L12 ≠ L22 can be set. That is, the time length L21 of the light emission stage t20 of the data writing frame 31 in the second mode M2 ​​is equal to the time length L11 of the light emission stage t20 of the data writing frame 31 in the first mode M1. By adjusting the time length of the light emission stage t20 of the holding frame 32 in the first mode M1 and the second mode M2, the brightness of the screen display in different modes can be compensated, thereby improving the problem of uneven screen display brightness in the display panel.

[0171] When the pixel circuit operates at a lower data refresh rate, the number of holding frames in one data refresh cycle is large, and the overall duration of all holding frames in one data refresh cycle is long. This results in a greater attenuation of the light-emitting element's brightness, leading to a noticeable decrease in the overall screen brightness. In this embodiment, by adjusting the duration of the light-emitting phase t20 of the large number of holding frames 32, the screen brightness can be compensated, achieving a significant brightness compensation and thus improving the problem of uneven screen brightness.

[0172] In addition, such as Figure 17 As shown, in data writing frame 31, more display signals need to be written to the pixel circuit, while in holding frame 32, fewer display signals need to be written to the pixel circuit. Therefore, by adjusting the duration of the light-emitting phase t20 of the more numerous holding frames 32, the brightness of the screen display can be compensated. While allowing for a wider range of adjustments, the duration of the pre-stage t10 in data writing frame 31 can be made more stable. This helps to improve the accuracy and stability of the pixel circuit writing data signals to the gate of the driving transistor in data writing frame 31, and reduces the impact on the display effect of the screen panel.

[0173] In another embodiment, such as Figure 16 As shown, L11≠L21 and L12=L22 can be set. That is, the duration L22 of the light-emitting phase t20 of frame 32 in the second mode M2 ​​is equal to the duration L12 of the light-emitting phase t20 of frame 32 in the first mode M1. By adjusting the duration t20 of the light-emitting phase of data writing frame 31 in the first mode M1 and the second mode M2, the brightness of the screen display in different modes can be compensated, thereby improving the problem of uneven screen display brightness in the display panel.

[0174] In this embodiment, when the pixel circuit operates at an arbitrary data refresh rate, only one data write frame 31 is included in one data refresh cycle. By adjusting the duration of the light emission phase t20 of the relatively small number of data write frames 31, the brightness of the screen display can be compensated more precisely, thus improving the problem of uneven screen display brightness. At the same time, adjusting the duration of the light emission phase t20 of the relatively small number of data write frames 31 requires adjusting the number of frames in the driving timing, which helps to reduce the complexity of the driving timing and makes it easier to implement.

[0175] Continue to refer to Figure 17 and Figure 19 Optional, 0≤|L11-L21|<|L12-L22|.

[0176] Specifically, such as Figure 17As shown, 0 = |L11-L21| < |L12-L22|. At this time, L11 = L21, L12 ≠ L22. In the second mode M2, the duration L21 of the light-emitting phase t20 of the data writing frame 31 is equal to the duration L11 of the light-emitting phase t20 of the data writing frame 31 in the first mode M1. By adjusting only the duration t20 of the light-emitting phase of the holding frame 32 in the first mode M1 and the second mode M2, the brightness of the displayed image in different modes can be compensated, improving the problem of uneven brightness in the display panel. With this setting, by adjusting the duration t20 of the light-emitting phase of a relatively large number of holding frames 32, a significant brightness compensation can be achieved. Simultaneously, the duration t10 of the pre-stage in the data writing frame 31 can be made more stable, which helps improve the accuracy and stability of the pixel circuit writing the data signal to the gate of the driving transistor in the data writing frame 31, reducing the impact on the display panel's image display effect.

[0177] In another embodiment, such as Figure 19 As shown, 0 < |L11-L21| < |L12-L22|. At this time, L11 ≠ L21 and L12 ≠ L22. By simultaneously adjusting the time length of the data writing frame 31 and the holding frame 32 in the light emission stage t20, the brightness of the screen display under the first mode M1 and the second mode M2 ​​can be compensated, which can achieve a greater brightness compensation and improve the problem of uneven screen display brightness in the display panel.

[0178] Furthermore, such as Figure 19 As shown, |L11-L21| < |L12-L22|. At this time, the adjustment range of the light emission stage t20 of the holding frame 32 is greater than the adjustment range of the light emission stage t20 of the data writing frame 31. On the one hand, a larger adjustment to the light emission stage t20 of the numerous holding frames 32 can achieve a larger brightness compensation. On the other hand, a smaller adjustment to the light emission stage t20 of the data writing frame 31 can reduce the variation range of the pre-stage t10 in the data writing frame 31. This helps to ensure the accuracy and stability of the pixel circuit in writing the data signal to the gate of the driving transistor in the data writing frame 31, and reduces the impact on the display effect of the display panel.

[0179] Figure 20 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention. Figure 21 This invention provides a driving timing diagram for another pixel circuit in a first mode and a second mode, according to an embodiment of the invention. Figure 22 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention, such as Figures 20-22 As shown, optionally, in the first mode M1, the time length of the pre-stage t10 of the data writing frame 31 is W11, and the time length of the pre-stage t10 of the holding frame 32 is W12; in the second mode M2, the time length of the pre-stage t10 of the data writing frame 31 is W21, and the time length of the pre-stage of the holding frame 32 is W22; wherein, (F1-F2)×(W11-W21)≥0; and / or, (F1-F2)×(W12-W22)≥0.

[0180] Specifically, such as Figure 20 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, F1-F2>0, the duration L21 of the light emission stage t20 of the data writing frame 31 in the second mode M2 ​​is greater than the duration L11 of the light emission stage t20 of the data writing frame 31 in the first mode M1. This compensates for the screen display brightness in the second mode M2 ​​and improves the problem of uneven screen display brightness in the display panel.

[0181] At this point, setting W11-W21>0, i.e. (F1-F2)×(W11-W21)>0, makes the time length W21 of the pre-stage t10 of the data writing frame 31 in the second mode M2 ​​less than the time length W11 of the pre-stage t10 of the data writing frame 31 in the first mode M1. Under the condition that the refresh time of one frame of the data writing frame 31 remains unchanged, sufficient extension space is provided for the time length L21 of the light emission stage t20 of the data writing frame 31 in the second mode M2. Thus, while compensating for the brightness of the screen display in the second mode M2, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals based on a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0182] Similarly, in another embodiment, when the first data refresh frequency F1 is less than the second data refresh frequency F2, F1-F2<0, the duration L21 of the light emission phase t20 of the data writing frame 31 in the second mode M2 ​​is less than the duration L11 of the light emission phase t20 of the data writing frame 31 in the first mode M1, so as to compensate for the screen display brightness in the first mode M1, so that the screen display brightness in the first mode M1 is close to the screen display brightness in the second mode M2, thereby improving the problem of uneven screen display brightness in the display panel.

[0183] At this time, W11-W21<0 can be set, that is, (F1-F2)×(W11-W21)>0, so that the time length W21 of the pre-stage t10 of the data writing frame 31 under the second mode M2 ​​is greater than the time length W11 of the pre-stage t10 of the data writing frame 31 under the first mode M1. Under the condition that the refresh time of one frame of the data writing frame 31 remains unchanged, sufficient extension space can be provided for the time length L11 of the light emission stage t20 of the data writing frame 31 under the first mode M1. Thus, while compensating for the brightness of the screen display under the first mode M1, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals based on a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0184] like Figure 21 As shown, optionally, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, F1-F2>0, the duration L22 of the light emission phase t20 of the frame 32 in the second mode M2 ​​is greater than the duration L12 of the light emission phase t20 of the frame 32 in the first mode M1, so as to compensate for the screen display brightness in the second mode M2 ​​and improve the problem of uneven screen display brightness in the display panel.

[0185] At this point, setting W12-W22>0, i.e. (F1-F2)×(W12-W22)>0, makes the time length W22 of the pre-stage of the holding frame 32 in the second mode M2 ​​less than the time length W12 of the pre-stage t10 of the holding frame 32 in the first mode M1. Under the condition that the refresh time of the holding frame 32 remains unchanged, sufficient extension space is provided for the time length L22 of the light emission stage t20 of the holding frame 32 in the second mode M2. Thus, while compensating for the brightness of the screen display in the second mode M2, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals based on a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0186] Similarly, in another embodiment, when the first data refresh frequency F1 is less than the second data refresh frequency F2, F1-F2<0, the duration L22 of the light emission phase t20 of the frame 32 in the second mode M2 ​​is less than the duration L12 of the light emission phase t20 of the frame 32 in the first mode M1, so as to compensate for the screen display brightness in the first mode M1, so that the screen display brightness in the first mode M1 is close to the screen display brightness in the second mode M2, thereby improving the problem of uneven screen display brightness in the display panel.

[0187] At this point, W12-W22<0 can be set, i.e. (F1-F2)×(W12-W22)>0, so that the time length W22 of the pre-stage of the holding frame 32 under the second mode M2 ​​is greater than the time length W12 of the pre-stage t10 of the holding frame 32 under the first mode M1. Under the condition that the refresh time of the holding frame 32 remains unchanged, sufficient extension space can be provided for the time length L12 of the light emission stage t20 of the holding frame 32 under the first mode M1. Thus, while compensating for the brightness of the screen display under the first mode M1, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals based on a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0188] like Figure 22 As shown, optionally, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, F1-F2>0, the duration L21 of the light emission phase t20 of the data writing frame 31 in the second mode M2 ​​is greater than the duration L11 of the light emission phase t20 of the data writing frame 31 in the first mode M1, and the duration L22 of the light emission phase t20 of the holding frame 32 in the second mode M2 ​​is greater than the duration L12 of the light emission phase t20 of the holding frame 32 in the first mode M1, so as to compensate for the screen display brightness in the second mode M2 ​​and improve the problem of uneven screen display brightness in the display panel.

[0189] At this point, setting W11-W21>0 and W12-W22>0, i.e., (F1-F2)×(W11-W21)>0 and (F1-F2)×(W12-W22)>0, ensures that the time length W21 of the pre-stage t10 of the data writing frame 31 under the second mode M2 ​​is less than the time length W11 of the pre-stage t10 of the data writing frame 31 under the first mode M1, and the time length W22 of the pre-stage of the holding frame 32 under the second mode M2 ​​is less than the time length W12 of the pre-stage t10 of the holding frame 32 under the first mode M1, thereby enabling... Under the condition that the refresh time of one frame of data writing frame 31 and holding frame 32 remains unchanged, sufficient extension space is provided for the duration of the light emission stage t20 of data writing frame 31 and holding frame 32 in the second mode M2. Thus, while compensating for the brightness of the screen display in the second mode M2, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals based on a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0190] Similarly, in another embodiment, when the first data refresh frequency F1 is less than the second data refresh frequency F2, F1-F2<0, the duration L21 of the light emission phase t20 of the data writing frame 31 in the second mode M2 ​​is less than the duration L11 of the light emission phase t20 of the data writing frame 31 in the first mode M1, and the duration L22 of the light emission phase t20 of the holding frame 32 in the second mode M2 ​​is less than the duration L12 of the light emission phase t20 of the holding frame 32 in the first mode M1, so as to compensate for the screen display brightness in the first mode M1, so that the screen display brightness in the first mode M1 is close to the screen display brightness in the second mode M2, thereby improving the problem of uneven screen display brightness in the display panel.

[0191] At this point, W11-W21 < 0 and W12-W22 < 0 can be set, i.e., (F1-F2)×(W11-W21) > 0 and (F1-F2)×(W12-W22) > 0. This ensures that the time length W21 of the pre-stage t10 of the data writing frame 31 under the second mode M2 ​​is greater than the time length W11 of the pre-stage t10 of the data writing frame 31 under the first mode M1, and the time length W22 of the pre-stage of the holding frame 32 under the second mode M2 ​​is greater than the time length W12 of the pre-stage t10 of the holding frame 32 under the first mode M1. Therefore, it is possible to... Under the condition that the refresh time of one frame of data writing frame 31 and holding frame 32 remains unchanged, sufficient extension space is provided for the duration of the light emission stage t20 of data writing frame 31 and holding frame 32 in the first mode M1. Thus, while compensating for the brightness of the screen display in the first mode M1, the driver chip that provides display signals such as light emission control signals to the pixel circuit can provide display signals based on a fixed frame refresh frequency. This helps to reduce the complexity of the display signals output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0192] Continue to refer to Figures 16-19 Optionally, W11 can be set to W21, meaning that the time length W21 of the pre-stage t10 of the data writing frame 31 in the second mode M2 ​​is equal to the time length W11 of the pre-stage t10 of the data writing frame 31 in the first mode M1. In this case, (F1-F2)×(W11-W21)=0. With this setting, the time length of the pre-stage t10 of the data writing frame 31 in the first mode M1 and the second mode M2 ​​remains unchanged. This helps to ensure the accuracy and stability of the data signal writing to the gate of the driving transistor in the pre-stage t10 of the data writing frame 31 in the first mode M1 and the second mode M2, and reduces the impact on the display effect of the display panel.

[0193] Continue to refer to Figures 16-19Optionally, W12 can be set to W22, meaning that the duration W22 of the pre-conception phase of holding frame 32 in the second mode M2 ​​is equal to the duration W12 of the pre-conception phase t10 of holding frame 32 in the first mode M1. In this case, (F1-F2)×(W12-W22)=0. With this setting, the duration t10 of the pre-conception phase of holding frame 32 remains unchanged in both the first mode M1 and the second mode M2. This helps to ensure the stability of the initialization phase t13 and the bias adjustment phase t14 of the pre-conception phase t10 of holding frame 32 in both the first mode M1 and the second mode M2, thus reducing the impact on the display effect of the display panel.

[0194] Continue to refer to Figures 16-19 Optionally, W11 = W21 and W12 = W22 can also be set simultaneously. In this case, (F1-F2)×(W11-W21) = 0 and (F1-F2)×(W12-W22) = 0, which helps to ensure the accuracy and stability of the data signal writing to the gate of the driving transistor in the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2. At the same time, it ensures the stability of the initialization stage t13 and the bias adjustment stage t14 in the pre-stage t10 of the frame 32 under the first mode M1 and the second mode M2, and reduces the impact on the display effect of the display panel.

[0195] Continue to refer to Figure 22 Optional, |W11-W21|=|W12-W22|.

[0196] Among them, such as Figure 22 As shown, by setting |W11-W21|=|W12-W22|, the variation range of the time length of the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2 ​​is the same as the variation range of the time length of the pre-stage t10 of the holding frame 32. This setting helps to make the refresh time of one frame of the data writing frame 31 and the holding frame 32 the same under the same mode, making the driving timing of the pixel circuit simpler and easier to implement.

[0197] Figure 23 Another driving timing diagram of a pixel circuit in the first and second modes provided in the embodiments of the present invention, as shown below. Figure 23 As shown, it is optional that |W11-W21|≠|W12-W22|.

[0198] As mentioned above, the pixel circuit includes one data write frame in one data refresh cycle in both the first mode M1 and the second mode M2. The difference in the number of hold frames in one data refresh cycle, and the difference in the degree of brightness decay of the display in the first mode M1 and the second mode M2, are mainly based on the difference in the number of hold frames 32 in one data refresh cycle of the pixel circuit in the first mode M1 and the second mode M2.

[0199] Therefore, in this embodiment, as Figure 23 As shown, by setting |W11-W21|≠|W12-W22|, the variation range of the time length of the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2 ​​can be different from the variation range of the time length of the pre-stage t10 of the holding frame 32. With this setting, the time length of the pre-stage t10 can be adjusted for the data writing frame 31 and the holding frame 32 respectively according to the number of holding frames 32 in one data refresh cycle under the first mode M1 and the second mode M2, which helps to improve the problem of uneven brightness of the display panel.

[0200] In addition, such as Figure 23 As shown, the operation processes of data writing frame 31 and holding frame 32 are different. In data writing frame 31, more display signals need to be written to the pixel circuit, while in holding frame 32, fewer display signals need to be written to the pixel circuit. Therefore, by adjusting the duration of the pre-stage t10 for data writing frame 31 and holding frame 32 respectively, based on the characteristics of their operation processes, the duration of the pre-stage t10 in data writing frame 31 and holding frame 32 can be adjusted independently. This improves the flexibility of adjusting the duration of the pre-stage t10 in data writing frame 31 and holding frame 32, and helps the display panel meet the usage requirements of more application scenarios.

[0201] Continue to refer to Figure 20 and Figure 21 Alternatively, |W11-W21|=0, |W12-W22|≠0; or, |W11-W21|≠0, |W12-W22|=0.

[0202] Specifically, such as Figure 21As shown, in this embodiment, W11 = W21 and W12 ≠ W22 can be set. In this case, the time length W21 of the pre-stage t10 of the data writing frame 31 under the second mode M2 ​​is equal to the time length W11 of the pre-stage t10 of the data writing frame 31 under the first mode M1. With this setting, the time length of the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2 ​​remains unchanged. This helps to ensure the accuracy and stability of the data signal writing to the gate of the driving transistor in the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2, and reduces the impact on the display effect of the display panel.

[0203] Meanwhile, W12≠W22, that is, by adjusting the time length of the pre-stage t10 of frame 32 under the first mode M1 and the second mode M2, the refresh time of frame 32 remains unchanged under the first mode M1 and the second mode M2. This allows the driver chip to provide display signals based on a fixed frame refresh frequency, which helps to reduce the complexity of the display signal output by the driver chip and reduces the process complexity and manufacturing cost of the driver chip and display panel.

[0204] In another embodiment, such as Figure 20 As shown, W11≠W21 and W12=W22 can be set. In this case, the time length W22 of the pre-conception stage t10 of the holding frame 32 in the second mode M2 ​​is equal to the time length W12 of the pre-conception stage t10 of the holding frame 32 in the first mode M1. With this setting, the time length of the pre-conception stage t10 of the holding frame 32 in the first mode M1 and the second mode M2 ​​remains unchanged. This helps to ensure the stability of the initialization stage t13 and the bias adjustment stage t14 of the holding frame 32 in the first mode M1 and the second mode M2, and reduces the impact on the display effect of the display panel.

[0205] Meanwhile, W11≠W21, that is, by adjusting the time length of the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2, the refresh time of one frame of the data writing frame 31 remains unchanged under the first mode M1 and the second mode M2. This allows the driver chip to provide display signals based on a fixed frame refresh frequency, which helps to reduce the complexity of the display signal output by the driver chip and reduces the process complexity and manufacturing cost of the driver chip and the display panel.

[0206] Continue to refer to Figure 21 and Figure 23 Optional, 0≤|W11-W21|<|W12-W22|.

[0207] Specifically, such as Figure 21As shown, 0 = |W11-W21| < |W12-W22|. At this time, W11 = W21, W12 ≠ W22. In this case, the time length W21 of the pre-stage t10 of the data writing frame 31 under the second mode M2 ​​is equal to the time length W11 of the pre-stage t10 of the data writing frame 31 under the first mode M1. The time length of the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2 ​​remains unchanged. This helps to ensure the accuracy and stability of the data signal writing to the gate of the driving transistor in the pre-stage t10 of the data writing frame 31 under the first mode M1 and the second mode M2, and reduces the impact on the display effect of the display panel. Meanwhile, by adjusting the duration of the pre-stage t10 of the holding frame 32 under the first mode M1 and the second mode M2, the refresh time of one frame of the holding frame 32 remains unchanged under the first mode M1 and the second mode M2. This allows the driver chip to provide display signals based on a fixed frame refresh frequency, which helps to reduce the complexity of the display signals output by the driver chip and reduces the process complexity and manufacturing cost of the driver chip and the display panel.

[0208] In another embodiment, such as Figure 23 As shown, 0 < |W11-W21| < |W12-W22|. At this time, W11 ≠ W21 and W12 ≠ W22. By simultaneously adjusting the time length of the data writing frame 31 and the holding frame 32 in the pre-stage t10, the refresh time of the entire data writing frame 31 and the holding frame 32 can remain unchanged under the first mode M1 and the second mode M2. This allows the driver chip to provide display signals based on a fixed frame refresh frequency, which helps to reduce the complexity of the display signal output by the driver chip and reduces the process complexity and manufacturing cost of the driver chip and the display panel.

[0209] Furthermore, such as Figure 23 As shown, |W11-W21| < |W12-W22|. At this time, the adjustment range of the time length of the pre-stage t10 of the holding frame 32 is greater than the adjustment range of the time length of the pre-stage t10 of the data writing frame 31. Under the condition that the refresh time of one frame of the data writing frame 31 and the holding frame 32 remains unchanged in the first mode M1 and the second mode M2, a larger adjustment can be made to the time length of the light emission stage t20 of the large number of holding frames 32, which is conducive to achieving a larger brightness compensation. At the same time, the variation range of the time length of the pre-stage t10 in the data writing frame 31 is smaller, which is conducive to ensuring the accuracy and stability of the pixel circuit writing the data signal to the gate of the driving transistor in the data writing frame 31, and reducing the impact on the display effect of the display panel.

[0210] Continue to refer to Figures 20-23Optionally, W11+L11=W21+L21; and / or, W12+L12=W22+L22.

[0211] Specifically, such as Figures 20-23 As shown, the sum of the time length W11 of the pre-stage t10 of the data writing frame 31 under the first mode M1 and the time length L11 of the light emission stage t20 of the data writing frame 31 under the first mode M1 is the refresh time of one frame of the data writing frame 31 under the first mode M1. Similarly, the sum of the time length W21 of the pre-stage t10 of the data writing frame 31 under the second mode M2 ​​and the time length L21 of the light emission stage t20 of the data writing frame 31 under the second mode M2 ​​is the refresh time of one frame of the data writing frame 31 under the second mode M2.

[0212] In this embodiment, by setting W11+L11=W21+L21, the refresh time of one frame of data writing frame 31 under the first mode M1 and the refresh time of one frame of data writing frame 31 under the second mode M2 ​​can be made equal. That is, the refresh time of one frame of data writing frame 31 is the same when the pixel circuit is working in the first mode M1 and when the pixel circuit is working in the second mode M2. At this time, the driver chip can provide display signals to the pixel circuit according to the fixed refresh time of one frame of data writing frame 31, which helps to reduce the complexity of the display signal output by the driver chip, and thus reduces the process complexity and manufacturing cost of the driver chip and the display panel.

[0213] Continue to refer to Figures 20-23 As shown, in another embodiment, W12+L12=W22+L22 can be set so that the refresh time of one frame of the holding frame 32 in the first mode M1 is equal to the refresh time of one frame of the holding frame 32 in the second mode M2. That is, the refresh time of one frame of the holding frame 32 is the same when the pixel circuit is working in the first mode M1 and when the pixel circuit is working in the second mode M2. At this time, the driver chip can provide a display signal to the pixel circuit according to the fixed refresh time of the holding frame 32, which helps to reduce the complexity of the display signal output by the driver chip, and thus reduces the process complexity and manufacturing cost of the driver chip and the display panel.

[0214] Continue to refer to Figures 20-23As shown, in another embodiment, W11+L11=W21+L21 and W12+L12=W22+L22 can be set simultaneously, so that the refresh time of one frame of data writing frame 31 under the first mode M1 is equal to the refresh time of one frame of data writing frame 31 under the second mode M2, and the refresh time of one frame of holding frame 32 under the first mode M1 is equal to the refresh time of one frame of holding frame 32 under the second mode M2. At this time, the driver chip can provide display signals to the pixel circuit according to the fixed refresh time of data writing frame 31 and holding frame 32, which is beneficial to further reduce the complexity of the display signal output by the driver chip, thereby reducing the process complexity and manufacturing cost of the driver chip and the display panel.

[0215] Continue to refer to Figure 19 Optionally, F1 > F2, W11 + L11 < W21 + L21; and / or, F1 > F2, W12 + L12 < W22 + L22.

[0216] Specifically, such as Figure 19 As shown, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration L21 of the light emission stage t20 of the data writing frame 31 in the second mode M2 ​​is greater than the duration L11 of the light emission stage t20 of the data writing frame 31 in the first mode M1, so as to compensate for the screen display brightness in the second mode M2, so that the screen display brightness in the second mode M2 ​​is close to the screen display brightness in the first mode M1, thereby improving the problem of uneven screen display brightness in the display panel.

[0217] In this embodiment, W11+L11 < W21+L21 is set, meaning that the refresh time of one frame of data writing frame 31 under the first mode M1 is less than the refresh time of one frame of data writing frame 31 under the second mode M2. Under the condition that L21>L11, that is, while compensating for the brightness of the screen display under the second mode M2, the time length W11 of the pre-stage t10 of data writing frame 31 under the first mode M1 and the time length W21 of the pre-stage t10 of data writing frame 31 under the second mode M2 ​​do not need to be adjusted accordingly. This helps to ensure the accuracy and stability of the pixel circuit writing the data signal to the gate of the driving transistor in the pre-stage t10 under the first mode M1 and the second mode M2, and avoids affecting the screen display effect of the display panel.

[0218] Continue to refer to Figure 19In another embodiment, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration L22 of the light emission phase t20 of the holding frame 32 in the second mode M2 ​​is greater than the duration L12 of the light emission phase t20 of the holding frame 32 in the first mode M1, so as to compensate for the screen display brightness in the second mode M2, so that the screen display brightness in the second mode M2 ​​is close to the screen display brightness in the first mode M1, thereby improving the problem of uneven screen display brightness in the display panel.

[0219] In this embodiment, W12+L12 < W22+L22 can be set, that is, the refresh time of one frame of the holding frame 32 under the first mode M1 is less than the refresh time of one frame of the holding frame 32 under the second mode M2. Under the condition that L22>L12, that is, while compensating for the brightness of the screen display under the second mode M2, the time length W12 of the pre-stage t10 of the holding frame 32 under the first mode M1 and the time length W22 of the pre-stage of the holding frame 32 under the second mode M2 ​​do not need to be adjusted accordingly. This helps to ensure the stability of the initialization stage t13 and the bias adjustment stage t14 of the pixel circuit in the pre-stage t10 of the holding frame 32 under the first mode M1 and the second mode M2, and reduces the impact on the display effect of the screen display panel.

[0220] Continue to refer to Figure 19 In another embodiment, when the first data refresh frequency F1 is greater than the second data refresh frequency F2, the duration L21 of the light emission phase t20 of the data writing frame 31 in the second mode M2 ​​is greater than the duration L11 of the light emission phase t20 of the data writing frame 31 in the first mode M1. At the same time, the duration L22 of the light emission phase t20 of the holding frame 32 in the second mode M2 ​​is greater than the duration L12 of the light emission phase t20 of the holding frame 32 in the first mode M1. This is to compensate for the screen display brightness in the second mode M2, so that the screen display brightness in the second mode M2 ​​is close to the screen display brightness in the first mode M1, thereby improving the problem of uneven screen display brightness in the display panel.

[0221] In this embodiment, W11+L11 < W21+L21 and W12+L12 < W22+L22 can be set simultaneously. That is, the refresh time of one frame of data writing frame 31 under the first mode M1 is less than the refresh time of one frame of data writing frame 31 under the second mode M2, and the refresh time of one frame of holding frame 32 under the first mode M1 is less than the refresh time of one frame of holding frame 32 under the second mode M2. Thus, under the condition that L21>L11 and L22>L12, the time length W11 of the pre-stage t10 of data writing frame 31 under the first mode M1 and the time length W21 of the pre-stage t10 of data writing frame 31 under the second mode M2 ​​do not need to be adjusted. Adjustments should be made, and the time length W12 of the pre-conception stage t10 of the holding frame 32 in the first mode M1 and the time length W22 of the pre-conception stage of the holding frame 32 in the second mode M2 ​​do not need to be adjusted accordingly. This helps to ensure the accuracy and stability of the data signal writing to the gate of the driving transistor in the pre-conception stage t10 of the pixel circuit in the first mode M1 and the second mode M2, avoiding affecting the display effect of the display panel. At the same time, it helps to ensure the stability of the initialization stage t13 and the bias adjustment stage t14 of the holding frame 32 in the first mode M1 and the second mode M2, reducing the impact on the display effect of the display panel.

[0222] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 24 As shown, the display device 40 includes the display panel 41 described in any embodiment of the present invention. Therefore, the display device 40 provided by the embodiments of the present invention has the technical effects of the technical solutions in any of the above embodiments. The explanations of the same or corresponding structures and terms as described in the above embodiments will not be repeated here.

[0223] The display device 40 provided in this embodiment of the invention can be Figure 24 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0224] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0225] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The operation of the pixel circuit includes a first mode and a second mode. In the first mode, the data refresh frequency of the pixel circuit is a first data refresh frequency F1, and in the second mode, the data refresh frequency of the pixel circuit is a second data refresh frequency F2. The refresh time of the pixel circuit per frame includes a pre-processing stage and a light-emitting stage. In the first mode, the duration of the light-emitting stage is L1, and in the second mode, the duration of the light-emitting stage is L2. (F1-F2)×(L1-L2)<0; The operation of the pixel circuit includes writing data frames and holding frames; In the first mode, the duration of the light emission phase of the data writing frame is L11, and the duration of the light emission phase of the holding frame is L12. In the second mode, the duration of the light-emitting phase of the data writing frame is L21, and the duration of the light-emitting phase of the holding frame is L22; wherein, 0≤|L11-L21|<|L12-L22|; In the first mode, the duration of the pre-stage of the data writing frame is W11, and the duration of the pre-stage of the holding frame is W12. In the second mode, the duration of the pre-processing phase of the data writing frame is W21, and the duration of the pre-processing phase of the holding frame is W22; wherein, |W11-W21|=0, |W12-W22|≠0; or, |W11-W21|≠0, |W12-W22|=0.

2. The display panel according to claim 1, characterized in that, The operation of the pixel circuit includes a first time period and a second time period; During the first time period, the pixel circuit operates in the first mode, and during the second time period, the pixel circuit operates in the second mode.

3. The display panel according to claim 1, characterized in that, The display panel includes a first display area and a second display area; The pixel circuit of the first display area operates in the first mode, and the pixel circuit of the second display area operates in the second mode.

4. The display panel according to claim 1, characterized in that, F1 > F2, F1 / F2 > L2 / L1.

5. The display panel according to claim 1, characterized in that, F1 > F2, L1 / L2 > 1 / 2.

6. The display panel according to claim 1, characterized in that, In the first mode, the duration of the pre-stage is W1; in the second mode, the duration of the pre-stage is W2; wherein... (F1-F2)×(W1-W2)≥0.

7. The display panel according to claim 6, characterized in that, W1+L1=W2+L2.

8. The display panel according to claim 6, characterized in that, F1 > F2, W1 + L1 < W2 + L2.

9. The display panel according to claim 1, characterized in that, The data refresh frequency of the pixel circuit includes a first frequency band and a second frequency band. The data refresh frequency span of the first frequency band is ΔF1, and the duration of the light emission stage within the second frequency band remains unchanged. The data refresh frequency span of the first frequency band is ΔF2, and the duration of the light emission stage within the second frequency band remains unchanged. The first data refresh frequency F1 is located in the first frequency band, and the second data refresh frequency F2 is located in the second frequency band.

10. The display panel according to claim 9, characterized in that, △F1=△F2.

11. The display panel according to claim 9, characterized in that, F1 < F2, △F1 < △F2.

12. The display panel according to claim 1, characterized in that, (F1-F2)×(W11-W21)≥0; and / or, (F1-F2)×(W12-W22)≥0.

13. The display panel according to claim 1, characterized in that, 0 ≤ |W11-W21| < |W12-W22|.

14. The display panel according to claim 12, characterized in that, W11+L11=W21+L21; and / or, W12+L12=W22+L22.

15. The display panel according to claim 12, characterized in that, F1 > F2, W11 + L11 < W21 + L21; and / or, F1>F2, W12+L12<W22+L22.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-15.

Images